[PATCH] mark struct file_operations const 1
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / i386 / kernel / msr.c
CommitLineData
1da177e4
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1/* ----------------------------------------------------------------------- *
2 *
3 * Copyright 2000 H. Peter Anvin - All Rights Reserved
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139,
8 * USA; either version 2 of the License, or (at your option) any later
9 * version; incorporated herein by reference.
10 *
11 * ----------------------------------------------------------------------- */
12
13/*
14 * msr.c
15 *
16 * x86 MSR access device
17 *
18 * This device is accessed by lseek() to the appropriate register number
19 * and then read/write in chunks of 8 bytes. A larger size means multiple
20 * reads or writes of the same register.
21 *
22 * This driver uses /dev/cpu/%d/msr where %d is the minor number, and on
23 * an SMP box will direct the access to CPU %d.
24 */
25
26#include <linux/module.h>
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27
28#include <linux/types.h>
29#include <linux/errno.h>
30#include <linux/fcntl.h>
31#include <linux/init.h>
32#include <linux/poll.h>
33#include <linux/smp.h>
34#include <linux/smp_lock.h>
35#include <linux/major.h>
36#include <linux/fs.h>
37#include <linux/device.h>
38#include <linux/cpu.h>
39#include <linux/notifier.h>
40
41#include <asm/processor.h>
42#include <asm/msr.h>
43#include <asm/uaccess.h>
44#include <asm/system.h>
45
8874b414 46static struct class *msr_class;
1da177e4 47
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48static inline int wrmsr_eio(u32 reg, u32 eax, u32 edx)
49{
50 int err;
51
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ZA
52 err = wrmsr_safe(reg, eax, edx);
53 if (err)
54 err = -EIO;
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55 return err;
56}
57
58static inline int rdmsr_eio(u32 reg, u32 *eax, u32 *edx)
59{
60 int err;
61
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ZA
62 err = rdmsr_safe(reg, eax, edx);
63 if (err)
64 err = -EIO;
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65 return err;
66}
67
68#ifdef CONFIG_SMP
69
70struct msr_command {
71 int cpu;
72 int err;
73 u32 reg;
74 u32 data[2];
75};
76
77static void msr_smp_wrmsr(void *cmd_block)
78{
79 struct msr_command *cmd = (struct msr_command *)cmd_block;
80
81 if (cmd->cpu == smp_processor_id())
82 cmd->err = wrmsr_eio(cmd->reg, cmd->data[0], cmd->data[1]);
83}
84
85static void msr_smp_rdmsr(void *cmd_block)
86{
87 struct msr_command *cmd = (struct msr_command *)cmd_block;
88
89 if (cmd->cpu == smp_processor_id())
90 cmd->err = rdmsr_eio(cmd->reg, &cmd->data[0], &cmd->data[1]);
91}
92
93static inline int do_wrmsr(int cpu, u32 reg, u32 eax, u32 edx)
94{
95 struct msr_command cmd;
96 int ret;
97
98 preempt_disable();
99 if (cpu == smp_processor_id()) {
100 ret = wrmsr_eio(reg, eax, edx);
101 } else {
102 cmd.cpu = cpu;
103 cmd.reg = reg;
104 cmd.data[0] = eax;
105 cmd.data[1] = edx;
106
107 smp_call_function(msr_smp_wrmsr, &cmd, 1, 1);
108 ret = cmd.err;
109 }
110 preempt_enable();
111 return ret;
112}
113
114static inline int do_rdmsr(int cpu, u32 reg, u32 * eax, u32 * edx)
115{
116 struct msr_command cmd;
117 int ret;
118
119 preempt_disable();
120 if (cpu == smp_processor_id()) {
121 ret = rdmsr_eio(reg, eax, edx);
122 } else {
123 cmd.cpu = cpu;
124 cmd.reg = reg;
125
126 smp_call_function(msr_smp_rdmsr, &cmd, 1, 1);
127
128 *eax = cmd.data[0];
129 *edx = cmd.data[1];
130
131 ret = cmd.err;
132 }
133 preempt_enable();
134 return ret;
135}
136
137#else /* ! CONFIG_SMP */
138
139static inline int do_wrmsr(int cpu, u32 reg, u32 eax, u32 edx)
140{
141 return wrmsr_eio(reg, eax, edx);
142}
143
144static inline int do_rdmsr(int cpu, u32 reg, u32 *eax, u32 *edx)
145{
146 return rdmsr_eio(reg, eax, edx);
147}
148
149#endif /* ! CONFIG_SMP */
150
151static loff_t msr_seek(struct file *file, loff_t offset, int orig)
152{
153 loff_t ret = -EINVAL;
154
155 lock_kernel();
156 switch (orig) {
157 case 0:
158 file->f_pos = offset;
159 ret = file->f_pos;
160 break;
161 case 1:
162 file->f_pos += offset;
163 ret = file->f_pos;
164 }
165 unlock_kernel();
166 return ret;
167}
168
169static ssize_t msr_read(struct file *file, char __user * buf,
170 size_t count, loff_t * ppos)
171{
172 u32 __user *tmp = (u32 __user *) buf;
173 u32 data[2];
1da177e4 174 u32 reg = *ppos;
aab4c5a5 175 int cpu = iminor(file->f_path.dentry->d_inode);
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176 int err;
177
178 if (count % 8)
179 return -EINVAL; /* Invalid chunk size */
180
6926d570 181 for (; count; count -= 8) {
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182 err = do_rdmsr(cpu, reg, &data[0], &data[1]);
183 if (err)
184 return err;
185 if (copy_to_user(tmp, &data, 8))
186 return -EFAULT;
187 tmp += 2;
188 }
189
190 return ((char __user *)tmp) - buf;
191}
192
193static ssize_t msr_write(struct file *file, const char __user *buf,
194 size_t count, loff_t *ppos)
195{
196 const u32 __user *tmp = (const u32 __user *)buf;
197 u32 data[2];
1da177e4 198 u32 reg = *ppos;
aab4c5a5 199 int cpu = iminor(file->f_path.dentry->d_inode);
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200 int err;
201
202 if (count % 8)
203 return -EINVAL; /* Invalid chunk size */
204
f475ff35 205 for (; count; count -= 8) {
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206 if (copy_from_user(&data, tmp, 8))
207 return -EFAULT;
208 err = do_wrmsr(cpu, reg, data[0], data[1]);
209 if (err)
210 return err;
211 tmp += 2;
212 }
213
214 return ((char __user *)tmp) - buf;
215}
216
217static int msr_open(struct inode *inode, struct file *file)
218{
aab4c5a5 219 unsigned int cpu = iminor(file->f_path.dentry->d_inode);
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220 struct cpuinfo_x86 *c = &(cpu_data)[cpu];
221
222 if (cpu >= NR_CPUS || !cpu_online(cpu))
223 return -ENXIO; /* No such CPU */
224 if (!cpu_has(c, X86_FEATURE_MSR))
225 return -EIO; /* MSR not supported */
226
227 return 0;
228}
229
230/*
231 * File operations we support
232 */
233static struct file_operations msr_fops = {
234 .owner = THIS_MODULE,
235 .llseek = msr_seek,
236 .read = msr_read,
237 .write = msr_write,
238 .open = msr_open,
239};
240
a271aaf1 241static int msr_device_create(int i)
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242{
243 int err = 0;
a271aaf1 244 struct device *dev;
1da177e4 245
a271aaf1
GKH
246 dev = device_create(msr_class, NULL, MKDEV(MSR_MAJOR, i), "msr%d",i);
247 if (IS_ERR(dev))
248 err = PTR_ERR(dev);
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249 return err;
250}
251
e09793bb
AM
252static int msr_class_cpu_callback(struct notifier_block *nfb,
253 unsigned long action, void *hcpu)
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254{
255 unsigned int cpu = (unsigned long)hcpu;
256
257 switch (action) {
258 case CPU_ONLINE:
a271aaf1 259 msr_device_create(cpu);
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260 break;
261 case CPU_DEAD:
a271aaf1 262 device_destroy(msr_class, MKDEV(MSR_MAJOR, cpu));
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263 break;
264 }
265 return NOTIFY_OK;
266}
267
74b85f37 268static struct notifier_block __cpuinitdata msr_class_cpu_notifier =
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269{
270 .notifier_call = msr_class_cpu_callback,
271};
272
273static int __init msr_init(void)
274{
275 int i, err = 0;
276 i = 0;
277
278 if (register_chrdev(MSR_MAJOR, "cpu/msr", &msr_fops)) {
279 printk(KERN_ERR "msr: unable to get major %d for msr\n",
280 MSR_MAJOR);
281 err = -EBUSY;
282 goto out;
283 }
8874b414 284 msr_class = class_create(THIS_MODULE, "msr");
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285 if (IS_ERR(msr_class)) {
286 err = PTR_ERR(msr_class);
287 goto out_chrdev;
288 }
289 for_each_online_cpu(i) {
a271aaf1 290 err = msr_device_create(i);
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291 if (err != 0)
292 goto out_class;
293 }
e09793bb 294 register_hotcpu_notifier(&msr_class_cpu_notifier);
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295
296 err = 0;
297 goto out;
298
299out_class:
300 i = 0;
301 for_each_online_cpu(i)
a271aaf1 302 device_destroy(msr_class, MKDEV(MSR_MAJOR, i));
8874b414 303 class_destroy(msr_class);
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304out_chrdev:
305 unregister_chrdev(MSR_MAJOR, "cpu/msr");
306out:
307 return err;
308}
309
310static void __exit msr_exit(void)
311{
312 int cpu = 0;
313 for_each_online_cpu(cpu)
a271aaf1 314 device_destroy(msr_class, MKDEV(MSR_MAJOR, cpu));
8874b414 315 class_destroy(msr_class);
1da177e4 316 unregister_chrdev(MSR_MAJOR, "cpu/msr");
e09793bb 317 unregister_hotcpu_notifier(&msr_class_cpu_notifier);
1da177e4
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318}
319
320module_init(msr_init);
321module_exit(msr_exit)
322
323MODULE_AUTHOR("H. Peter Anvin <hpa@zytor.com>");
324MODULE_DESCRIPTION("x86 generic MSR driver");
325MODULE_LICENSE("GPL");