[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / i386 / kernel / irq_32.c

/*
 *	linux/arch/i386/kernel/irq.c
 *
 *	Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
 *
 * This file contains the lowest level x86-specific interrupt
 * entry, irq-stacks and irq statistics code. All the remaining
 * irq logic is done by the generic kernel/irq/ code and
 * by the x86-specific irq controller code. (e.g. i8259.c and
 * io_apic.c.)
 */

#include <linux/module.h>
#include <linux/seq_file.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/notifier.h>
#include <linux/cpu.h>
#include <linux/delay.h>

#include <asm/apic.h>
#include <asm/uaccess.h>

DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
EXPORT_PER_CPU_SYMBOL(irq_stat);

DEFINE_PER_CPU(struct pt_regs *, irq_regs);
EXPORT_PER_CPU_SYMBOL(irq_regs);

/*
 * 'what should we do if we get a hw irq event on an illegal vector'.
 * each architecture has to answer this themselves.
 */
void ack_bad_irq(unsigned int irq)
{
	printk(KERN_ERR "unexpected IRQ trap at vector %02x\n", irq);

#ifdef CONFIG_X86_LOCAL_APIC
	/*
	 * Currently unexpected vectors happen only on SMP and APIC.
	 * We _must_ ack these because every local APIC has only N
	 * irq slots per priority level, and a 'hanging, unacked' IRQ
	 * holds up an irq slot - in excessive cases (when multiple
	 * unexpected vectors occur) that might lock up the APIC
	 * completely.
	 * But only ack when the APIC is enabled -AK
	 */
	if (cpu_has_apic)
		ack_APIC_irq();
#endif
}

#ifdef CONFIG_4KSTACKS
/*
 * per-CPU IRQ handling contexts (thread information and stack)
 */
union irq_ctx {
	struct thread_info      tinfo;
	u32                     stack[THREAD_SIZE/sizeof(u32)];
};

static union irq_ctx *hardirq_ctx[NR_CPUS] __read_mostly;
static union irq_ctx *softirq_ctx[NR_CPUS] __read_mostly;
#endif

/*
 * do_IRQ handles all normal device IRQ's (the special
 * SMP cross-CPU interrupts have their own specific
 * handlers).
 */
fastcall unsigned int do_IRQ(struct pt_regs *regs)
{	
	struct pt_regs *old_regs;
	/* high bit used in ret_from_ code */
	int irq = ~regs->orig_eax;
	struct irq_desc *desc = irq_desc + irq;
#ifdef CONFIG_4KSTACKS
	union irq_ctx *curctx, *irqctx;
	u32 *isp;
#endif

	if (unlikely((unsigned)irq >= NR_IRQS)) {
		printk(KERN_EMERG "%s: cannot handle IRQ %d\n",
					__FUNCTION__, irq);
		BUG();
	}

	old_regs = set_irq_regs(regs);
	irq_enter();
#ifdef CONFIG_DEBUG_STACKOVERFLOW
	/* Debugging check for stack overflow: is there less than 1KB free? */
	{
		long esp;

		__asm__ __volatile__("andl %%esp,%0" :
					"=r" (esp) : "0" (THREAD_SIZE - 1));
		if (unlikely(esp < (sizeof(struct thread_info) + STACK_WARN))) {
			printk("do_IRQ: stack overflow: %ld\n",
				esp - sizeof(struct thread_info));
			dump_stack();
		}
	}
#endif

#ifdef CONFIG_4KSTACKS

	curctx = (union irq_ctx *) current_thread_info();
	irqctx = hardirq_ctx[smp_processor_id()];

	/*
	 * this is where we switch to the IRQ stack. However, if we are
	 * already using the IRQ stack (because we interrupted a hardirq
	 * handler) we can't do that and just have to keep using the
	 * current stack (which is the irq stack already after all)
	 */
	if (curctx != irqctx) {
		int arg1, arg2, ebx;

		/* build the stack frame on the IRQ stack */
		isp = (u32*) ((char*)irqctx + sizeof(*irqctx));
		irqctx->tinfo.task = curctx->tinfo.task;
		irqctx->tinfo.previous_esp = current_stack_pointer;

		/*
		 * Copy the softirq bits in preempt_count so that the
		 * softirq checks work in the hardirq context.
		 */
		irqctx->tinfo.preempt_count =
			(irqctx->tinfo.preempt_count & ~SOFTIRQ_MASK) |
			(curctx->tinfo.preempt_count & SOFTIRQ_MASK);

		asm volatile(
			"       xchgl  %%ebx,%%esp      \n"
			"       call   *%%edi           \n"
			"       movl   %%ebx,%%esp      \n"
			: "=a" (arg1), "=d" (arg2), "=b" (ebx)
			:  "0" (irq),   "1" (desc),  "2" (isp),
			   "D" (desc->handle_irq)
			: "memory", "cc"
		);
	} else
#endif
		desc->handle_irq(irq, desc);

	irq_exit();
	set_irq_regs(old_regs);
	return 1;
}

#ifdef CONFIG_4KSTACKS

static char softirq_stack[NR_CPUS * THREAD_SIZE]
		__attribute__((__section__(".bss.page_aligned")));

static char hardirq_stack[NR_CPUS * THREAD_SIZE]
		__attribute__((__section__(".bss.page_aligned")));

/*
 * allocate per-cpu stacks for hardirq and for softirq processing
 */
void irq_ctx_init(int cpu)
{
	union irq_ctx *irqctx;

	if (hardirq_ctx[cpu])
		return;

	irqctx = (union irq_ctx*) &hardirq_stack[cpu*THREAD_SIZE];
	irqctx->tinfo.task              = NULL;
	irqctx->tinfo.exec_domain       = NULL;
	irqctx->tinfo.cpu               = cpu;
	irqctx->tinfo.preempt_count     = HARDIRQ_OFFSET;
	irqctx->tinfo.addr_limit        = MAKE_MM_SEG(0);

	hardirq_ctx[cpu] = irqctx;

	irqctx = (union irq_ctx*) &softirq_stack[cpu*THREAD_SIZE];
	irqctx->tinfo.task              = NULL;
	irqctx->tinfo.exec_domain       = NULL;
	irqctx->tinfo.cpu               = cpu;
	irqctx->tinfo.preempt_count     = 0;
	irqctx->tinfo.addr_limit        = MAKE_MM_SEG(0);

	softirq_ctx[cpu] = irqctx;

	printk("CPU %u irqstacks, hard=%p soft=%p\n",
		cpu,hardirq_ctx[cpu],softirq_ctx[cpu]);
}

void irq_ctx_exit(int cpu)
{
	hardirq_ctx[cpu] = NULL;
}

extern asmlinkage void __do_softirq(void);

asmlinkage void do_softirq(void)
{
	unsigned long flags;
	struct thread_info *curctx;
	union irq_ctx *irqctx;
	u32 *isp;

	if (in_interrupt())
		return;

	local_irq_save(flags);

	if (local_softirq_pending()) {
		curctx = current_thread_info();
		irqctx = softirq_ctx[smp_processor_id()];
		irqctx->tinfo.task = curctx->task;
		irqctx->tinfo.previous_esp = current_stack_pointer;

		/* build the stack frame on the softirq stack */
		isp = (u32*) ((char*)irqctx + sizeof(*irqctx));

		asm volatile(
			"       xchgl   %%ebx,%%esp     \n"
			"       call    __do_softirq    \n"
			"       movl    %%ebx,%%esp     \n"
			: "=b"(isp)
			: "0"(isp)
			: "memory", "cc", "edx", "ecx", "eax"
		);
		/*
		 * Shouldnt happen, we returned above if in_interrupt():
	 	 */
		WARN_ON_ONCE(softirq_count());
	}

	local_irq_restore(flags);
}

EXPORT_SYMBOL(do_softirq);
#endif

/*
 * Interrupt statistics:
 */

atomic_t irq_err_count;

/*
 * /proc/interrupts printing:
 */

int show_interrupts(struct seq_file *p, void *v)
{
	int i = *(loff_t *) v, j;
	struct irqaction * action;
	unsigned long flags;

	if (i == 0) {
		seq_printf(p, "           ");
		for_each_online_cpu(j)
			seq_printf(p, "CPU%-8d",j);
		seq_putc(p, '\n');
	}

	if (i < NR_IRQS) {
		spin_lock_irqsave(&irq_desc[i].lock, flags);
		action = irq_desc[i].action;
		if (!action)
			goto skip;
		seq_printf(p, "%3d: ",i);
#ifndef CONFIG_SMP
		seq_printf(p, "%10u ", kstat_irqs(i));
#else
		for_each_online_cpu(j)
			seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
#endif
		seq_printf(p, " %8s", irq_desc[i].chip->name);
		seq_printf(p, "-%-8s", irq_desc[i].name);
		seq_printf(p, "  %s", action->name);

		for (action=action->next; action; action = action->next)
			seq_printf(p, ", %s", action->name);

		seq_putc(p, '\n');
skip:
		spin_unlock_irqrestore(&irq_desc[i].lock, flags);
	} else if (i == NR_IRQS) {
		seq_printf(p, "NMI: ");
		for_each_online_cpu(j)
			seq_printf(p, "%10u ", nmi_count(j));
		seq_putc(p, '\n');
#ifdef CONFIG_X86_LOCAL_APIC
		seq_printf(p, "LOC: ");
		for_each_online_cpu(j)
			seq_printf(p, "%10u ",
				per_cpu(irq_stat,j).apic_timer_irqs);
		seq_putc(p, '\n');
#endif
		seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
#if defined(CONFIG_X86_IO_APIC)
		seq_printf(p, "MIS: %10u\n", atomic_read(&irq_mis_count));
#endif
	}
	return 0;
}

#ifdef CONFIG_HOTPLUG_CPU
#include <mach_apic.h>

void fixup_irqs(cpumask_t map)
{
	unsigned int irq;
	static int warned;

	for (irq = 0; irq < NR_IRQS; irq++) {
		cpumask_t mask;
		if (irq == 2)
			continue;

		cpus_and(mask, irq_desc[irq].affinity, map);
		if (any_online_cpu(mask) == NR_CPUS) {
			printk("Breaking affinity for irq %i\n", irq);
			mask = map;
		}
		if (irq_desc[irq].chip->set_affinity)
			irq_desc[irq].chip->set_affinity(irq, mask);
		else if (irq_desc[irq].action && !(warned++))
			printk("Cannot set affinity for irq %i\n", irq);
	}

#if 0
	barrier();
	/* Ingo Molnar says: "after the IO-APIC masks have been redirected
	   [note the nop - the interrupt-enable boundary on x86 is two
	   instructions from sti] - to flush out pending hardirqs and
	   IPIs. After this point nothing is supposed to reach this CPU." */
	__asm__ __volatile__("sti; nop; cli");
	barrier();
#else
	/* That doesn't seem sufficient.  Give it 1ms. */
	local_irq_enable();
	mdelay(1);
	local_irq_disable();
#endif
}
#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/i386/kernel/irq.c
	3	*
	4	* Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
	5	*
	6	* This file contains the lowest level x86-specific interrupt
	7	* entry, irq-stacks and irq statistics code. All the remaining
	8	* irq logic is done by the generic kernel/irq/ code and
	9	* by the x86-specific irq controller code. (e.g. i8259.c and
	10	* io_apic.c.)
	11	*/
	12
1da177e4 LT	13	#include <linux/module.h>
	14	#include <linux/seq_file.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/kernel_stat.h>
f3705136 ZM	17	#include <linux/notifier.h>
	18	#include <linux/cpu.h>
	19	#include <linux/delay.h>
1da177e4	20
e05d723f TG	21	#include <asm/apic.h>
	22	#include <asm/uaccess.h>
	23
f34e3b61	24	DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
1da177e4 LT	25	EXPORT_PER_CPU_SYMBOL(irq_stat);
1da177e4 LT	26
7c3576d2 JF	27	DEFINE_PER_CPU(struct pt_regs *, irq_regs);
	28	EXPORT_PER_CPU_SYMBOL(irq_regs);
	29
1da177e4 LT	30	/*
	31	* 'what should we do if we get a hw irq event on an illegal vector'.
	32	* each architecture has to answer this themselves.
	33	*/
	34	void ack_bad_irq(unsigned int irq)
	35	{
e05d723f TG	36	printk(KERN_ERR "unexpected IRQ trap at vector %02x\n", irq);
	37
	38	#ifdef CONFIG_X86_LOCAL_APIC
	39	/*
	40	* Currently unexpected vectors happen only on SMP and APIC.
	41	* We _must_ ack these because every local APIC has only N
	42	* irq slots per priority level, and a 'hanging, unacked' IRQ
	43	* holds up an irq slot - in excessive cases (when multiple
	44	* unexpected vectors occur) that might lock up the APIC
	45	* completely.
	46	* But only ack when the APIC is enabled -AK
	47	*/
	48	if (cpu_has_apic)
	49	ack_APIC_irq();
1da177e4	50	#endif
e05d723f	51	}
1da177e4 LT	52
	53	#ifdef CONFIG_4KSTACKS
	54	/*
	55	* per-CPU IRQ handling contexts (thread information and stack)
	56	*/
	57	union irq_ctx {
	58	struct thread_info tinfo;
	59	u32 stack[THREAD_SIZE/sizeof(u32)];
	60	};
	61
22722051 AM	62	static union irq_ctx *hardirq_ctx[NR_CPUS] __read_mostly;
22722051 AM	63	static union irq_ctx *softirq_ctx[NR_CPUS] __read_mostly;
1da177e4 LT	64	#endif
	65
	66	/*
	67	* do_IRQ handles all normal device IRQ's (the special
	68	* SMP cross-CPU interrupts have their own specific
	69	* handlers).
	70	*/
	71	fastcall unsigned int do_IRQ(struct pt_regs *regs)
	72	{
7d12e780	73	struct pt_regs *old_regs;
19eadf98 RR	74	/* high bit used in ret_from_ code */
19eadf98 RR	75	int irq = ~regs->orig_eax;
f5b9ed7a	76	struct irq_desc *desc = irq_desc + irq;
1da177e4 LT	77	#ifdef CONFIG_4KSTACKS
	78	union irq_ctx curctx, irqctx;
	79	u32 *isp;
	80	#endif
	81
a052b68b AM	82	if (unlikely((unsigned)irq >= NR_IRQS)) {
	83	printk(KERN_EMERG "%s: cannot handle IRQ %d\n",
	84	__FUNCTION__, irq);
	85	BUG();
	86	}
	87
7d12e780	88	old_regs = set_irq_regs(regs);
1da177e4 LT	89	irq_enter();
	90	#ifdef CONFIG_DEBUG_STACKOVERFLOW
	91	/* Debugging check for stack overflow: is there less than 1KB free? */
	92	{
	93	long esp;
	94
	95	__asm__ __volatile__("andl %%esp,%0" :
	96	"=r" (esp) : "0" (THREAD_SIZE - 1));
	97	if (unlikely(esp < (sizeof(struct thread_info) + STACK_WARN))) {
	98	printk("do_IRQ: stack overflow: %ld\n",
	99	esp - sizeof(struct thread_info));
	100	dump_stack();
	101	}
	102	}
	103	#endif
	104
	105	#ifdef CONFIG_4KSTACKS
	106
	107	curctx = (union irq_ctx *) current_thread_info();
	108	irqctx = hardirq_ctx[smp_processor_id()];
	109
	110	/*
	111	* this is where we switch to the IRQ stack. However, if we are
	112	* already using the IRQ stack (because we interrupted a hardirq
	113	* handler) we can't do that and just have to keep using the
	114	* current stack (which is the irq stack already after all)
	115	*/
	116	if (curctx != irqctx) {
7d12e780	117	int arg1, arg2, ebx;
1da177e4 LT	118
	119	/* build the stack frame on the IRQ stack */
	120	isp = (u32) ((char)irqctx + sizeof(*irqctx));
	121	irqctx->tinfo.task = curctx->tinfo.task;
	122	irqctx->tinfo.previous_esp = current_stack_pointer;
	123
a5d157e0 BS	124	/*
	125	* Copy the softirq bits in preempt_count so that the
	126	* softirq checks work in the hardirq context.
	127	*/
	128	irqctx->tinfo.preempt_count =
91bf4602 AM	129	(irqctx->tinfo.preempt_count & ~SOFTIRQ_MASK) \|
91bf4602 AM	130	(curctx->tinfo.preempt_count & SOFTIRQ_MASK);
a5d157e0	131
1da177e4	132	asm volatile(
f5b9ed7a IM	133	" xchgl %%ebx,%%esp \n"
f5b9ed7a IM	134	" call *%%edi \n"
1da177e4	135	" movl %%ebx,%%esp \n"
7d12e780 DH	136	: "=a" (arg1), "=d" (arg2), "=b" (ebx)
7d12e780 DH	137	: "0" (irq), "1" (desc), "2" (isp),
f5b9ed7a IM	138	"D" (desc->handle_irq)
f5b9ed7a IM	139	: "memory", "cc"
1da177e4 LT	140	);
	141	} else
	142	#endif
7d12e780	143	desc->handle_irq(irq, desc);
1da177e4 LT	144
1da177e4 LT	145	irq_exit();
7d12e780	146	set_irq_regs(old_regs);
1da177e4 LT	147	return 1;
	148	}
	149
	150	#ifdef CONFIG_4KSTACKS
	151
1da177e4	152	static char softirq_stack[NR_CPUS * THREAD_SIZE]
09fce8a1	153	__attribute__((__section__(".bss.page_aligned")));
1da177e4 LT	154
1da177e4 LT	155	static char hardirq_stack[NR_CPUS * THREAD_SIZE]
09fce8a1	156	__attribute__((__section__(".bss.page_aligned")));
1da177e4 LT	157
	158	/*
	159	* allocate per-cpu stacks for hardirq and for softirq processing
	160	*/
	161	void irq_ctx_init(int cpu)
	162	{
	163	union irq_ctx *irqctx;
	164
	165	if (hardirq_ctx[cpu])
	166	return;
	167
	168	irqctx = (union irq_ctx) &hardirq_stack[cpuTHREAD_SIZE];
	169	irqctx->tinfo.task = NULL;
	170	irqctx->tinfo.exec_domain = NULL;
	171	irqctx->tinfo.cpu = cpu;
	172	irqctx->tinfo.preempt_count = HARDIRQ_OFFSET;
	173	irqctx->tinfo.addr_limit = MAKE_MM_SEG(0);
	174
	175	hardirq_ctx[cpu] = irqctx;
	176
	177	irqctx = (union irq_ctx) &softirq_stack[cpuTHREAD_SIZE];
	178	irqctx->tinfo.task = NULL;
	179	irqctx->tinfo.exec_domain = NULL;
	180	irqctx->tinfo.cpu = cpu;
55f327fa	181	irqctx->tinfo.preempt_count = 0;
1da177e4 LT	182	irqctx->tinfo.addr_limit = MAKE_MM_SEG(0);
	183
	184	softirq_ctx[cpu] = irqctx;
	185
	186	printk("CPU %u irqstacks, hard=%p soft=%p\n",
	187	cpu,hardirq_ctx[cpu],softirq_ctx[cpu]);
	188	}
	189
e1367daf LS	190	void irq_ctx_exit(int cpu)
	191	{
	192	hardirq_ctx[cpu] = NULL;
	193	}
	194
1da177e4 LT	195	extern asmlinkage void __do_softirq(void);
	196
	197	asmlinkage void do_softirq(void)
	198	{
	199	unsigned long flags;
	200	struct thread_info *curctx;
	201	union irq_ctx *irqctx;
	202	u32 *isp;
	203
	204	if (in_interrupt())
	205	return;
	206
	207	local_irq_save(flags);
	208
	209	if (local_softirq_pending()) {
	210	curctx = current_thread_info();
	211	irqctx = softirq_ctx[smp_processor_id()];
	212	irqctx->tinfo.task = curctx->task;
	213	irqctx->tinfo.previous_esp = current_stack_pointer;
	214
	215	/* build the stack frame on the softirq stack */
	216	isp = (u32) ((char)irqctx + sizeof(*irqctx));
	217
	218	asm volatile(
	219	" xchgl %%ebx,%%esp \n"
	220	" call __do_softirq \n"
	221	" movl %%ebx,%%esp \n"
	222	: "=b"(isp)
	223	: "0"(isp)
	224	: "memory", "cc", "edx", "ecx", "eax"
	225	);
55f327fa IM	226	/*
	227	* Shouldnt happen, we returned above if in_interrupt():
	228	*/
	229	WARN_ON_ONCE(softirq_count());
1da177e4 LT	230	}
	231
	232	local_irq_restore(flags);
	233	}
	234
	235	EXPORT_SYMBOL(do_softirq);
	236	#endif
	237
	238	/*
	239	* Interrupt statistics:
	240	*/
	241
	242	atomic_t irq_err_count;
	243
	244	/*
	245	* /proc/interrupts printing:
	246	*/
	247
	248	int show_interrupts(struct seq_file p, void v)
	249	{
	250	int i = (loff_t ) v, j;
	251	struct irqaction * action;
	252	unsigned long flags;
	253
	254	if (i == 0) {
	255	seq_printf(p, " ");
9f40a72a	256	for_each_online_cpu(j)
bdbdaa79	257	seq_printf(p, "CPU%-8d",j);
1da177e4 LT	258	seq_putc(p, '\n');
	259	}
	260
	261	if (i < NR_IRQS) {
	262	spin_lock_irqsave(&irq_desc[i].lock, flags);
	263	action = irq_desc[i].action;
	264	if (!action)
	265	goto skip;
	266	seq_printf(p, "%3d: ",i);
	267	#ifndef CONFIG_SMP
	268	seq_printf(p, "%10u ", kstat_irqs(i));
	269	#else
9f40a72a	270	for_each_online_cpu(j)
f3705136	271	seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
1da177e4	272	#endif
f5b9ed7a	273	seq_printf(p, " %8s", irq_desc[i].chip->name);
a460e745	274	seq_printf(p, "-%-8s", irq_desc[i].name);
1da177e4 LT	275	seq_printf(p, " %s", action->name);
	276
	277	for (action=action->next; action; action = action->next)
	278	seq_printf(p, ", %s", action->name);
	279
	280	seq_putc(p, '\n');
	281	skip:
	282	spin_unlock_irqrestore(&irq_desc[i].lock, flags);
	283	} else if (i == NR_IRQS) {
	284	seq_printf(p, "NMI: ");
9f40a72a	285	for_each_online_cpu(j)
f3705136	286	seq_printf(p, "%10u ", nmi_count(j));
1da177e4 LT	287	seq_putc(p, '\n');
	288	#ifdef CONFIG_X86_LOCAL_APIC
	289	seq_printf(p, "LOC: ");
9f40a72a	290	for_each_online_cpu(j)
f3705136 ZM	291	seq_printf(p, "%10u ",
f3705136 ZM	292	per_cpu(irq_stat,j).apic_timer_irqs);
1da177e4 LT	293	seq_putc(p, '\n');
	294	#endif
	295	seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
	296	#if defined(CONFIG_X86_IO_APIC)
	297	seq_printf(p, "MIS: %10u\n", atomic_read(&irq_mis_count));
	298	#endif
	299	}
	300	return 0;
	301	}
f3705136 ZM	302
	303	#ifdef CONFIG_HOTPLUG_CPU
	304	#include <mach_apic.h>
	305
	306	void fixup_irqs(cpumask_t map)
	307	{
	308	unsigned int irq;
	309	static int warned;
	310
	311	for (irq = 0; irq < NR_IRQS; irq++) {
	312	cpumask_t mask;
	313	if (irq == 2)
	314	continue;
	315
a53da52f	316	cpus_and(mask, irq_desc[irq].affinity, map);
f3705136 ZM	317	if (any_online_cpu(mask) == NR_CPUS) {
	318	printk("Breaking affinity for irq %i\n", irq);
	319	mask = map;
	320	}
d1bef4ed IM	321	if (irq_desc[irq].chip->set_affinity)
d1bef4ed IM	322	irq_desc[irq].chip->set_affinity(irq, mask);
f3705136 ZM	323	else if (irq_desc[irq].action && !(warned++))
	324	printk("Cannot set affinity for irq %i\n", irq);
	325	}
	326
	327	#if 0
	328	barrier();
	329	/* Ingo Molnar says: "after the IO-APIC masks have been redirected
	330	[note the nop - the interrupt-enable boundary on x86 is two
	331	instructions from sti] - to flush out pending hardirqs and
	332	IPIs. After this point nothing is supposed to reach this CPU." */
	333	__asm__ __volatile__("sti; nop; cli");
	334	barrier();
	335	#else
	336	/* That doesn't seem sufficient. Give it 1ms. */
	337	local_irq_enable();
	338	mdelay(1);
	339	local_irq_disable();
	340	#endif
	341	}
	342	#endif
	343