Commit | Line | Data |
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5d0cf410 | 1 | #include <linux/clocksource.h> |
e9e2cdb4 | 2 | #include <linux/clockchips.h> |
5d0cf410 | 3 | #include <linux/errno.h> |
4 | #include <linux/hpet.h> | |
5 | #include <linux/init.h> | |
399afa4f ML |
6 | #include <linux/sysdev.h> |
7 | #include <linux/pm.h> | |
5d0cf410 | 8 | |
9 | #include <asm/hpet.h> | |
10 | #include <asm/io.h> | |
11 | ||
e9e2cdb4 TG |
12 | extern struct clock_event_device *global_clock_event; |
13 | ||
7f9f303a | 14 | #define HPET_MASK CLOCKSOURCE_MASK(32) |
5d0cf410 | 15 | #define HPET_SHIFT 22 |
16 | ||
17 | /* FSEC = 10^-15 NSEC = 10^-9 */ | |
18 | #define FSEC_PER_NSEC 1000000 | |
19 | ||
e9e2cdb4 TG |
20 | /* |
21 | * HPET address is set in acpi/boot.c, when an ACPI entry exists | |
22 | */ | |
23 | unsigned long hpet_address; | |
24 | static void __iomem * hpet_virt_address; | |
25 | ||
26 | static inline unsigned long hpet_readl(unsigned long a) | |
27 | { | |
28 | return readl(hpet_virt_address + a); | |
29 | } | |
30 | ||
31 | static inline void hpet_writel(unsigned long d, unsigned long a) | |
32 | { | |
33 | writel(d, hpet_virt_address + a); | |
34 | } | |
35 | ||
36 | /* | |
37 | * HPET command line enable / disable | |
38 | */ | |
39 | static int boot_hpet_disable; | |
40 | ||
41 | static int __init hpet_setup(char* str) | |
42 | { | |
43 | if (str) { | |
44 | if (!strncmp("disable", str, 7)) | |
45 | boot_hpet_disable = 1; | |
46 | } | |
47 | return 1; | |
48 | } | |
49 | __setup("hpet=", hpet_setup); | |
50 | ||
51 | static inline int is_hpet_capable(void) | |
52 | { | |
53 | return (!boot_hpet_disable && hpet_address); | |
54 | } | |
55 | ||
56 | /* | |
57 | * HPET timer interrupt enable / disable | |
58 | */ | |
59 | static int hpet_legacy_int_enabled; | |
60 | ||
61 | /** | |
62 | * is_hpet_enabled - check whether the hpet timer interrupt is enabled | |
63 | */ | |
64 | int is_hpet_enabled(void) | |
65 | { | |
66 | return is_hpet_capable() && hpet_legacy_int_enabled; | |
67 | } | |
68 | ||
69 | /* | |
70 | * When the hpet driver (/dev/hpet) is enabled, we need to reserve | |
71 | * timer 0 and timer 1 in case of RTC emulation. | |
72 | */ | |
73 | #ifdef CONFIG_HPET | |
74 | static void hpet_reserve_platform_timers(unsigned long id) | |
75 | { | |
76 | struct hpet __iomem *hpet = hpet_virt_address; | |
77 | struct hpet_timer __iomem *timer = &hpet->hpet_timers[2]; | |
78 | unsigned int nrtimers, i; | |
79 | struct hpet_data hd; | |
80 | ||
81 | nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; | |
82 | ||
83 | memset(&hd, 0, sizeof (hd)); | |
84 | hd.hd_phys_address = hpet_address; | |
85 | hd.hd_address = hpet_virt_address; | |
86 | hd.hd_nirqs = nrtimers; | |
87 | hd.hd_flags = HPET_DATA_PLATFORM; | |
88 | hpet_reserve_timer(&hd, 0); | |
89 | ||
90 | #ifdef CONFIG_HPET_EMULATE_RTC | |
91 | hpet_reserve_timer(&hd, 1); | |
92 | #endif | |
93 | ||
94 | hd.hd_irq[0] = HPET_LEGACY_8254; | |
95 | hd.hd_irq[1] = HPET_LEGACY_RTC; | |
96 | ||
97 | for (i = 2; i < nrtimers; timer++, i++) | |
98 | hd.hd_irq[i] = (timer->hpet_config & Tn_INT_ROUTE_CNF_MASK) >> | |
99 | Tn_INT_ROUTE_CNF_SHIFT; | |
100 | ||
101 | hpet_alloc(&hd); | |
102 | ||
103 | } | |
104 | #else | |
105 | static void hpet_reserve_platform_timers(unsigned long id) { } | |
106 | #endif | |
107 | ||
108 | /* | |
109 | * Common hpet info | |
110 | */ | |
111 | static unsigned long hpet_period; | |
112 | ||
113 | static void hpet_set_mode(enum clock_event_mode mode, | |
114 | struct clock_event_device *evt); | |
115 | static int hpet_next_event(unsigned long delta, | |
116 | struct clock_event_device *evt); | |
117 | ||
118 | /* | |
119 | * The hpet clock event device | |
120 | */ | |
121 | static struct clock_event_device hpet_clockevent = { | |
122 | .name = "hpet", | |
123 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
124 | .set_mode = hpet_set_mode, | |
125 | .set_next_event = hpet_next_event, | |
126 | .shift = 32, | |
127 | .irq = 0, | |
128 | }; | |
129 | ||
130 | static void hpet_start_counter(void) | |
131 | { | |
132 | unsigned long cfg = hpet_readl(HPET_CFG); | |
133 | ||
134 | cfg &= ~HPET_CFG_ENABLE; | |
135 | hpet_writel(cfg, HPET_CFG); | |
136 | hpet_writel(0, HPET_COUNTER); | |
137 | hpet_writel(0, HPET_COUNTER + 4); | |
138 | cfg |= HPET_CFG_ENABLE; | |
139 | hpet_writel(cfg, HPET_CFG); | |
140 | } | |
141 | ||
142 | static void hpet_enable_int(void) | |
143 | { | |
144 | unsigned long cfg = hpet_readl(HPET_CFG); | |
145 | ||
146 | cfg |= HPET_CFG_LEGACY; | |
147 | hpet_writel(cfg, HPET_CFG); | |
148 | hpet_legacy_int_enabled = 1; | |
149 | } | |
150 | ||
151 | static void hpet_set_mode(enum clock_event_mode mode, | |
152 | struct clock_event_device *evt) | |
153 | { | |
154 | unsigned long cfg, cmp, now; | |
155 | uint64_t delta; | |
156 | ||
157 | switch(mode) { | |
158 | case CLOCK_EVT_MODE_PERIODIC: | |
159 | delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * hpet_clockevent.mult; | |
160 | delta >>= hpet_clockevent.shift; | |
161 | now = hpet_readl(HPET_COUNTER); | |
162 | cmp = now + (unsigned long) delta; | |
163 | cfg = hpet_readl(HPET_T0_CFG); | |
164 | cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | | |
165 | HPET_TN_SETVAL | HPET_TN_32BIT; | |
166 | hpet_writel(cfg, HPET_T0_CFG); | |
167 | /* | |
168 | * The first write after writing TN_SETVAL to the | |
169 | * config register sets the counter value, the second | |
170 | * write sets the period. | |
171 | */ | |
172 | hpet_writel(cmp, HPET_T0_CMP); | |
173 | udelay(1); | |
174 | hpet_writel((unsigned long) delta, HPET_T0_CMP); | |
175 | break; | |
176 | ||
177 | case CLOCK_EVT_MODE_ONESHOT: | |
178 | cfg = hpet_readl(HPET_T0_CFG); | |
179 | cfg &= ~HPET_TN_PERIODIC; | |
180 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
181 | hpet_writel(cfg, HPET_T0_CFG); | |
182 | break; | |
183 | ||
184 | case CLOCK_EVT_MODE_UNUSED: | |
185 | case CLOCK_EVT_MODE_SHUTDOWN: | |
186 | cfg = hpet_readl(HPET_T0_CFG); | |
187 | cfg &= ~HPET_TN_ENABLE; | |
188 | hpet_writel(cfg, HPET_T0_CFG); | |
189 | break; | |
18de5bc4 TG |
190 | |
191 | case CLOCK_EVT_MODE_RESUME: | |
192 | hpet_enable_int(); | |
193 | break; | |
e9e2cdb4 TG |
194 | } |
195 | } | |
196 | ||
197 | static int hpet_next_event(unsigned long delta, | |
198 | struct clock_event_device *evt) | |
199 | { | |
200 | unsigned long cnt; | |
201 | ||
202 | cnt = hpet_readl(HPET_COUNTER); | |
203 | cnt += delta; | |
204 | hpet_writel(cnt, HPET_T0_CMP); | |
205 | ||
c7f6d15f | 206 | return ((long)(hpet_readl(HPET_COUNTER) - cnt ) > 0) ? -ETIME : 0; |
e9e2cdb4 TG |
207 | } |
208 | ||
6bb74df4 | 209 | /* |
210 | * Clock source related code | |
211 | */ | |
212 | static cycle_t read_hpet(void) | |
213 | { | |
214 | return (cycle_t)hpet_readl(HPET_COUNTER); | |
215 | } | |
216 | ||
217 | static struct clocksource clocksource_hpet = { | |
218 | .name = "hpet", | |
219 | .rating = 250, | |
220 | .read = read_hpet, | |
221 | .mask = HPET_MASK, | |
222 | .shift = HPET_SHIFT, | |
223 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
18de5bc4 | 224 | .resume = hpet_start_counter, |
6bb74df4 | 225 | }; |
226 | ||
e9e2cdb4 TG |
227 | /* |
228 | * Try to setup the HPET timer | |
229 | */ | |
230 | int __init hpet_enable(void) | |
231 | { | |
232 | unsigned long id; | |
233 | uint64_t hpet_freq; | |
6bb74df4 | 234 | u64 tmp; |
e9e2cdb4 TG |
235 | |
236 | if (!is_hpet_capable()) | |
237 | return 0; | |
238 | ||
239 | hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE); | |
240 | ||
241 | /* | |
242 | * Read the period and check for a sane value: | |
243 | */ | |
244 | hpet_period = hpet_readl(HPET_PERIOD); | |
245 | if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD) | |
246 | goto out_nohpet; | |
247 | ||
248 | /* | |
249 | * The period is a femto seconds value. We need to calculate the | |
250 | * scaled math multiplication factor for nanosecond to hpet tick | |
251 | * conversion. | |
252 | */ | |
253 | hpet_freq = 1000000000000000ULL; | |
254 | do_div(hpet_freq, hpet_period); | |
255 | hpet_clockevent.mult = div_sc((unsigned long) hpet_freq, | |
256 | NSEC_PER_SEC, 32); | |
257 | /* Calculate the min / max delta */ | |
258 | hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, | |
259 | &hpet_clockevent); | |
260 | hpet_clockevent.min_delta_ns = clockevent_delta2ns(0x30, | |
261 | &hpet_clockevent); | |
262 | ||
263 | /* | |
264 | * Read the HPET ID register to retrieve the IRQ routing | |
265 | * information and the number of channels | |
266 | */ | |
267 | id = hpet_readl(HPET_ID); | |
268 | ||
269 | #ifdef CONFIG_HPET_EMULATE_RTC | |
270 | /* | |
271 | * The legacy routing mode needs at least two channels, tick timer | |
272 | * and the rtc emulation channel. | |
273 | */ | |
274 | if (!(id & HPET_ID_NUMBER)) | |
275 | goto out_nohpet; | |
276 | #endif | |
277 | ||
278 | /* Start the counter */ | |
279 | hpet_start_counter(); | |
280 | ||
6bb74df4 | 281 | /* Initialize and register HPET clocksource |
282 | * | |
283 | * hpet period is in femto seconds per cycle | |
284 | * so we need to convert this to ns/cyc units | |
285 | * aproximated by mult/2^shift | |
286 | * | |
287 | * fsec/cyc * 1nsec/1000000fsec = nsec/cyc = mult/2^shift | |
288 | * fsec/cyc * 1ns/1000000fsec * 2^shift = mult | |
289 | * fsec/cyc * 2^shift * 1nsec/1000000fsec = mult | |
290 | * (fsec/cyc << shift)/1000000 = mult | |
291 | * (hpet_period << shift)/FSEC_PER_NSEC = mult | |
292 | */ | |
293 | tmp = (u64)hpet_period << HPET_SHIFT; | |
294 | do_div(tmp, FSEC_PER_NSEC); | |
295 | clocksource_hpet.mult = (u32)tmp; | |
296 | ||
297 | clocksource_register(&clocksource_hpet); | |
298 | ||
e9e2cdb4 TG |
299 | if (id & HPET_ID_LEGSUP) { |
300 | hpet_enable_int(); | |
301 | hpet_reserve_platform_timers(id); | |
302 | /* | |
303 | * Start hpet with the boot cpu mask and make it | |
304 | * global after the IO_APIC has been initialized. | |
305 | */ | |
306 | hpet_clockevent.cpumask =cpumask_of_cpu(0); | |
307 | clockevents_register_device(&hpet_clockevent); | |
308 | global_clock_event = &hpet_clockevent; | |
309 | return 1; | |
310 | } | |
311 | return 0; | |
5d0cf410 | 312 | |
e9e2cdb4 TG |
313 | out_nohpet: |
314 | iounmap(hpet_virt_address); | |
315 | hpet_virt_address = NULL; | |
399afa4f | 316 | boot_hpet_disable = 1; |
e9e2cdb4 TG |
317 | return 0; |
318 | } | |
319 | ||
e9e2cdb4 TG |
320 | |
321 | #ifdef CONFIG_HPET_EMULATE_RTC | |
322 | ||
323 | /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET | |
324 | * is enabled, we support RTC interrupt functionality in software. | |
325 | * RTC has 3 kinds of interrupts: | |
326 | * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock | |
327 | * is updated | |
328 | * 2) Alarm Interrupt - generate an interrupt at a specific time of day | |
329 | * 3) Periodic Interrupt - generate periodic interrupt, with frequencies | |
330 | * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2) | |
331 | * (1) and (2) above are implemented using polling at a frequency of | |
332 | * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt | |
333 | * overhead. (DEFAULT_RTC_INT_FREQ) | |
334 | * For (3), we use interrupts at 64Hz or user specified periodic | |
335 | * frequency, whichever is higher. | |
336 | */ | |
337 | #include <linux/mc146818rtc.h> | |
338 | #include <linux/rtc.h> | |
339 | ||
340 | #define DEFAULT_RTC_INT_FREQ 64 | |
341 | #define DEFAULT_RTC_SHIFT 6 | |
342 | #define RTC_NUM_INTS 1 | |
343 | ||
344 | static unsigned long hpet_rtc_flags; | |
345 | static unsigned long hpet_prev_update_sec; | |
346 | static struct rtc_time hpet_alarm_time; | |
347 | static unsigned long hpet_pie_count; | |
348 | static unsigned long hpet_t1_cmp; | |
349 | static unsigned long hpet_default_delta; | |
350 | static unsigned long hpet_pie_delta; | |
351 | static unsigned long hpet_pie_limit; | |
352 | ||
353 | /* | |
354 | * Timer 1 for RTC emulation. We use one shot mode, as periodic mode | |
355 | * is not supported by all HPET implementations for timer 1. | |
356 | * | |
357 | * hpet_rtc_timer_init() is called when the rtc is initialized. | |
358 | */ | |
359 | int hpet_rtc_timer_init(void) | |
360 | { | |
361 | unsigned long cfg, cnt, delta, flags; | |
362 | ||
363 | if (!is_hpet_enabled()) | |
364 | return 0; | |
365 | ||
366 | if (!hpet_default_delta) { | |
367 | uint64_t clc; | |
368 | ||
369 | clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; | |
370 | clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT; | |
371 | hpet_default_delta = (unsigned long) clc; | |
372 | } | |
373 | ||
374 | if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) | |
375 | delta = hpet_default_delta; | |
376 | else | |
377 | delta = hpet_pie_delta; | |
378 | ||
379 | local_irq_save(flags); | |
380 | ||
381 | cnt = delta + hpet_readl(HPET_COUNTER); | |
382 | hpet_writel(cnt, HPET_T1_CMP); | |
383 | hpet_t1_cmp = cnt; | |
384 | ||
385 | cfg = hpet_readl(HPET_T1_CFG); | |
386 | cfg &= ~HPET_TN_PERIODIC; | |
387 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
388 | hpet_writel(cfg, HPET_T1_CFG); | |
389 | ||
390 | local_irq_restore(flags); | |
391 | ||
392 | return 1; | |
393 | } | |
394 | ||
395 | /* | |
396 | * The functions below are called from rtc driver. | |
397 | * Return 0 if HPET is not being used. | |
398 | * Otherwise do the necessary changes and return 1. | |
399 | */ | |
400 | int hpet_mask_rtc_irq_bit(unsigned long bit_mask) | |
401 | { | |
402 | if (!is_hpet_enabled()) | |
403 | return 0; | |
404 | ||
405 | hpet_rtc_flags &= ~bit_mask; | |
406 | return 1; | |
407 | } | |
408 | ||
409 | int hpet_set_rtc_irq_bit(unsigned long bit_mask) | |
410 | { | |
411 | unsigned long oldbits = hpet_rtc_flags; | |
412 | ||
413 | if (!is_hpet_enabled()) | |
414 | return 0; | |
415 | ||
416 | hpet_rtc_flags |= bit_mask; | |
417 | ||
418 | if (!oldbits) | |
419 | hpet_rtc_timer_init(); | |
420 | ||
421 | return 1; | |
422 | } | |
423 | ||
424 | int hpet_set_alarm_time(unsigned char hrs, unsigned char min, | |
425 | unsigned char sec) | |
426 | { | |
427 | if (!is_hpet_enabled()) | |
428 | return 0; | |
429 | ||
430 | hpet_alarm_time.tm_hour = hrs; | |
431 | hpet_alarm_time.tm_min = min; | |
432 | hpet_alarm_time.tm_sec = sec; | |
433 | ||
434 | return 1; | |
435 | } | |
436 | ||
437 | int hpet_set_periodic_freq(unsigned long freq) | |
438 | { | |
439 | uint64_t clc; | |
440 | ||
441 | if (!is_hpet_enabled()) | |
442 | return 0; | |
443 | ||
444 | if (freq <= DEFAULT_RTC_INT_FREQ) | |
445 | hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq; | |
446 | else { | |
447 | clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; | |
448 | do_div(clc, freq); | |
449 | clc >>= hpet_clockevent.shift; | |
450 | hpet_pie_delta = (unsigned long) clc; | |
451 | } | |
452 | return 1; | |
453 | } | |
454 | ||
455 | int hpet_rtc_dropped_irq(void) | |
456 | { | |
457 | return is_hpet_enabled(); | |
458 | } | |
459 | ||
460 | static void hpet_rtc_timer_reinit(void) | |
461 | { | |
462 | unsigned long cfg, delta; | |
463 | int lost_ints = -1; | |
464 | ||
465 | if (unlikely(!hpet_rtc_flags)) { | |
466 | cfg = hpet_readl(HPET_T1_CFG); | |
467 | cfg &= ~HPET_TN_ENABLE; | |
468 | hpet_writel(cfg, HPET_T1_CFG); | |
469 | return; | |
470 | } | |
471 | ||
472 | if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) | |
473 | delta = hpet_default_delta; | |
474 | else | |
475 | delta = hpet_pie_delta; | |
476 | ||
477 | /* | |
478 | * Increment the comparator value until we are ahead of the | |
479 | * current count. | |
480 | */ | |
481 | do { | |
482 | hpet_t1_cmp += delta; | |
483 | hpet_writel(hpet_t1_cmp, HPET_T1_CMP); | |
484 | lost_ints++; | |
485 | } while ((long)(hpet_readl(HPET_COUNTER) - hpet_t1_cmp) > 0); | |
486 | ||
487 | if (lost_ints) { | |
488 | if (hpet_rtc_flags & RTC_PIE) | |
489 | hpet_pie_count += lost_ints; | |
490 | if (printk_ratelimit()) | |
491 | printk(KERN_WARNING "rtc: lost %d interrupts\n", | |
492 | lost_ints); | |
493 | } | |
494 | } | |
495 | ||
496 | irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id) | |
497 | { | |
498 | struct rtc_time curr_time; | |
499 | unsigned long rtc_int_flag = 0; | |
500 | ||
501 | hpet_rtc_timer_reinit(); | |
502 | ||
503 | if (hpet_rtc_flags & (RTC_UIE | RTC_AIE)) | |
504 | rtc_get_rtc_time(&curr_time); | |
505 | ||
506 | if (hpet_rtc_flags & RTC_UIE && | |
507 | curr_time.tm_sec != hpet_prev_update_sec) { | |
508 | rtc_int_flag = RTC_UF; | |
509 | hpet_prev_update_sec = curr_time.tm_sec; | |
510 | } | |
511 | ||
512 | if (hpet_rtc_flags & RTC_PIE && | |
513 | ++hpet_pie_count >= hpet_pie_limit) { | |
514 | rtc_int_flag |= RTC_PF; | |
515 | hpet_pie_count = 0; | |
516 | } | |
517 | ||
518 | if (hpet_rtc_flags & RTC_PIE && | |
519 | (curr_time.tm_sec == hpet_alarm_time.tm_sec) && | |
520 | (curr_time.tm_min == hpet_alarm_time.tm_min) && | |
521 | (curr_time.tm_hour == hpet_alarm_time.tm_hour)) | |
522 | rtc_int_flag |= RTC_AF; | |
523 | ||
524 | if (rtc_int_flag) { | |
525 | rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8)); | |
526 | rtc_interrupt(rtc_int_flag, dev_id); | |
527 | } | |
528 | return IRQ_HANDLED; | |
529 | } | |
530 | #endif |