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[CPUFREQ] Optimize gx-suspmod revision ID fetching
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / i386 / kernel / cpu / cpufreq / speedstep-centrino.c
CommitLineData
1da177e4
LT		 1/*
2 * cpufreq driver for Enhanced SpeedStep, as found in Intel's Pentium
3 * M (part of the Centrino chipset).
4 *
491b07c9
JF		 5 * Since the original Pentium M, most new Intel CPUs support Enhanced
6 * SpeedStep.
7 *
1da177e4
LT		 8 * Despite the "SpeedStep" in the name, this is almost entirely unlike
9 * traditional SpeedStep.
10 *
11 * Modelled on speedstep.c
12 *
13 * Copyright (C) 2003 Jeremy Fitzhardinge <jeremy@goop.org>
1da177e4
LT		 14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/cpufreq.h>
4e57b681 20#include <linux/sched.h> /* current */
1da177e4
LT		 21#include <linux/delay.h>
22#include <linux/compiler.h>
23
24#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
25#include <linux/acpi.h>
8adcc0c6 26#include <linux/dmi.h>
1da177e4
LT		 27#include <acpi/processor.h>
28#endif
29
30#include <asm/msr.h>
31#include <asm/processor.h>
32#include <asm/cpufeature.h>
33
1da177e4 34#define PFX "speedstep-centrino: "
491b07c9 35#define MAINTAINER "cpufreq@lists.linux.org.uk"
1da177e4
LT		 36
37#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-centrino", msg)
38
39
40struct cpu_id
41{
42 __u8 x86; /* CPU family */
43 __u8 x86_model; /* model */
44 __u8 x86_mask; /* stepping */
45};
46
47enum {
48 CPU_BANIAS,
49 CPU_DOTHAN_A1,
50 CPU_DOTHAN_A2,
51 CPU_DOTHAN_B0,
8282864a
DJ		 52 CPU_MP4HT_D0,
53 CPU_MP4HT_E0,
1da177e4
LT		 54};
55
56static const struct cpu_id cpu_ids[] = {
57 [CPU_BANIAS] = { 6, 9, 5 },
58 [CPU_DOTHAN_A1] = { 6, 13, 1 },
59 [CPU_DOTHAN_A2] = { 6, 13, 2 },
60 [CPU_DOTHAN_B0] = { 6, 13, 6 },
8282864a
DJ		 61 [CPU_MP4HT_D0] = {15, 3, 4 },
62 [CPU_MP4HT_E0] = {15, 4, 1 },
1da177e4 63};
38e548ee 64#define N_IDS ARRAY_SIZE(cpu_ids)
1da177e4
LT		 65
66struct cpu_model
67{
68 const struct cpu_id *cpu_id;
69 const char *model_name;
70 unsigned max_freq; /* max clock in kHz */
71
72 struct cpufreq_frequency_table *op_points; /* clock/voltage pairs */
73};
74static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, const struct cpu_id *x);
75
76/* Operating points for current CPU */
77static struct cpu_model *centrino_model[NR_CPUS];
78static const struct cpu_id *centrino_cpu[NR_CPUS];
79
80static struct cpufreq_driver centrino_driver;
81
82#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE
83
84/* Computes the correct form for IA32_PERF_CTL MSR for a particular
85 frequency/voltage operating point; frequency in MHz, volts in mV.
86 This is stored as "index" in the structure. */
87#define OP(mhz, mv) \
88 { \
89 .frequency = (mhz) * 1000, \
90 .index = (((mhz)/100) << 8) | ((mv - 700) / 16) \
91 }
92
93/*
94 * These voltage tables were derived from the Intel Pentium M
95 * datasheet, document 25261202.pdf, Table 5. I have verified they
96 * are consistent with my IBM ThinkPad X31, which has a 1.3GHz Pentium
97 * M.
98 */
99
100/* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */
101static struct cpufreq_frequency_table banias_900[] =
102{
103 OP(600, 844),
104 OP(800, 988),
105 OP(900, 1004),
106 { .frequency = CPUFREQ_TABLE_END }
107};
108
109/* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */
110static struct cpufreq_frequency_table banias_1000[] =
111{
112 OP(600, 844),
113 OP(800, 972),
114 OP(900, 988),
115 OP(1000, 1004),
116 { .frequency = CPUFREQ_TABLE_END }
117};
118
119/* Low Voltage Intel Pentium M processor 1.10GHz (Banias) */
120static struct cpufreq_frequency_table banias_1100[] =
121{
122 OP( 600, 956),
123 OP( 800, 1020),
124 OP( 900, 1100),
125 OP(1000, 1164),
126 OP(1100, 1180),
127 { .frequency = CPUFREQ_TABLE_END }
128};
129
130
131/* Low Voltage Intel Pentium M processor 1.20GHz (Banias) */
132static struct cpufreq_frequency_table banias_1200[] =
133{
134 OP( 600, 956),
135 OP( 800, 1004),
136 OP( 900, 1020),
137 OP(1000, 1100),
138 OP(1100, 1164),
139 OP(1200, 1180),
140 { .frequency = CPUFREQ_TABLE_END }
141};
142
143/* Intel Pentium M processor 1.30GHz (Banias) */
144static struct cpufreq_frequency_table banias_1300[] =
145{
146 OP( 600, 956),
147 OP( 800, 1260),
148 OP(1000, 1292),
149 OP(1200, 1356),
150 OP(1300, 1388),
151 { .frequency = CPUFREQ_TABLE_END }
152};
153
154/* Intel Pentium M processor 1.40GHz (Banias) */
155static struct cpufreq_frequency_table banias_1400[] =
156{
157 OP( 600, 956),
158 OP( 800, 1180),
159 OP(1000, 1308),
160 OP(1200, 1436),
161 OP(1400, 1484),
162 { .frequency = CPUFREQ_TABLE_END }
163};
164
165/* Intel Pentium M processor 1.50GHz (Banias) */
166static struct cpufreq_frequency_table banias_1500[] =
167{
168 OP( 600, 956),
169 OP( 800, 1116),
170 OP(1000, 1228),
171 OP(1200, 1356),
172 OP(1400, 1452),
173 OP(1500, 1484),
174 { .frequency = CPUFREQ_TABLE_END }
175};
176
177/* Intel Pentium M processor 1.60GHz (Banias) */
178static struct cpufreq_frequency_table banias_1600[] =
179{
180 OP( 600, 956),
181 OP( 800, 1036),
182 OP(1000, 1164),
183 OP(1200, 1276),
184 OP(1400, 1420),
185 OP(1600, 1484),
186 { .frequency = CPUFREQ_TABLE_END }
187};
188
189/* Intel Pentium M processor 1.70GHz (Banias) */
190static struct cpufreq_frequency_table banias_1700[] =
191{
192 OP( 600, 956),
193 OP( 800, 1004),
194 OP(1000, 1116),
195 OP(1200, 1228),
196 OP(1400, 1308),
197 OP(1700, 1484),
198 { .frequency = CPUFREQ_TABLE_END }
199};
200#undef OP
201
202#define _BANIAS(cpuid, max, name) \
203{ .cpu_id = cpuid, \
204 .model_name = "Intel(R) Pentium(R) M processor " name "MHz", \
205 .max_freq = (max)*1000, \
206 .op_points = banias_##max, \
207}
208#define BANIAS(max) _BANIAS(&cpu_ids[CPU_BANIAS], max, #max)
209
210/* CPU models, their operating frequency range, and freq/voltage
211 operating points */
212static struct cpu_model models[] =
213{
214 _BANIAS(&cpu_ids[CPU_BANIAS], 900, " 900"),
215 BANIAS(1000),
216 BANIAS(1100),
217 BANIAS(1200),
218 BANIAS(1300),
219 BANIAS(1400),
220 BANIAS(1500),
221 BANIAS(1600),
222 BANIAS(1700),
223
224 /* NULL model_name is a wildcard */
225 { &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL },
226 { &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL },
227 { &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL },
8282864a
DJ		 228 { &cpu_ids[CPU_MP4HT_D0], NULL, 0, NULL },
229 { &cpu_ids[CPU_MP4HT_E0], NULL, 0, NULL },
1da177e4
LT		 230
231 { NULL, }
232};
233#undef _BANIAS
234#undef BANIAS
235
236static int centrino_cpu_init_table(struct cpufreq_policy *policy)
237{
238 struct cpuinfo_x86 *cpu = &cpu_data[policy->cpu];
239 struct cpu_model *model;
240
241 for(model = models; model->cpu_id != NULL; model++)
242 if (centrino_verify_cpu_id(cpu, model->cpu_id) &&
243 (model->model_name == NULL ||
244 strcmp(cpu->x86_model_id, model->model_name) == 0))
245 break;
246
247 if (model->cpu_id == NULL) {
248 /* No match at all */
8c362a5d 249 dprintk("no support for CPU model \"%s\": "
1da177e4
LT		 250 "send /proc/cpuinfo to " MAINTAINER "\n",
251 cpu->x86_model_id);
252 return -ENOENT;
253 }
254
255 if (model->op_points == NULL) {
256 /* Matched a non-match */
8c362a5d 257 dprintk("no table support for CPU model \"%s\"\n",
1da177e4
LT		 258 cpu->x86_model_id);
259#ifndef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
8c362a5d 260 dprintk("try compiling with CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI enabled\n");
1da177e4
LT		 261#endif
262 return -ENOENT;
263 }
264
265 centrino_model[policy->cpu] = model;
266
267 dprintk("found \"%s\": max frequency: %dkHz\n",
268 model->model_name, model->max_freq);
269
270 return 0;
271}
272
273#else
274static inline int centrino_cpu_init_table(struct cpufreq_policy *policy) { return -ENODEV; }
275#endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE */
276
277static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, const struct cpu_id *x)
278{
279 if ((c->x86 == x->x86) &&
280 (c->x86_model == x->x86_model) &&
281 (c->x86_mask == x->x86_mask))
282 return 1;
283 return 0;
284}
285
286/* To be called only after centrino_model is initialized */
287static unsigned extract_clock(unsigned msr, unsigned int cpu, int failsafe)
288{
289 int i;
290
291 /*
292 * Extract clock in kHz from PERF_CTL value
293 * for centrino, as some DSDTs are buggy.
294 * Ideally, this can be done using the acpi_data structure.
295 */
296 if ((centrino_cpu[cpu] == &cpu_ids[CPU_BANIAS]) ||
297 (centrino_cpu[cpu] == &cpu_ids[CPU_DOTHAN_A1]) ||
298 (centrino_cpu[cpu] == &cpu_ids[CPU_DOTHAN_B0])) {
299 msr = (msr >> 8) & 0xff;
300 return msr * 100000;
301 }
302
303 if ((!centrino_model[cpu]) || (!centrino_model[cpu]->op_points))
304 return 0;
305
306 msr &= 0xffff;
307 for (i=0;centrino_model[cpu]->op_points[i].frequency != CPUFREQ_TABLE_END; i++) {
308 if (msr == centrino_model[cpu]->op_points[i].index)
309 return centrino_model[cpu]->op_points[i].frequency;
310 }
311 if (failsafe)
312 return centrino_model[cpu]->op_points[i-1].frequency;
313 else
314 return 0;
315}
316
317/* Return the current CPU frequency in kHz */
318static unsigned int get_cur_freq(unsigned int cpu)
319{
320 unsigned l, h;
321 unsigned clock_freq;
322 cpumask_t saved_mask;
323
324 saved_mask = current->cpus_allowed;
325 set_cpus_allowed(current, cpumask_of_cpu(cpu));
326 if (smp_processor_id() != cpu)
327 return 0;
328
329 rdmsr(MSR_IA32_PERF_STATUS, l, h);
330 clock_freq = extract_clock(l, cpu, 0);
331
332 if (unlikely(clock_freq == 0)) {
333 /*
334 * On some CPUs, we can see transient MSR values (which are
335 * not present in _PSS), while CPU is doing some automatic
336 * P-state transition (like TM2). Get the last freq set
337 * in PERF_CTL.
338 */
339 rdmsr(MSR_IA32_PERF_CTL, l, h);
340 clock_freq = extract_clock(l, cpu, 1);
341 }
342
343 set_cpus_allowed(current, saved_mask);
344 return clock_freq;
345}
346
347
348#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
349
c52851b6
VP		 350static struct acpi_processor_performance *acpi_perf_data[NR_CPUS];
351
352/*
353 * centrino_cpu_early_init_acpi - Do the preregistering with ACPI P-States
354 * library
355 *
356 * Before doing the actual init, we need to do _PSD related setup whenever
357 * supported by the BIOS. These are handled by this early_init routine.
358 */
359static int centrino_cpu_early_init_acpi(void)
360{
361 unsigned int i, j;
362 struct acpi_processor_performance *data;
363
fb1bb34d 364 for_each_possible_cpu(i) {
c52851b6
VP		 365 data = kzalloc(sizeof(struct acpi_processor_performance),
366 GFP_KERNEL);
367 if (!data) {
fb1bb34d 368 for_each_possible_cpu(j) {
c52851b6
VP		 369 kfree(acpi_perf_data[j]);
370 acpi_perf_data[j] = NULL;
371 }
372 return (-ENOMEM);
373 }
374 acpi_perf_data[i] = data;
375 }
376
377 acpi_processor_preregister_performance(acpi_perf_data);
378 return 0;
379}
1da177e4 380
8adcc0c6 381
95625b8f 382#ifdef CONFIG_SMP
8adcc0c6
VP		 383/*
384 * Some BIOSes do SW_ANY coordination internally, either set it up in hw
385 * or do it in BIOS firmware and won't inform about it to OS. If not
386 * detected, this has a side effect of making CPU run at a different speed
387 * than OS intended it to run at. Detect it and handle it cleanly.
388 */
389static int bios_with_sw_any_bug;
0497c8ca 390static int sw_any_bug_found(struct dmi_system_id *d)
8adcc0c6
VP		 391{
392 bios_with_sw_any_bug = 1;
393 return 0;
394}
395
24669f7d 396static struct dmi_system_id sw_any_bug_dmi_table[] = {
8adcc0c6
VP		 397 {
398 .callback = sw_any_bug_found,
399 .ident = "Supermicro Server X6DLP",
400 .matches = {
401 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
402 DMI_MATCH(DMI_BIOS_VERSION, "080010"),
403 DMI_MATCH(DMI_PRODUCT_NAME, "X6DLP"),
404 },
405 },
406 { }
407};
fe0f9602 408#endif
8adcc0c6 409
1da177e4
LT		 410/*
411 * centrino_cpu_init_acpi - register with ACPI P-States library
412 *
413 * Register with the ACPI P-States library (part of drivers/acpi/processor.c)
414 * in order to determine correct frequency and voltage pairings by reading
415 * the _PSS of the ACPI DSDT or SSDT tables.
416 */
417static int centrino_cpu_init_acpi(struct cpufreq_policy *policy)
418{
1da177e4
LT		 419 unsigned long cur_freq;
420 int result = 0, i;
421 unsigned int cpu = policy->cpu;
c52851b6
VP		 422 struct acpi_processor_performance *p;
423
424 p = acpi_perf_data[cpu];
1da177e4 425
1da177e4 426 /* register with ACPI core */
c52851b6 427 if (acpi_processor_register_performance(p, cpu)) {
37224470 428 dprintk(PFX "obtaining ACPI data failed\n");
1da177e4
LT		 429 return -EIO;
430 }
8adcc0c6 431
c52851b6 432 policy->shared_type = p->shared_type;
46f18e3a
VP		 433 /*
434 * Will let policy->cpus know about dependency only when software
435 * coordination is required.
436 */
437 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ALL ||
8adcc0c6 438 policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) {
46f18e3a 439 policy->cpus = p->shared_cpu_map;
8adcc0c6
VP		 440 }
441
442#ifdef CONFIG_SMP
443 dmi_check_system(sw_any_bug_dmi_table);
444 if (bios_with_sw_any_bug && cpus_weight(policy->cpus) == 1) {
445 policy->shared_type = CPUFREQ_SHARED_TYPE_ALL;
446 policy->cpus = cpu_core_map[cpu];
447 }
448#endif
1da177e4
LT		 449
450 /* verify the acpi_data */
c52851b6 451 if (p->state_count <= 1) {
1da177e4
LT		 452 dprintk("No P-States\n");
453 result = -ENODEV;
454 goto err_unreg;
455 }
456
c52851b6
VP		 457 if ((p->control_register.space_id != ACPI_ADR_SPACE_FIXED_HARDWARE) ||
458 (p->status_register.space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) {
1da177e4 459 dprintk("Invalid control/status registers (%x - %x)\n",
c52851b6 460 p->control_register.space_id, p->status_register.space_id);
1da177e4
LT		 461 result = -EIO;
462 goto err_unreg;
463 }
464
c52851b6
VP		 465 for (i=0; i<p->state_count; i++) {
466 if (p->states[i].control != p->states[i].status) {
123411f2 467 dprintk("Different control (%llu) and status values (%llu)\n",
c52851b6 468 p->states[i].control, p->states[i].status);
1da177e4
LT		 469 result = -EINVAL;
470 goto err_unreg;
471 }
472
c52851b6 473 if (!p->states[i].core_frequency) {
1da177e4
LT		 474 dprintk("Zero core frequency for state %u\n", i);
475 result = -EINVAL;
476 goto err_unreg;
477 }
478
c52851b6 479 if (p->states[i].core_frequency > p->states[0].core_frequency) {
123411f2 480 dprintk("P%u has larger frequency (%llu) than P0 (%llu), skipping\n", i,
c52851b6
VP		 481 p->states[i].core_frequency, p->states[0].core_frequency);
482 p->states[i].core_frequency = 0;
1da177e4
LT		 483 continue;
484 }
485 }
486
bfdc708d 487 centrino_model[cpu] = kzalloc(sizeof(struct cpu_model), GFP_KERNEL);
1da177e4
LT		 488 if (!centrino_model[cpu]) {
489 result = -ENOMEM;
490 goto err_unreg;
491 }
1da177e4
LT		 492
493 centrino_model[cpu]->model_name=NULL;
c52851b6 494 centrino_model[cpu]->max_freq = p->states[0].core_frequency * 1000;
1da177e4 495 centrino_model[cpu]->op_points = kmalloc(sizeof(struct cpufreq_frequency_table) *
c52851b6 496 (p->state_count + 1), GFP_KERNEL);
1da177e4
LT		 497 if (!centrino_model[cpu]->op_points) {
498 result = -ENOMEM;
499 goto err_kfree;
500 }
501
c52851b6
VP		 502 for (i=0; i<p->state_count; i++) {
503 centrino_model[cpu]->op_points[i].index = p->states[i].control;
504 centrino_model[cpu]->op_points[i].frequency = p->states[i].core_frequency * 1000;
1da177e4
LT		 505 dprintk("adding state %i with frequency %u and control value %04x\n",
506 i, centrino_model[cpu]->op_points[i].frequency, centrino_model[cpu]->op_points[i].index);
507 }
c52851b6 508 centrino_model[cpu]->op_points[p->state_count].frequency = CPUFREQ_TABLE_END;
1da177e4
LT		 509
510 cur_freq = get_cur_freq(cpu);
511
c52851b6
VP		 512 for (i=0; i<p->state_count; i++) {
513 if (!p->states[i].core_frequency) {
1da177e4
LT		 514 dprintk("skipping state %u\n", i);
515 centrino_model[cpu]->op_points[i].frequency = CPUFREQ_ENTRY_INVALID;
516 continue;
517 }
518
519 if (extract_clock(centrino_model[cpu]->op_points[i].index, cpu, 0) !=
520 (centrino_model[cpu]->op_points[i].frequency)) {
521 dprintk("Invalid encoded frequency (%u vs. %u)\n",
522 extract_clock(centrino_model[cpu]->op_points[i].index, cpu, 0),
523 centrino_model[cpu]->op_points[i].frequency);
524 result = -EINVAL;
525 goto err_kfree_all;
526 }
527
528 if (cur_freq == centrino_model[cpu]->op_points[i].frequency)
c52851b6 529 p->state = i;
1da177e4
LT		 530 }
531
532 /* notify BIOS that we exist */
533 acpi_processor_notify_smm(THIS_MODULE);
83d0515b
VP		 534 printk("speedstep-centrino with X86_SPEEDSTEP_CENTRINO_ACPI"
535 "config is deprecated.\n "
536 "Use X86_ACPI_CPUFREQ (acpi-cpufreq instead.\n" );
1da177e4
LT		 537
538 return 0;
539
540 err_kfree_all:
541 kfree(centrino_model[cpu]->op_points);
542 err_kfree:
543 kfree(centrino_model[cpu]);
544 err_unreg:
c52851b6 545 acpi_processor_unregister_performance(p, cpu);
37224470 546 dprintk(PFX "invalid ACPI data\n");
1da177e4
LT		 547 return (result);
548}
549#else
550static inline int centrino_cpu_init_acpi(struct cpufreq_policy *policy) { return -ENODEV; }
c52851b6 551static inline int centrino_cpu_early_init_acpi(void) { return 0; }
1da177e4
LT		 552#endif
553
554static int centrino_cpu_init(struct cpufreq_policy *policy)
555{
556 struct cpuinfo_x86 *cpu = &cpu_data[policy->cpu];
557 unsigned freq;
558 unsigned l, h;
559 int ret;
560 int i;
561
562 /* Only Intel makes Enhanced Speedstep-capable CPUs */
563 if (cpu->x86_vendor != X86_VENDOR_INTEL || !cpu_has(cpu, X86_FEATURE_EST))
564 return -ENODEV;
565
8ad5496d 566 if (cpu_has(cpu, X86_FEATURE_CONSTANT_TSC))
1da177e4 567 centrino_driver.flags |= CPUFREQ_CONST_LOOPS;
1da177e4
LT		 568
569 if (centrino_cpu_init_acpi(policy)) {
570 if (policy->cpu != 0)
571 return -ENODEV;
572
f914be79
VP		 573 for (i = 0; i < N_IDS; i++)
574 if (centrino_verify_cpu_id(cpu, &cpu_ids[i]))
575 break;
576
577 if (i != N_IDS)
578 centrino_cpu[policy->cpu] = &cpu_ids[i];
579
1da177e4 580 if (!centrino_cpu[policy->cpu]) {
8c362a5d 581 dprintk("found unsupported CPU with "
1da177e4
LT		 582 "Enhanced SpeedStep: send /proc/cpuinfo to "
583 MAINTAINER "\n");
584 return -ENODEV;
585 }
586
587 if (centrino_cpu_init_table(policy)) {
588 return -ENODEV;
589 }
590 }
591
592 /* Check to see if Enhanced SpeedStep is enabled, and try to
593 enable it if not. */
594 rdmsr(MSR_IA32_MISC_ENABLE, l, h);
595
596 if (!(l & (1<<16))) {
597 l |= (1<<16);
598 dprintk("trying to enable Enhanced SpeedStep (%x)\n", l);
599 wrmsr(MSR_IA32_MISC_ENABLE, l, h);
600
601 /* check to see if it stuck */
602 rdmsr(MSR_IA32_MISC_ENABLE, l, h);
603 if (!(l & (1<<16))) {
604 printk(KERN_INFO PFX "couldn't enable Enhanced SpeedStep\n");
605 return -ENODEV;
606 }
607 }
608
609 freq = get_cur_freq(policy->cpu);
610
611 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
612 policy->cpuinfo.transition_latency = 10000; /* 10uS transition latency */
613 policy->cur = freq;
614
615 dprintk("centrino_cpu_init: cur=%dkHz\n", policy->cur);
616
617 ret = cpufreq_frequency_table_cpuinfo(policy, centrino_model[policy->cpu]->op_points);
618 if (ret)
619 return (ret);
620
621 cpufreq_frequency_table_get_attr(centrino_model[policy->cpu]->op_points, policy->cpu);
622
623 return 0;
624}
625
626static int centrino_cpu_exit(struct cpufreq_policy *policy)
627{
628 unsigned int cpu = policy->cpu;
629
630 if (!centrino_model[cpu])
631 return -ENODEV;
632
633 cpufreq_frequency_table_put_attr(cpu);
634
635#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
636 if (!centrino_model[cpu]->model_name) {
c52851b6
VP		 637 static struct acpi_processor_performance *p;
638
639 if (acpi_perf_data[cpu]) {
640 p = acpi_perf_data[cpu];
641 dprintk("unregistering and freeing ACPI data\n");
642 acpi_processor_unregister_performance(p, cpu);
643 kfree(centrino_model[cpu]->op_points);
644 kfree(centrino_model[cpu]);
645 }
1da177e4
LT		 646 }
647#endif
648
649 centrino_model[cpu] = NULL;
650
651 return 0;
652}
653
654/**
655 * centrino_verify - verifies a new CPUFreq policy
656 * @policy: new policy
657 *
658 * Limit must be within this model's frequency range at least one
659 * border included.
660 */
661static int centrino_verify (struct cpufreq_policy *policy)
662{
663 return cpufreq_frequency_table_verify(policy, centrino_model[policy->cpu]->op_points);
664}
665
666/**
667 * centrino_setpolicy - set a new CPUFreq policy
668 * @policy: new policy
669 * @target_freq: the target frequency
670 * @relation: how that frequency relates to achieved frequency (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
671 *
672 * Sets a new CPUFreq policy.
673 */
674static int centrino_target (struct cpufreq_policy *policy,
675 unsigned int target_freq,
676 unsigned int relation)
677{
678 unsigned int newstate = 0;
c52851b6 679 unsigned int msr, oldmsr = 0, h = 0, cpu = policy->cpu;
1da177e4 680 struct cpufreq_freqs freqs;
c52851b6 681 cpumask_t online_policy_cpus;
1da177e4 682 cpumask_t saved_mask;
c52851b6
VP		 683 cpumask_t set_mask;
684 cpumask_t covered_cpus;
685 int retval = 0;
686 unsigned int j, k, first_cpu, tmp;
1da177e4 687
c52851b6 688 if (unlikely(centrino_model[cpu] == NULL))
1da177e4
LT		 689 return -ENODEV;
690
c52851b6
VP		 691 if (unlikely(cpufreq_frequency_table_target(policy,
692 centrino_model[cpu]->op_points,
693 target_freq,
694 relation,
695 &newstate))) {
696 return -EINVAL;
1da177e4
LT		 697 }
698
7e1f19e5 699#ifdef CONFIG_HOTPLUG_CPU
c52851b6
VP		 700 /* cpufreq holds the hotplug lock, so we are safe from here on */
701 cpus_and(online_policy_cpus, cpu_online_map, policy->cpus);
7e1f19e5
AM		 702#else
703 online_policy_cpus = policy->cpus;
704#endif
1da177e4 705
c52851b6
VP		 706 saved_mask = current->cpus_allowed;
707 first_cpu = 1;
708 cpus_clear(covered_cpus);
709 for_each_cpu_mask(j, online_policy_cpus) {
710 /*
711 * Support for SMP systems.
712 * Make sure we are running on CPU that wants to change freq
713 */
714 cpus_clear(set_mask);
715 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
716 cpus_or(set_mask, set_mask, online_policy_cpus);
717 else
718 cpu_set(j, set_mask);
719
720 set_cpus_allowed(current, set_mask);
721 if (unlikely(!cpu_isset(smp_processor_id(), set_mask))) {
722 dprintk("couldn't limit to CPUs in this domain\n");
723 retval = -EAGAIN;
724 if (first_cpu) {
725 /* We haven't started the transition yet. */
726 goto migrate_end;
727 }
728 break;
729 }
1da177e4 730
c52851b6
VP		 731 msr = centrino_model[cpu]->op_points[newstate].index;
732
733 if (first_cpu) {
734 rdmsr(MSR_IA32_PERF_CTL, oldmsr, h);
735 if (msr == (oldmsr & 0xffff)) {
736 dprintk("no change needed - msr was and needs "
737 "to be %x\n", oldmsr);
738 retval = 0;
739 goto migrate_end;
740 }
741
742 freqs.old = extract_clock(oldmsr, cpu, 0);
743 freqs.new = extract_clock(msr, cpu, 0);
744
745 dprintk("target=%dkHz old=%d new=%d msr=%04x\n",
746 target_freq, freqs.old, freqs.new, msr);
747
748 for_each_cpu_mask(k, online_policy_cpus) {
749 freqs.cpu = k;
750 cpufreq_notify_transition(&freqs,
751 CPUFREQ_PRECHANGE);
752 }
753
754 first_cpu = 0;
755 /* all but 16 LSB are reserved, treat them with care */
756 oldmsr &= ~0xffff;
757 msr &= 0xffff;
758 oldmsr |= msr;
759 }
1da177e4 760
c52851b6
VP		 761 wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
762 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
763 break;
1da177e4 764
c52851b6
VP		 765 cpu_set(j, covered_cpus);
766 }
1da177e4 767
c52851b6
VP		 768 for_each_cpu_mask(k, online_policy_cpus) {
769 freqs.cpu = k;
770 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
771 }
1da177e4 772
c52851b6
VP		 773 if (unlikely(retval)) {
774 /*
775 * We have failed halfway through the frequency change.
776 * We have sent callbacks to policy->cpus and
777 * MSRs have already been written on coverd_cpus.
778 * Best effort undo..
779 */
1da177e4 780
c52851b6
VP		 781 if (!cpus_empty(covered_cpus)) {
782 for_each_cpu_mask(j, covered_cpus) {
783 set_cpus_allowed(current, cpumask_of_cpu(j));
784 wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
785 }
786 }
1da177e4 787
c52851b6
VP		 788 tmp = freqs.new;
789 freqs.new = freqs.old;
790 freqs.old = tmp;
791 for_each_cpu_mask(j, online_policy_cpus) {
792 freqs.cpu = j;
793 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
794 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
795 }
796 }
1da177e4 797
1da177e4
LT		 798migrate_end:
799 set_cpus_allowed(current, saved_mask);
c52851b6 800 return 0;
1da177e4
LT		 801}
802
803static struct freq_attr* centrino_attr[] = {
804 &cpufreq_freq_attr_scaling_available_freqs,
805 NULL,
806};
807
808static struct cpufreq_driver centrino_driver = {
809 .name = "centrino", /* should be speedstep-centrino,
810 but there's a 16 char limit */
811 .init = centrino_cpu_init,
812 .exit = centrino_cpu_exit,
813 .verify = centrino_verify,
814 .target = centrino_target,
815 .get = get_cur_freq,
816 .attr = centrino_attr,
817 .owner = THIS_MODULE,
818};
819
820
821/**
822 * centrino_init - initializes the Enhanced SpeedStep CPUFreq driver
823 *
824 * Initializes the Enhanced SpeedStep support. Returns -ENODEV on
825 * unsupported devices, -ENOENT if there's no voltage table for this
826 * particular CPU model, -EINVAL on problems during initiatization,
827 * and zero on success.
828 *
829 * This is quite picky. Not only does the CPU have to advertise the
830 * "est" flag in the cpuid capability flags, we look for a specific
831 * CPU model and stepping, and we need to have the exact model name in
832 * our voltage tables. That is, be paranoid about not releasing
833 * someone's valuable magic smoke.
834 */
835static int __init centrino_init(void)
836{
837 struct cpuinfo_x86 *cpu = cpu_data;
838
839 if (!cpu_has(cpu, X86_FEATURE_EST))
840 return -ENODEV;
841
c52851b6
VP		 842 centrino_cpu_early_init_acpi();
843
1da177e4
LT		 844 return cpufreq_register_driver(&centrino_driver);
845}
846
847static void __exit centrino_exit(void)
848{
c52851b6
VP		 849#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
850 unsigned int j;
851#endif
852
1da177e4 853 cpufreq_unregister_driver(&centrino_driver);
c52851b6
VP		 854
855#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
fb1bb34d 856 for_each_possible_cpu(j) {
c52851b6
VP		 857 kfree(acpi_perf_data[j]);
858 acpi_perf_data[j] = NULL;
859 }
860#endif
1da177e4
LT		 861}
862
863MODULE_AUTHOR ("Jeremy Fitzhardinge <jeremy@goop.org>");
864MODULE_DESCRIPTION ("Enhanced SpeedStep driver for Intel Pentium M processors.");
865MODULE_LICENSE ("GPL");
866
867late_initcall(centrino_init);
868module_exit(centrino_exit);
kernel source for telekom puls (alcatel/mediatek)