[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / frv / mb93090-mb00 / pci-vdk.c

/* pci-vdk.c: MB93090-MB00 (VDK) PCI support
 *
 * Copyright (C) 2003, 2004 Red Hat, Inc. All Rights Reserved.
 * Written by David Howells (dhowells@redhat.com)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/delay.h>

#include <asm/segment.h>
#include <asm/io.h>
#include <asm/mb-regs.h>
#include <asm/mb86943a.h>
#include "pci-frv.h"

unsigned int __nongpreldata pci_probe = 1;

int  __nongpreldata pcibios_last_bus = -1;
struct pci_bus *__nongpreldata pci_root_bus;
struct pci_ops *__nongpreldata pci_root_ops;

/*
 * The accessible PCI window does not cover the entire CPU address space, but
 * there are devices we want to access outside of that window, so we need to
 * insert specific PCI bus resources instead of using the platform-level bus
 * resources directly for the PCI root bus.
 *
 * These are configured and inserted by pcibios_init() and are attached to the
 * root bus by pcibios_fixup_bus().
 */
static struct resource pci_ioport_resource = {
	.name	= "PCI IO",
	.start	= 0,
	.end	= IO_SPACE_LIMIT,
	.flags	= IORESOURCE_IO,
};

static struct resource pci_iomem_resource = {
	.name	= "PCI mem",
	.start	= 0,
	.end	= -1,
	.flags	= IORESOURCE_MEM,
};

/*
 * Functions for accessing PCI configuration space
 */

#define CONFIG_CMD(bus, dev, where) \
	(0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))

#define __set_PciCfgAddr(A) writel((A), (volatile void __iomem *) __region_CS1 + 0x80)

#define __get_PciCfgDataB(A) readb((volatile void __iomem *) __region_CS1 + 0x88 + ((A) & 3))
#define __get_PciCfgDataW(A) readw((volatile void __iomem *) __region_CS1 + 0x88 + ((A) & 2))
#define __get_PciCfgDataL(A) readl((volatile void __iomem *) __region_CS1 + 0x88)

#define __set_PciCfgDataB(A,V) \
	writeb((V), (volatile void __iomem *) __region_CS1 + 0x88 + (3 - ((A) & 3)))

#define __set_PciCfgDataW(A,V) \
	writew((V), (volatile void __iomem *) __region_CS1 + 0x88 + (2 - ((A) & 2)))

#define __set_PciCfgDataL(A,V) \
	writel((V), (volatile void __iomem *) __region_CS1 + 0x88)

#define __get_PciBridgeDataB(A) readb((volatile void __iomem *) __region_CS1 + 0x800 + (A))
#define __get_PciBridgeDataW(A) readw((volatile void __iomem *) __region_CS1 + 0x800 + (A))
#define __get_PciBridgeDataL(A) readl((volatile void __iomem *) __region_CS1 + 0x800 + (A))

#define __set_PciBridgeDataB(A,V) writeb((V), (volatile void __iomem *) __region_CS1 + 0x800 + (A))
#define __set_PciBridgeDataW(A,V) writew((V), (volatile void __iomem *) __region_CS1 + 0x800 + (A))
#define __set_PciBridgeDataL(A,V) writel((V), (volatile void __iomem *) __region_CS1 + 0x800 + (A))

static inline int __query(const struct pci_dev *dev)
{
//	return dev->bus->number==0 && (dev->devfn==PCI_DEVFN(0,0));
//	return dev->bus->number==1;
//	return dev->bus->number==0 &&
//		(dev->devfn==PCI_DEVFN(2,0) || dev->devfn==PCI_DEVFN(3,0));
	return 0;
}

/*****************************************************************************/
/*
 *
 */
static int pci_frv_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size,
			       u32 *val)
{
	u32 _value;

	if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
		_value = __get_PciBridgeDataL(where & ~3);
	}
	else {
		__set_PciCfgAddr(CONFIG_CMD(bus, devfn, where));
		_value = __get_PciCfgDataL(where & ~3);
	}

	switch (size) {
	case 1:
		_value = _value >> ((where & 3) * 8);
		break;

	case 2:
		_value = _value >> ((where & 2) * 8);
		break;

	case 4:
		break;

	default:
		BUG();
	}

	*val = _value;
	return PCIBIOS_SUCCESSFUL;
}

static int pci_frv_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size,
				u32 value)
{
	switch (size) {
	case 1:
		if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
			__set_PciBridgeDataB(where, value);
		}
		else {
			__set_PciCfgAddr(CONFIG_CMD(bus, devfn, where));
			__set_PciCfgDataB(where, value);
		}
		break;

	case 2:
		if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
			__set_PciBridgeDataW(where, value);
		}
		else {
			__set_PciCfgAddr(CONFIG_CMD(bus, devfn, where));
			__set_PciCfgDataW(where, value);
		}
		break;

	case 4:
		if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
			__set_PciBridgeDataL(where, value);
		}
		else {
			__set_PciCfgAddr(CONFIG_CMD(bus, devfn, where));
			__set_PciCfgDataL(where, value);
		}
		break;

	default:
		BUG();
	}

	return PCIBIOS_SUCCESSFUL;
}

static struct pci_ops pci_direct_frv = {
	pci_frv_read_config,
	pci_frv_write_config,
};

/*
 * Before we decide to use direct hardware access mechanisms, we try to do some
 * trivial checks to ensure it at least _seems_ to be working -- we just test
 * whether bus 00 contains a host bridge (this is similar to checking
 * techniques used in XFree86, but ours should be more reliable since we
 * attempt to make use of direct access hints provided by the PCI BIOS).
 *
 * This should be close to trivial, but it isn't, because there are buggy
 * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
 */
static int __init pci_sanity_check(struct pci_ops *o)
{
	struct pci_bus bus;		/* Fake bus and device */
	u32 id;

	bus.number	= 0;

	if (o->read(&bus, 0, PCI_VENDOR_ID, 4, &id) == PCIBIOS_SUCCESSFUL) {
		printk("PCI: VDK Bridge device:vendor: %08x\n", id);
		if (id == 0x200e10cf)
			return 1;
	}

	printk("PCI: VDK Bridge: Sanity check failed\n");
	return 0;
}

static struct pci_ops * __init pci_check_direct(void)
{
	unsigned long flags;

	local_irq_save(flags);

	/* check if access works */
	if (pci_sanity_check(&pci_direct_frv)) {
		local_irq_restore(flags);
		printk("PCI: Using configuration frv\n");
//		request_mem_region(0xBE040000, 256, "FRV bridge");
//		request_mem_region(0xBFFFFFF4, 12, "PCI frv");
		return &pci_direct_frv;
	}

	local_irq_restore(flags);
	return NULL;
}

/*
 * Discover remaining PCI buses in case there are peer host bridges.
 * We use the number of last PCI bus provided by the PCI BIOS.
 */
static void __init pcibios_fixup_peer_bridges(void)
{
	struct pci_bus bus;
	struct pci_dev dev;
	int n;
	u16 l;

	if (pcibios_last_bus <= 0 || pcibios_last_bus >= 0xff)
		return;
	printk("PCI: Peer bridge fixup\n");
	for (n=0; n <= pcibios_last_bus; n++) {
		if (pci_find_bus(0, n))
			continue;
		bus.number = n;
		bus.ops = pci_root_ops;
		dev.bus = &bus;
		for(dev.devfn=0; dev.devfn<256; dev.devfn += 8)
			if (!pci_read_config_word(&dev, PCI_VENDOR_ID, &l) &&
			    l != 0x0000 && l != 0xffff) {
				printk("Found device at %02x:%02x [%04x]\n", n, dev.devfn, l);
				printk("PCI: Discovered peer bus %02x\n", n);
				pci_scan_bus(n, pci_root_ops, NULL);
				break;
			}
	}
}

/*
 * Exceptions for specific devices. Usually work-arounds for fatal design flaws.
 */

static void __init pci_fixup_umc_ide(struct pci_dev *d)
{
	/*
	 * UM8886BF IDE controller sets region type bits incorrectly,
	 * therefore they look like memory despite of them being I/O.
	 */
	int i;

	printk("PCI: Fixing base address flags for device %s\n", pci_name(d));
	for(i=0; i<4; i++)
		d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
}

static void __init pci_fixup_ide_bases(struct pci_dev *d)
{
	int i;

	/*
	 * PCI IDE controllers use non-standard I/O port decoding, respect it.
	 */
	if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
		return;
	printk("PCI: IDE base address fixup for %s\n", pci_name(d));
	for(i=0; i<4; i++) {
		struct resource *r = &d->resource[i];
		if ((r->start & ~0x80) == 0x374) {
			r->start |= 2;
			r->end = r->start;
		}
	}
}

static void __init pci_fixup_ide_trash(struct pci_dev *d)
{
	int i;

	/*
	 * There exist PCI IDE controllers which have utter garbage
	 * in first four base registers. Ignore that.
	 */
	printk("PCI: IDE base address trash cleared for %s\n", pci_name(d));
	for(i=0; i<4; i++)
		d->resource[i].start = d->resource[i].end = d->resource[i].flags = 0;
}

static void __devinit  pci_fixup_latency(struct pci_dev *d)
{
	/*
	 *  SiS 5597 and 5598 chipsets require latency timer set to
	 *  at most 32 to avoid lockups.
	 */
	DBG("PCI: Setting max latency to 32\n");
	pcibios_max_latency = 32;
}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, pci_fixup_ide_trash);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency);
DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);

/*
 *  Called after each bus is probed, but before its children
 *  are examined.
 */

void __init pcibios_fixup_bus(struct pci_bus *bus)
{
#if 0
	printk("### PCIBIOS_FIXUP_BUS(%d)\n",bus->number);
#endif

	if (bus->number == 0) {
		bus->resource[0] = &pci_ioport_resource;
		bus->resource[1] = &pci_iomem_resource;
	}

	pci_read_bridge_bases(bus);

	if (bus->number == 0) {
		struct list_head *ln;
		struct pci_dev *dev;
		for (ln=bus->devices.next; ln != &bus->devices; ln=ln->next) {
			dev = pci_dev_b(ln);
			if (dev->devfn == 0) {
				dev->resource[0].start = 0;
				dev->resource[0].end = 0;
			}
		}
	}
}

/*
 * Initialization. Try all known PCI access methods. Note that we support
 * using both PCI BIOS and direct access: in such cases, we use I/O ports
 * to access config space, but we still keep BIOS order of cards to be
 * compatible with 2.0.X. This should go away some day.
 */

int __init pcibios_init(void)
{
	struct pci_ops *dir = NULL;

	if (!mb93090_mb00_detected)
		return -ENXIO;

	__reg_MB86943_sl_ctl |= MB86943_SL_CTL_DRCT_MASTER_SWAP | MB86943_SL_CTL_DRCT_SLAVE_SWAP;

	__reg_MB86943_ecs_base(1)	= ((__region_CS2 + 0x01000000) >> 9) | 0x08000000;
	__reg_MB86943_ecs_base(2)	= ((__region_CS2 + 0x00000000) >> 9) | 0x08000000;

	*(volatile uint32_t *) (__region_CS1 + 0x848) = 0xe0000000;
	*(volatile uint32_t *) (__region_CS1 + 0x8b8) = 0x00000000;

	__reg_MB86943_sl_pci_io_base	= (__region_CS2 + 0x04000000) >> 9;
	__reg_MB86943_sl_pci_mem_base	= (__region_CS2 + 0x08000000) >> 9;
	__reg_MB86943_pci_sl_io_base	= __region_CS2 + 0x04000000;
	__reg_MB86943_pci_sl_mem_base	= __region_CS2 + 0x08000000;
	mb();

	/* enable PCI arbitration */
	__reg_MB86943_pci_arbiter	= MB86943_PCIARB_EN;

	pci_ioport_resource.start	= (__reg_MB86943_sl_pci_io_base << 9) & 0xfffffc00;
	pci_ioport_resource.end		= (__reg_MB86943_sl_pci_io_range << 9) | 0x3ff;
	pci_ioport_resource.end		+= pci_ioport_resource.start;

	printk("PCI IO window:  %08llx-%08llx\n",
	       (unsigned long long) pci_ioport_resource.start,
	       (unsigned long long) pci_ioport_resource.end);

	pci_iomem_resource.start	= (__reg_MB86943_sl_pci_mem_base << 9) & 0xfffffc00;
	pci_iomem_resource.end		= (__reg_MB86943_sl_pci_mem_range << 9) | 0x3ff;
	pci_iomem_resource.end		+= pci_iomem_resource.start;

	/* Reserve somewhere to write to flush posted writes.  This is used by
	 * __flush_PCI_writes() from asm/io.h to force the write FIFO in the
	 * CPU-PCI bridge to flush as this doesn't happen automatically when a
	 * read is performed on the MB93090 development kit motherboard.
	 */
	pci_iomem_resource.start	+= 0x400;

	printk("PCI MEM window: %08llx-%08llx\n",
	       (unsigned long long) pci_iomem_resource.start,
	       (unsigned long long) pci_iomem_resource.end);
	printk("PCI DMA memory: %08lx-%08lx\n",
	       dma_coherent_mem_start, dma_coherent_mem_end);

	if (insert_resource(&iomem_resource, &pci_iomem_resource) < 0)
		panic("Unable to insert PCI IOMEM resource\n");
	if (insert_resource(&ioport_resource, &pci_ioport_resource) < 0)
		panic("Unable to insert PCI IOPORT resource\n");

	if (!pci_probe)
		return -ENXIO;

	dir = pci_check_direct();
	if (dir)
		pci_root_ops = dir;
	else {
		printk("PCI: No PCI bus detected\n");
		return -ENXIO;
	}

	printk("PCI: Probing PCI hardware\n");
	pci_root_bus = pci_scan_bus(0, pci_root_ops, NULL);

	pcibios_irq_init();
	pcibios_fixup_peer_bridges();
	pcibios_fixup_irqs();
	pcibios_resource_survey();

	return 0;
}

arch_initcall(pcibios_init);

char * __init pcibios_setup(char *str)
{
	if (!strcmp(str, "off")) {
		pci_probe = 0;
		return NULL;
	} else if (!strncmp(str, "lastbus=", 8)) {
		pcibios_last_bus = simple_strtol(str+8, NULL, 0);
		return NULL;
	}
	return str;
}

int pcibios_enable_device(struct pci_dev *dev, int mask)
{
	int err;

	if ((err = pci_enable_resources(dev, mask)) < 0)
		return err;
	if (!dev->msi_enabled)
		pcibios_enable_irq(dev);
	return 0;
}
Commit	Line	Data
1da177e4 LT	1	/* pci-vdk.c: MB93090-MB00 (VDK) PCI support
	2	*
	3	* Copyright (C) 2003, 2004 Red Hat, Inc. All Rights Reserved.
	4	* Written by David Howells (dhowells@redhat.com)
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version
	9	* 2 of the License, or (at your option) any later version.
	10	*/
	11
1da177e4 LT	12	#include <linux/types.h>
	13	#include <linux/kernel.h>
	14	#include <linux/sched.h>
	15	#include <linux/pci.h>
	16	#include <linux/init.h>
	17	#include <linux/ioport.h>
	18	#include <linux/delay.h>
1da177e4 LT	19
	20	#include <asm/segment.h>
	21	#include <asm/io.h>
	22	#include <asm/mb-regs.h>
	23	#include <asm/mb86943a.h>
	24	#include "pci-frv.h"
	25
	26	unsigned int __nongpreldata pci_probe = 1;
	27
	28	int __nongpreldata pcibios_last_bus = -1;
	29	struct pci_bus *__nongpreldata pci_root_bus;
	30	struct pci_ops *__nongpreldata pci_root_ops;
	31
77e38a55 DH	32	/*
	33	* The accessible PCI window does not cover the entire CPU address space, but
	34	* there are devices we want to access outside of that window, so we need to
	35	* insert specific PCI bus resources instead of using the platform-level bus
	36	* resources directly for the PCI root bus.
	37	*
	38	* These are configured and inserted by pcibios_init() and are attached to the
	39	* root bus by pcibios_fixup_bus().
	40	*/
	41	static struct resource pci_ioport_resource = {
	42	.name = "PCI IO",
	43	.start = 0,
	44	.end = IO_SPACE_LIMIT,
	45	.flags = IORESOURCE_IO,
	46	};
	47
	48	static struct resource pci_iomem_resource = {
	49	.name = "PCI mem",
	50	.start = 0,
	51	.end = -1,
	52	.flags = IORESOURCE_MEM,
	53	};
	54
1da177e4 LT	55	/*
	56	* Functions for accessing PCI configuration space
	57	*/
	58
	59	#define CONFIG_CMD(bus, dev, where) \
	60	(0x80000000 \| (bus->number << 16) \| (devfn << 8) \| (where & ~3))
	61
	62	#define __set_PciCfgAddr(A) writel((A), (volatile void __iomem *) __region_CS1 + 0x80)
	63
	64	#define __get_PciCfgDataB(A) readb((volatile void __iomem *) __region_CS1 + 0x88 + ((A) & 3))
	65	#define __get_PciCfgDataW(A) readw((volatile void __iomem *) __region_CS1 + 0x88 + ((A) & 2))
	66	#define __get_PciCfgDataL(A) readl((volatile void __iomem *) __region_CS1 + 0x88)
	67
	68	#define __set_PciCfgDataB(A,V) \
	69	writeb((V), (volatile void __iomem *) __region_CS1 + 0x88 + (3 - ((A) & 3)))
	70
	71	#define __set_PciCfgDataW(A,V) \
	72	writew((V), (volatile void __iomem *) __region_CS1 + 0x88 + (2 - ((A) & 2)))
	73
	74	#define __set_PciCfgDataL(A,V) \
	75	writel((V), (volatile void __iomem *) __region_CS1 + 0x88)
	76
	77	#define __get_PciBridgeDataB(A) readb((volatile void __iomem *) __region_CS1 + 0x800 + (A))
	78	#define __get_PciBridgeDataW(A) readw((volatile void __iomem *) __region_CS1 + 0x800 + (A))
	79	#define __get_PciBridgeDataL(A) readl((volatile void __iomem *) __region_CS1 + 0x800 + (A))
	80
	81	#define __set_PciBridgeDataB(A,V) writeb((V), (volatile void __iomem *) __region_CS1 + 0x800 + (A))
	82	#define __set_PciBridgeDataW(A,V) writew((V), (volatile void __iomem *) __region_CS1 + 0x800 + (A))
	83	#define __set_PciBridgeDataL(A,V) writel((V), (volatile void __iomem *) __region_CS1 + 0x800 + (A))
	84
	85	static inline int __query(const struct pci_dev *dev)
	86	{
	87	// return dev->bus->number==0 && (dev->devfn==PCI_DEVFN(0,0));
	88	// return dev->bus->number==1;
	89	// return dev->bus->number==0 &&
	90	// (dev->devfn==PCI_DEVFN(2,0) \|\| dev->devfn==PCI_DEVFN(3,0));
	91	return 0;
	92	}
	93
	94	/*****************************************************************************/
	95	/*
	96	*
	97	*/
	98	static int pci_frv_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size,
	99	u32 *val)
	100	{
	101	u32 _value;
	102
	103	if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
	104	_value = __get_PciBridgeDataL(where & ~3);
	105	}
	106	else {
	107	__set_PciCfgAddr(CONFIG_CMD(bus, devfn, where));
	108	_value = __get_PciCfgDataL(where & ~3);
	109	}
	110
	111	switch (size) {
	112	case 1:
	113	_value = _value >> ((where & 3) * 8);
	114	break;
	115
	116	case 2:
	117	_value = _value >> ((where & 2) * 8);
	118	break;
119
120	case 4:
121	break;
122
123	default:
124	BUG();
125	}
126
127	*val = _value;
128	return PCIBIOS_SUCCESSFUL;
129	}
130
131	static int pci_frv_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size,
132	u32 value)
133	{
134	switch (size) {
135	case 1:
136	if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
137	__set_PciBridgeDataB(where, value);
138	}
139	else {
140	__set_PciCfgAddr(CONFIG_CMD(bus, devfn, where));
141	__set_PciCfgDataB(where, value);
142	}
143	break;
144
145	case 2:
146	if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
147	__set_PciBridgeDataW(where, value);
148	}
149	else {
150	__set_PciCfgAddr(CONFIG_CMD(bus, devfn, where));
151	__set_PciCfgDataW(where, value);
152	}
153	break;
154
155	case 4:
156	if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
157	__set_PciBridgeDataL(where, value);
158	}
159	else {
160	__set_PciCfgAddr(CONFIG_CMD(bus, devfn, where));
161	__set_PciCfgDataL(where, value);
162	}
163	break;
164
165	default:
166	BUG();
167	}
168
169	return PCIBIOS_SUCCESSFUL;
170	}
171
172	static struct pci_ops pci_direct_frv = {
173	pci_frv_read_config,
174	pci_frv_write_config,
175	};
176
177	/*
178	* Before we decide to use direct hardware access mechanisms, we try to do some
179	* trivial checks to ensure it at least _seems_ to be working -- we just test
180	* whether bus 00 contains a host bridge (this is similar to checking
181	* techniques used in XFree86, but ours should be more reliable since we
182	* attempt to make use of direct access hints provided by the PCI BIOS).
183	*
184	* This should be close to trivial, but it isn't, because there are buggy
185	* chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
186	*/
187	static int __init pci_sanity_check(struct pci_ops *o)
188	{
189	struct pci_bus bus; /* Fake bus and device */
190	u32 id;
191
192	bus.number = 0;
193
194	if (o->read(&bus, 0, PCI_VENDOR_ID, 4, &id) == PCIBIOS_SUCCESSFUL) {
195	printk("PCI: VDK Bridge device:vendor: %08x\n", id);
196	if (id == 0x200e10cf)
197	return 1;
198	}
199
200	printk("PCI: VDK Bridge: Sanity check failed\n");
201	return 0;
202	}
203
204	static struct pci_ops * __init pci_check_direct(void)
205	{
206	unsigned long flags;
207
208	local_irq_save(flags);
209
210	/* check if access works */
211	if (pci_sanity_check(&pci_direct_frv)) {
212	local_irq_restore(flags);
213	printk("PCI: Using configuration frv\n");
214	// request_mem_region(0xBE040000, 256, "FRV bridge");
215	// request_mem_region(0xBFFFFFF4, 12, "PCI frv");
216	return &pci_direct_frv;
217	}
218
219	local_irq_restore(flags);
220	return NULL;
221	}
222
1da177e4 LT	223	/*
	224	* Discover remaining PCI buses in case there are peer host bridges.
	225	* We use the number of last PCI bus provided by the PCI BIOS.
	226	*/
	227	static void __init pcibios_fixup_peer_bridges(void)
	228	{
	229	struct pci_bus bus;
	230	struct pci_dev dev;
	231	int n;
	232	u16 l;
	233
	234	if (pcibios_last_bus <= 0 \|\| pcibios_last_bus >= 0xff)
	235	return;
	236	printk("PCI: Peer bridge fixup\n");
	237	for (n=0; n <= pcibios_last_bus; n++) {
	238	if (pci_find_bus(0, n))
	239	continue;
	240	bus.number = n;
	241	bus.ops = pci_root_ops;
	242	dev.bus = &bus;
	243	for(dev.devfn=0; dev.devfn<256; dev.devfn += 8)
	244	if (!pci_read_config_word(&dev, PCI_VENDOR_ID, &l) &&
	245	l != 0x0000 && l != 0xffff) {
	246	printk("Found device at %02x:%02x [%04x]\n", n, dev.devfn, l);
	247	printk("PCI: Discovered peer bus %02x\n", n);
	248	pci_scan_bus(n, pci_root_ops, NULL);
	249	break;
	250	}
	251	}
	252	}
	253
	254	/*
	255	* Exceptions for specific devices. Usually work-arounds for fatal design flaws.
	256	*/
	257
	258	static void __init pci_fixup_umc_ide(struct pci_dev *d)
	259	{
	260	/*
	261	* UM8886BF IDE controller sets region type bits incorrectly,
	262	* therefore they look like memory despite of them being I/O.
	263	*/
	264	int i;
	265
	266	printk("PCI: Fixing base address flags for device %s\n", pci_name(d));
	267	for(i=0; i<4; i++)
	268	d->resource[i].flags \|= PCI_BASE_ADDRESS_SPACE_IO;
	269	}
	270
	271	static void __init pci_fixup_ide_bases(struct pci_dev *d)
	272	{
	273	int i;
	274
	275	/*
	276	* PCI IDE controllers use non-standard I/O port decoding, respect it.
	277	*/
	278	if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
	279	return;
	280	printk("PCI: IDE base address fixup for %s\n", pci_name(d));
	281	for(i=0; i<4; i++) {
	282	struct resource *r = &d->resource[i];
	283	if ((r->start & ~0x80) == 0x374) {
	284	r->start \|= 2;
	285	r->end = r->start;
	286	}
287	}
288	}
289
290	static void __init pci_fixup_ide_trash(struct pci_dev *d)
291	{
292	int i;
293
294	/*
295	* There exist PCI IDE controllers which have utter garbage
296	* in first four base registers. Ignore that.
297	*/
298	printk("PCI: IDE base address trash cleared for %s\n", pci_name(d));
299	for(i=0; i<4; i++)
300	d->resource[i].start = d->resource[i].end = d->resource[i].flags = 0;
301	}
302
303	static void __devinit pci_fixup_latency(struct pci_dev *d)
304	{
305	/*
306	* SiS 5597 and 5598 chipsets require latency timer set to
307	* at most 32 to avoid lockups.
308	*/
309	DBG("PCI: Setting max latency to 32\n");
310	pcibios_max_latency = 32;
311	}
312
313	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide);
314	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, pci_fixup_ide_trash);
315	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency);
316	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency);
317	DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
318
319	/*
320	* Called after each bus is probed, but before its children
321	* are examined.
322	*/
323
324	void __init pcibios_fixup_bus(struct pci_bus *bus)
325	{
326	#if 0
327	printk("### PCIBIOS_FIXUP_BUS(%d)\n",bus->number);
328	#endif
77e38a55 DH	329
	330	if (bus->number == 0) {
	331	bus->resource[0] = &pci_ioport_resource;
	332	bus->resource[1] = &pci_iomem_resource;
	333	}
	334
1da177e4 LT	335	pci_read_bridge_bases(bus);
	336
	337	if (bus->number == 0) {
	338	struct list_head *ln;
	339	struct pci_dev *dev;
	340	for (ln=bus->devices.next; ln != &bus->devices; ln=ln->next) {
	341	dev = pci_dev_b(ln);
	342	if (dev->devfn == 0) {
	343	dev->resource[0].start = 0;
	344	dev->resource[0].end = 0;
	345	}
	346	}
	347	}
	348	}
	349
	350	/*
	351	* Initialization. Try all known PCI access methods. Note that we support
	352	* using both PCI BIOS and direct access: in such cases, we use I/O ports
	353	* to access config space, but we still keep BIOS order of cards to be
	354	* compatible with 2.0.X. This should go away some day.
	355	*/
	356
	357	int __init pcibios_init(void)
	358	{
	359	struct pci_ops *dir = NULL;
	360
	361	if (!mb93090_mb00_detected)
	362	return -ENXIO;
	363
	364	__reg_MB86943_sl_ctl \|= MB86943_SL_CTL_DRCT_MASTER_SWAP \| MB86943_SL_CTL_DRCT_SLAVE_SWAP;
	365
	366	__reg_MB86943_ecs_base(1) = ((__region_CS2 + 0x01000000) >> 9) \| 0x08000000;
	367	__reg_MB86943_ecs_base(2) = ((__region_CS2 + 0x00000000) >> 9) \| 0x08000000;
	368
	369	(volatile uint32_t ) (__region_CS1 + 0x848) = 0xe0000000;
	370	(volatile uint32_t ) (__region_CS1 + 0x8b8) = 0x00000000;
	371
	372	__reg_MB86943_sl_pci_io_base = (__region_CS2 + 0x04000000) >> 9;
	373	__reg_MB86943_sl_pci_mem_base = (__region_CS2 + 0x08000000) >> 9;
	374	__reg_MB86943_pci_sl_io_base = __region_CS2 + 0x04000000;
	375	__reg_MB86943_pci_sl_mem_base = __region_CS2 + 0x08000000;
	376	mb();
	377
04668873 DH	378	/* enable PCI arbitration */
04668873 DH	379	__reg_MB86943_pci_arbiter = MB86943_PCIARB_EN;
1da177e4	380
77e38a55 DH	381	pci_ioport_resource.start = (__reg_MB86943_sl_pci_io_base << 9) & 0xfffffc00;
	382	pci_ioport_resource.end = (__reg_MB86943_sl_pci_io_range << 9) \| 0x3ff;
	383	pci_ioport_resource.end += pci_ioport_resource.start;
1da177e4	384
9dec17eb	385	printk("PCI IO window: %08llx-%08llx\n",
77e38a55 DH	386	(unsigned long long) pci_ioport_resource.start,
77e38a55 DH	387	(unsigned long long) pci_ioport_resource.end);
1da177e4	388
77e38a55 DH	389	pci_iomem_resource.start = (__reg_MB86943_sl_pci_mem_base << 9) & 0xfffffc00;
	390	pci_iomem_resource.end = (__reg_MB86943_sl_pci_mem_range << 9) \| 0x3ff;
	391	pci_iomem_resource.end += pci_iomem_resource.start;
1da177e4	392
77e38a55 DH	393	/* Reserve somewhere to write to flush posted writes. This is used by
	394	* __flush_PCI_writes() from asm/io.h to force the write FIFO in the
	395	* CPU-PCI bridge to flush as this doesn't happen automatically when a
	396	* read is performed on the MB93090 development kit motherboard.
	397	*/
	398	pci_iomem_resource.start += 0x400;
1da177e4	399
9dec17eb	400	printk("PCI MEM window: %08llx-%08llx\n",
77e38a55 DH	401	(unsigned long long) pci_iomem_resource.start,
77e38a55 DH	402	(unsigned long long) pci_iomem_resource.end);
9dec17eb DH	403	printk("PCI DMA memory: %08lx-%08lx\n",
9dec17eb DH	404	dma_coherent_mem_start, dma_coherent_mem_end);
1da177e4	405
77e38a55 DH	406	if (insert_resource(&iomem_resource, &pci_iomem_resource) < 0)
	407	panic("Unable to insert PCI IOMEM resource\n");
	408	if (insert_resource(&ioport_resource, &pci_ioport_resource) < 0)
	409	panic("Unable to insert PCI IOPORT resource\n");
	410
1da177e4 LT	411	if (!pci_probe)
	412	return -ENXIO;
	413
	414	dir = pci_check_direct();
	415	if (dir)
	416	pci_root_ops = dir;
	417	else {
	418	printk("PCI: No PCI bus detected\n");
	419	return -ENXIO;
	420	}
	421
	422	printk("PCI: Probing PCI hardware\n");
	423	pci_root_bus = pci_scan_bus(0, pci_root_ops, NULL);
	424
	425	pcibios_irq_init();
	426	pcibios_fixup_peer_bridges();
	427	pcibios_fixup_irqs();
	428	pcibios_resource_survey();
	429
	430	return 0;
	431	}
	432
	433	arch_initcall(pcibios_init);
	434
	435	char * __init pcibios_setup(char *str)
	436	{
	437	if (!strcmp(str, "off")) {
	438	pci_probe = 0;
	439	return NULL;
	440	} else if (!strncmp(str, "lastbus=", 8)) {
	441	pcibios_last_bus = simple_strtol(str+8, NULL, 0);
	442	return NULL;
	443	}
	444	return str;
	445	}
	446
	447	int pcibios_enable_device(struct pci_dev *dev, int mask)
	448	{
	449	int err;
	450
9bd8f9c6	451	if ((err = pci_enable_resources(dev, mask)) < 0)
1da177e4	452	return err;
bba6f6fc EB	453	if (!dev->msi_enabled)
bba6f6fc EB	454	pcibios_enable_irq(dev);
1da177e4 LT	455	return 0;
1da177e4 LT	456	}