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1394f032 | 1 | /* |
96f1050d | 2 | * Copyright 2005-2009 Analog Devices Inc. |
1394f032 | 3 | * |
96f1050d | 4 | * Licensed under the ADI BSD license or the GPL-2 (or later) |
1394f032 BW |
5 | */ |
6 | ||
7 | #ifndef _DEF_BF561_H | |
8 | #define _DEF_BF561_H | |
9 | /* | |
10 | #if !defined(__ADSPBF561__) | |
11 | #warning defBF561.h should only be included for BF561 chip. | |
12 | #endif | |
13 | */ | |
14 | /* include all Core registers and bit definitions */ | |
639f6571 | 15 | #include <asm/def_LPBlackfin.h> |
1394f032 BW |
16 | |
17 | /*********************************************************************************** */ | |
18 | /* System MMR Register Map */ | |
19 | /*********************************************************************************** */ | |
20 | ||
21 | /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ | |
22 | ||
23 | #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ | |
24 | #define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ | |
25 | #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */ | |
26 | #define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */ | |
27 | #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */ | |
28 | #define CHIPID 0xFFC00014 /* Chip ID Register */ | |
29 | ||
315a8e34 MF |
30 | /* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ |
31 | #define SWRST SICA_SWRST | |
32 | #define SYSCR SICA_SYSCR | |
fa43cd8b | 33 | #define DOUBLE_FAULT (DOUBLE_FAULT_B|DOUBLE_FAULT_A) |
41241c17 MF |
34 | #define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A) |
35 | #define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A) | |
36 | #define RESET_SOFTWARE (SWRST_OCCURRED) | |
315a8e34 | 37 | |
1394f032 BW |
38 | /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ |
39 | #define SICA_SWRST 0xFFC00100 /* Software Reset register */ | |
40 | #define SICA_SYSCR 0xFFC00104 /* System Reset Configuration register */ | |
41 | #define SICA_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */ | |
42 | #define SICA_IMASK 0xFFC0010C /* SIC Interrupt Mask register 0 - hack to fix old tests */ | |
43 | #define SICA_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */ | |
44 | #define SICA_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */ | |
45 | #define SICA_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */ | |
46 | #define SICA_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */ | |
47 | #define SICA_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */ | |
48 | #define SICA_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */ | |
49 | #define SICA_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */ | |
50 | #define SICA_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */ | |
51 | #define SICA_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */ | |
52 | #define SICA_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */ | |
53 | #define SICA_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */ | |
54 | #define SICA_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */ | |
55 | #define SICA_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */ | |
56 | #define SICA_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */ | |
57 | ||
58 | /* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */ | |
59 | #define SICB_SWRST 0xFFC01100 /* reserved */ | |
60 | #define SICB_SYSCR 0xFFC01104 /* reserved */ | |
61 | #define SICB_RVECT 0xFFC01108 /* SIC Reset Vector Address Register */ | |
62 | #define SICB_IMASK0 0xFFC0110C /* SIC Interrupt Mask register 0 */ | |
63 | #define SICB_IMASK1 0xFFC01110 /* SIC Interrupt Mask register 1 */ | |
64 | #define SICB_IAR0 0xFFC01124 /* SIC Interrupt Assignment Register 0 */ | |
65 | #define SICB_IAR1 0xFFC01128 /* SIC Interrupt Assignment Register 1 */ | |
66 | #define SICB_IAR2 0xFFC0112C /* SIC Interrupt Assignment Register 2 */ | |
67 | #define SICB_IAR3 0xFFC01130 /* SIC Interrupt Assignment Register 3 */ | |
68 | #define SICB_IAR4 0xFFC01134 /* SIC Interrupt Assignment Register 4 */ | |
69 | #define SICB_IAR5 0xFFC01138 /* SIC Interrupt Assignment Register 5 */ | |
70 | #define SICB_IAR6 0xFFC0113C /* SIC Interrupt Assignment Register 6 */ | |
71 | #define SICB_IAR7 0xFFC01140 /* SIC Interrupt Assignment Register 7 */ | |
72 | #define SICB_ISR0 0xFFC01114 /* SIC Interrupt Status register 0 */ | |
73 | #define SICB_ISR1 0xFFC01118 /* SIC Interrupt Status register 1 */ | |
74 | #define SICB_IWR0 0xFFC0111C /* SIC Interrupt Wakeup-Enable register 0 */ | |
75 | #define SICB_IWR1 0xFFC01120 /* SIC Interrupt Wakeup-Enable register 1 */ | |
76 | ||
77 | /* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */ | |
78 | #define WDOGA_CTL 0xFFC00200 /* Watchdog Control register */ | |
79 | #define WDOGA_CNT 0xFFC00204 /* Watchdog Count register */ | |
80 | #define WDOGA_STAT 0xFFC00208 /* Watchdog Status register */ | |
81 | ||
82 | /* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */ | |
83 | #define WDOGB_CTL 0xFFC01200 /* Watchdog Control register */ | |
84 | #define WDOGB_CNT 0xFFC01204 /* Watchdog Count register */ | |
85 | #define WDOGB_STAT 0xFFC01208 /* Watchdog Status register */ | |
86 | ||
87 | /* UART Controller (0xFFC00400 - 0xFFC004FF) */ | |
6ed83942 GY |
88 | |
89 | /* | |
90 | * Because include/linux/serial_reg.h have defined UART_*, | |
91 | * So we define blackfin uart regs to BFIN_UART0_*. | |
92 | */ | |
93 | #define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */ | |
94 | #define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */ | |
95 | #define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ | |
96 | #define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */ | |
97 | #define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ | |
98 | #define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */ | |
99 | #define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */ | |
100 | #define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */ | |
101 | #define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */ | |
102 | #define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register */ | |
103 | #define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */ | |
104 | #define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */ | |
1394f032 BW |
105 | |
106 | /* SPI Controller (0xFFC00500 - 0xFFC005FF) */ | |
1d487f46 | 107 | #define SPI0_REGBASE 0xFFC00500 |
1394f032 BW |
108 | #define SPI_CTL 0xFFC00500 /* SPI Control Register */ |
109 | #define SPI_FLG 0xFFC00504 /* SPI Flag register */ | |
110 | #define SPI_STAT 0xFFC00508 /* SPI Status register */ | |
111 | #define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ | |
112 | #define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ | |
113 | #define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */ | |
114 | #define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ | |
115 | ||
116 | /* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */ | |
117 | #define TIMER0_CONFIG 0xFFC00600 /* Timer0 Configuration register */ | |
118 | #define TIMER0_COUNTER 0xFFC00604 /* Timer0 Counter register */ | |
119 | #define TIMER0_PERIOD 0xFFC00608 /* Timer0 Period register */ | |
120 | #define TIMER0_WIDTH 0xFFC0060C /* Timer0 Width register */ | |
121 | ||
122 | #define TIMER1_CONFIG 0xFFC00610 /* Timer1 Configuration register */ | |
123 | #define TIMER1_COUNTER 0xFFC00614 /* Timer1 Counter register */ | |
124 | #define TIMER1_PERIOD 0xFFC00618 /* Timer1 Period register */ | |
125 | #define TIMER1_WIDTH 0xFFC0061C /* Timer1 Width register */ | |
126 | ||
127 | #define TIMER2_CONFIG 0xFFC00620 /* Timer2 Configuration register */ | |
128 | #define TIMER2_COUNTER 0xFFC00624 /* Timer2 Counter register */ | |
129 | #define TIMER2_PERIOD 0xFFC00628 /* Timer2 Period register */ | |
130 | #define TIMER2_WIDTH 0xFFC0062C /* Timer2 Width register */ | |
131 | ||
132 | #define TIMER3_CONFIG 0xFFC00630 /* Timer3 Configuration register */ | |
133 | #define TIMER3_COUNTER 0xFFC00634 /* Timer3 Counter register */ | |
134 | #define TIMER3_PERIOD 0xFFC00638 /* Timer3 Period register */ | |
135 | #define TIMER3_WIDTH 0xFFC0063C /* Timer3 Width register */ | |
136 | ||
137 | #define TIMER4_CONFIG 0xFFC00640 /* Timer4 Configuration register */ | |
138 | #define TIMER4_COUNTER 0xFFC00644 /* Timer4 Counter register */ | |
139 | #define TIMER4_PERIOD 0xFFC00648 /* Timer4 Period register */ | |
140 | #define TIMER4_WIDTH 0xFFC0064C /* Timer4 Width register */ | |
141 | ||
142 | #define TIMER5_CONFIG 0xFFC00650 /* Timer5 Configuration register */ | |
143 | #define TIMER5_COUNTER 0xFFC00654 /* Timer5 Counter register */ | |
144 | #define TIMER5_PERIOD 0xFFC00658 /* Timer5 Period register */ | |
145 | #define TIMER5_WIDTH 0xFFC0065C /* Timer5 Width register */ | |
146 | ||
147 | #define TIMER6_CONFIG 0xFFC00660 /* Timer6 Configuration register */ | |
148 | #define TIMER6_COUNTER 0xFFC00664 /* Timer6 Counter register */ | |
149 | #define TIMER6_PERIOD 0xFFC00668 /* Timer6 Period register */ | |
150 | #define TIMER6_WIDTH 0xFFC0066C /* Timer6 Width register */ | |
151 | ||
152 | #define TIMER7_CONFIG 0xFFC00670 /* Timer7 Configuration register */ | |
153 | #define TIMER7_COUNTER 0xFFC00674 /* Timer7 Counter register */ | |
154 | #define TIMER7_PERIOD 0xFFC00678 /* Timer7 Period register */ | |
155 | #define TIMER7_WIDTH 0xFFC0067C /* Timer7 Width register */ | |
156 | ||
157 | #define TMRS8_ENABLE 0xFFC00680 /* Timer Enable Register */ | |
158 | #define TMRS8_DISABLE 0xFFC00684 /* Timer Disable register */ | |
159 | #define TMRS8_STATUS 0xFFC00688 /* Timer Status register */ | |
160 | ||
161 | /* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */ | |
162 | #define TIMER8_CONFIG 0xFFC01600 /* Timer8 Configuration register */ | |
163 | #define TIMER8_COUNTER 0xFFC01604 /* Timer8 Counter register */ | |
164 | #define TIMER8_PERIOD 0xFFC01608 /* Timer8 Period register */ | |
165 | #define TIMER8_WIDTH 0xFFC0160C /* Timer8 Width register */ | |
166 | ||
167 | #define TIMER9_CONFIG 0xFFC01610 /* Timer9 Configuration register */ | |
168 | #define TIMER9_COUNTER 0xFFC01614 /* Timer9 Counter register */ | |
169 | #define TIMER9_PERIOD 0xFFC01618 /* Timer9 Period register */ | |
170 | #define TIMER9_WIDTH 0xFFC0161C /* Timer9 Width register */ | |
171 | ||
172 | #define TIMER10_CONFIG 0xFFC01620 /* Timer10 Configuration register */ | |
173 | #define TIMER10_COUNTER 0xFFC01624 /* Timer10 Counter register */ | |
174 | #define TIMER10_PERIOD 0xFFC01628 /* Timer10 Period register */ | |
175 | #define TIMER10_WIDTH 0xFFC0162C /* Timer10 Width register */ | |
176 | ||
177 | #define TIMER11_CONFIG 0xFFC01630 /* Timer11 Configuration register */ | |
178 | #define TIMER11_COUNTER 0xFFC01634 /* Timer11 Counter register */ | |
179 | #define TIMER11_PERIOD 0xFFC01638 /* Timer11 Period register */ | |
180 | #define TIMER11_WIDTH 0xFFC0163C /* Timer11 Width register */ | |
181 | ||
182 | #define TMRS4_ENABLE 0xFFC01640 /* Timer Enable Register */ | |
183 | #define TMRS4_DISABLE 0xFFC01644 /* Timer Disable register */ | |
184 | #define TMRS4_STATUS 0xFFC01648 /* Timer Status register */ | |
185 | ||
186 | /* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */ | |
187 | #define FIO0_FLAG_D 0xFFC00700 /* Flag Data register */ | |
188 | #define FIO0_FLAG_C 0xFFC00704 /* Flag Clear register */ | |
189 | #define FIO0_FLAG_S 0xFFC00708 /* Flag Set register */ | |
190 | #define FIO0_FLAG_T 0xFFC0070C /* Flag Toggle register */ | |
191 | #define FIO0_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Data register */ | |
192 | #define FIO0_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Clear register */ | |
193 | #define FIO0_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Set register */ | |
194 | #define FIO0_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Toggle register */ | |
195 | #define FIO0_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Data register */ | |
196 | #define FIO0_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Clear register */ | |
197 | #define FIO0_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Set register */ | |
198 | #define FIO0_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Toggle register */ | |
199 | #define FIO0_DIR 0xFFC00730 /* Flag Direction register */ | |
200 | #define FIO0_POLAR 0xFFC00734 /* Flag Polarity register */ | |
201 | #define FIO0_EDGE 0xFFC00738 /* Flag Interrupt Sensitivity register */ | |
202 | #define FIO0_BOTH 0xFFC0073C /* Flag Set on Both Edges register */ | |
203 | #define FIO0_INEN 0xFFC00740 /* Flag Input Enable register */ | |
204 | ||
205 | /* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */ | |
206 | #define FIO1_FLAG_D 0xFFC01500 /* Flag Data register (mask used to directly */ | |
207 | #define FIO1_FLAG_C 0xFFC01504 /* Flag Clear register */ | |
208 | #define FIO1_FLAG_S 0xFFC01508 /* Flag Set register */ | |
209 | #define FIO1_FLAG_T 0xFFC0150C /* Flag Toggle register (mask used to */ | |
210 | #define FIO1_MASKA_D 0xFFC01510 /* Flag Mask Interrupt A Data register */ | |
211 | #define FIO1_MASKA_C 0xFFC01514 /* Flag Mask Interrupt A Clear register */ | |
212 | #define FIO1_MASKA_S 0xFFC01518 /* Flag Mask Interrupt A Set register */ | |
213 | #define FIO1_MASKA_T 0xFFC0151C /* Flag Mask Interrupt A Toggle register */ | |
214 | #define FIO1_MASKB_D 0xFFC01520 /* Flag Mask Interrupt B Data register */ | |
215 | #define FIO1_MASKB_C 0xFFC01524 /* Flag Mask Interrupt B Clear register */ | |
216 | #define FIO1_MASKB_S 0xFFC01528 /* Flag Mask Interrupt B Set register */ | |
217 | #define FIO1_MASKB_T 0xFFC0152C /* Flag Mask Interrupt B Toggle register */ | |
218 | #define FIO1_DIR 0xFFC01530 /* Flag Direction register */ | |
219 | #define FIO1_POLAR 0xFFC01534 /* Flag Polarity register */ | |
220 | #define FIO1_EDGE 0xFFC01538 /* Flag Interrupt Sensitivity register */ | |
221 | #define FIO1_BOTH 0xFFC0153C /* Flag Set on Both Edges register */ | |
222 | #define FIO1_INEN 0xFFC01540 /* Flag Input Enable register */ | |
223 | ||
224 | /* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */ | |
225 | #define FIO2_FLAG_D 0xFFC01700 /* Flag Data register (mask used to directly */ | |
226 | #define FIO2_FLAG_C 0xFFC01704 /* Flag Clear register */ | |
227 | #define FIO2_FLAG_S 0xFFC01708 /* Flag Set register */ | |
228 | #define FIO2_FLAG_T 0xFFC0170C /* Flag Toggle register (mask used to */ | |
229 | #define FIO2_MASKA_D 0xFFC01710 /* Flag Mask Interrupt A Data register */ | |
230 | #define FIO2_MASKA_C 0xFFC01714 /* Flag Mask Interrupt A Clear register */ | |
231 | #define FIO2_MASKA_S 0xFFC01718 /* Flag Mask Interrupt A Set register */ | |
232 | #define FIO2_MASKA_T 0xFFC0171C /* Flag Mask Interrupt A Toggle register */ | |
233 | #define FIO2_MASKB_D 0xFFC01720 /* Flag Mask Interrupt B Data register */ | |
234 | #define FIO2_MASKB_C 0xFFC01724 /* Flag Mask Interrupt B Clear register */ | |
235 | #define FIO2_MASKB_S 0xFFC01728 /* Flag Mask Interrupt B Set register */ | |
236 | #define FIO2_MASKB_T 0xFFC0172C /* Flag Mask Interrupt B Toggle register */ | |
237 | #define FIO2_DIR 0xFFC01730 /* Flag Direction register */ | |
238 | #define FIO2_POLAR 0xFFC01734 /* Flag Polarity register */ | |
239 | #define FIO2_EDGE 0xFFC01738 /* Flag Interrupt Sensitivity register */ | |
240 | #define FIO2_BOTH 0xFFC0173C /* Flag Set on Both Edges register */ | |
241 | #define FIO2_INEN 0xFFC01740 /* Flag Input Enable register */ | |
242 | ||
243 | /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ | |
244 | #define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ | |
245 | #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ | |
246 | #define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ | |
247 | #define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ | |
248 | #define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ | |
249 | #define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ | |
250 | #define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ | |
251 | #define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ | |
252 | #define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ | |
253 | #define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ | |
254 | #define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ | |
255 | #define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ | |
256 | #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ | |
257 | #define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ | |
258 | #define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ | |
259 | #define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ | |
260 | #define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ | |
261 | #define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ | |
262 | #define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ | |
263 | #define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ | |
264 | #define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ | |
265 | #define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ | |
266 | ||
267 | /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ | |
268 | #define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ | |
269 | #define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ | |
270 | #define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ | |
271 | #define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ | |
272 | #define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ | |
273 | #define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ | |
274 | #define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ | |
275 | #define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ | |
276 | #define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ | |
277 | #define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ | |
278 | #define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ | |
279 | #define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ | |
280 | #define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ | |
281 | #define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ | |
282 | #define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ | |
283 | #define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ | |
284 | #define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ | |
285 | #define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ | |
286 | #define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ | |
287 | #define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ | |
288 | #define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ | |
289 | #define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ | |
290 | ||
291 | /* Asynchronous Memory Controller - External Bus Interface Unit */ | |
292 | #define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ | |
293 | #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ | |
294 | #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ | |
295 | ||
296 | /* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ | |
297 | #define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ | |
298 | #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ | |
299 | #define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ | |
300 | #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ | |
301 | ||
302 | /* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */ | |
303 | #define PPI0_CONTROL 0xFFC01000 /* PPI0 Control register */ | |
304 | #define PPI0_STATUS 0xFFC01004 /* PPI0 Status register */ | |
305 | #define PPI0_COUNT 0xFFC01008 /* PPI0 Transfer Count register */ | |
306 | #define PPI0_DELAY 0xFFC0100C /* PPI0 Delay Count register */ | |
307 | #define PPI0_FRAME 0xFFC01010 /* PPI0 Frame Length register */ | |
308 | ||
309 | /*Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */ | |
310 | #define PPI1_CONTROL 0xFFC01300 /* PPI1 Control register */ | |
311 | #define PPI1_STATUS 0xFFC01304 /* PPI1 Status register */ | |
312 | #define PPI1_COUNT 0xFFC01308 /* PPI1 Transfer Count register */ | |
313 | #define PPI1_DELAY 0xFFC0130C /* PPI1 Delay Count register */ | |
314 | #define PPI1_FRAME 0xFFC01310 /* PPI1 Frame Length register */ | |
315 | ||
316 | /*DMA traffic control registers */ | |
317 | #define DMA1_TC_PER 0xFFC01B0C /* Traffic control periods */ | |
318 | #define DMA1_TC_CNT 0xFFC01B10 /* Traffic control current counts */ | |
319 | #define DMA2_TC_PER 0xFFC00B0C /* Traffic control periods */ | |
320 | #define DMA2_TC_CNT 0xFFC00B10 /* Traffic control current counts */ | |
321 | ||
322 | /* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */ | |
323 | #define DMA1_0_CONFIG 0xFFC01C08 /* DMA1 Channel 0 Configuration register */ | |
324 | #define DMA1_0_NEXT_DESC_PTR 0xFFC01C00 /* DMA1 Channel 0 Next Descripter Ptr Reg */ | |
325 | #define DMA1_0_START_ADDR 0xFFC01C04 /* DMA1 Channel 0 Start Address */ | |
326 | #define DMA1_0_X_COUNT 0xFFC01C10 /* DMA1 Channel 0 Inner Loop Count */ | |
327 | #define DMA1_0_Y_COUNT 0xFFC01C18 /* DMA1 Channel 0 Outer Loop Count */ | |
328 | #define DMA1_0_X_MODIFY 0xFFC01C14 /* DMA1 Channel 0 Inner Loop Addr Increment */ | |
329 | #define DMA1_0_Y_MODIFY 0xFFC01C1C /* DMA1 Channel 0 Outer Loop Addr Increment */ | |
330 | #define DMA1_0_CURR_DESC_PTR 0xFFC01C20 /* DMA1 Channel 0 Current Descriptor Pointer */ | |
331 | #define DMA1_0_CURR_ADDR 0xFFC01C24 /* DMA1 Channel 0 Current Address Pointer */ | |
332 | #define DMA1_0_CURR_X_COUNT 0xFFC01C30 /* DMA1 Channel 0 Current Inner Loop Count */ | |
333 | #define DMA1_0_CURR_Y_COUNT 0xFFC01C38 /* DMA1 Channel 0 Current Outer Loop Count */ | |
334 | #define DMA1_0_IRQ_STATUS 0xFFC01C28 /* DMA1 Channel 0 Interrupt/Status Register */ | |
335 | #define DMA1_0_PERIPHERAL_MAP 0xFFC01C2C /* DMA1 Channel 0 Peripheral Map Register */ | |
336 | ||
337 | #define DMA1_1_CONFIG 0xFFC01C48 /* DMA1 Channel 1 Configuration register */ | |
338 | #define DMA1_1_NEXT_DESC_PTR 0xFFC01C40 /* DMA1 Channel 1 Next Descripter Ptr Reg */ | |
339 | #define DMA1_1_START_ADDR 0xFFC01C44 /* DMA1 Channel 1 Start Address */ | |
340 | #define DMA1_1_X_COUNT 0xFFC01C50 /* DMA1 Channel 1 Inner Loop Count */ | |
341 | #define DMA1_1_Y_COUNT 0xFFC01C58 /* DMA1 Channel 1 Outer Loop Count */ | |
342 | #define DMA1_1_X_MODIFY 0xFFC01C54 /* DMA1 Channel 1 Inner Loop Addr Increment */ | |
343 | #define DMA1_1_Y_MODIFY 0xFFC01C5C /* DMA1 Channel 1 Outer Loop Addr Increment */ | |
344 | #define DMA1_1_CURR_DESC_PTR 0xFFC01C60 /* DMA1 Channel 1 Current Descriptor Pointer */ | |
345 | #define DMA1_1_CURR_ADDR 0xFFC01C64 /* DMA1 Channel 1 Current Address Pointer */ | |
346 | #define DMA1_1_CURR_X_COUNT 0xFFC01C70 /* DMA1 Channel 1 Current Inner Loop Count */ | |
347 | #define DMA1_1_CURR_Y_COUNT 0xFFC01C78 /* DMA1 Channel 1 Current Outer Loop Count */ | |
348 | #define DMA1_1_IRQ_STATUS 0xFFC01C68 /* DMA1 Channel 1 Interrupt/Status Register */ | |
349 | #define DMA1_1_PERIPHERAL_MAP 0xFFC01C6C /* DMA1 Channel 1 Peripheral Map Register */ | |
350 | ||
351 | #define DMA1_2_CONFIG 0xFFC01C88 /* DMA1 Channel 2 Configuration register */ | |
352 | #define DMA1_2_NEXT_DESC_PTR 0xFFC01C80 /* DMA1 Channel 2 Next Descripter Ptr Reg */ | |
353 | #define DMA1_2_START_ADDR 0xFFC01C84 /* DMA1 Channel 2 Start Address */ | |
354 | #define DMA1_2_X_COUNT 0xFFC01C90 /* DMA1 Channel 2 Inner Loop Count */ | |
355 | #define DMA1_2_Y_COUNT 0xFFC01C98 /* DMA1 Channel 2 Outer Loop Count */ | |
356 | #define DMA1_2_X_MODIFY 0xFFC01C94 /* DMA1 Channel 2 Inner Loop Addr Increment */ | |
357 | #define DMA1_2_Y_MODIFY 0xFFC01C9C /* DMA1 Channel 2 Outer Loop Addr Increment */ | |
358 | #define DMA1_2_CURR_DESC_PTR 0xFFC01CA0 /* DMA1 Channel 2 Current Descriptor Pointer */ | |
359 | #define DMA1_2_CURR_ADDR 0xFFC01CA4 /* DMA1 Channel 2 Current Address Pointer */ | |
360 | #define DMA1_2_CURR_X_COUNT 0xFFC01CB0 /* DMA1 Channel 2 Current Inner Loop Count */ | |
361 | #define DMA1_2_CURR_Y_COUNT 0xFFC01CB8 /* DMA1 Channel 2 Current Outer Loop Count */ | |
362 | #define DMA1_2_IRQ_STATUS 0xFFC01CA8 /* DMA1 Channel 2 Interrupt/Status Register */ | |
363 | #define DMA1_2_PERIPHERAL_MAP 0xFFC01CAC /* DMA1 Channel 2 Peripheral Map Register */ | |
364 | ||
365 | #define DMA1_3_CONFIG 0xFFC01CC8 /* DMA1 Channel 3 Configuration register */ | |
366 | #define DMA1_3_NEXT_DESC_PTR 0xFFC01CC0 /* DMA1 Channel 3 Next Descripter Ptr Reg */ | |
367 | #define DMA1_3_START_ADDR 0xFFC01CC4 /* DMA1 Channel 3 Start Address */ | |
368 | #define DMA1_3_X_COUNT 0xFFC01CD0 /* DMA1 Channel 3 Inner Loop Count */ | |
369 | #define DMA1_3_Y_COUNT 0xFFC01CD8 /* DMA1 Channel 3 Outer Loop Count */ | |
370 | #define DMA1_3_X_MODIFY 0xFFC01CD4 /* DMA1 Channel 3 Inner Loop Addr Increment */ | |
371 | #define DMA1_3_Y_MODIFY 0xFFC01CDC /* DMA1 Channel 3 Outer Loop Addr Increment */ | |
372 | #define DMA1_3_CURR_DESC_PTR 0xFFC01CE0 /* DMA1 Channel 3 Current Descriptor Pointer */ | |
373 | #define DMA1_3_CURR_ADDR 0xFFC01CE4 /* DMA1 Channel 3 Current Address Pointer */ | |
374 | #define DMA1_3_CURR_X_COUNT 0xFFC01CF0 /* DMA1 Channel 3 Current Inner Loop Count */ | |
375 | #define DMA1_3_CURR_Y_COUNT 0xFFC01CF8 /* DMA1 Channel 3 Current Outer Loop Count */ | |
376 | #define DMA1_3_IRQ_STATUS 0xFFC01CE8 /* DMA1 Channel 3 Interrupt/Status Register */ | |
377 | #define DMA1_3_PERIPHERAL_MAP 0xFFC01CEC /* DMA1 Channel 3 Peripheral Map Register */ | |
378 | ||
379 | #define DMA1_4_CONFIG 0xFFC01D08 /* DMA1 Channel 4 Configuration register */ | |
380 | #define DMA1_4_NEXT_DESC_PTR 0xFFC01D00 /* DMA1 Channel 4 Next Descripter Ptr Reg */ | |
381 | #define DMA1_4_START_ADDR 0xFFC01D04 /* DMA1 Channel 4 Start Address */ | |
382 | #define DMA1_4_X_COUNT 0xFFC01D10 /* DMA1 Channel 4 Inner Loop Count */ | |
383 | #define DMA1_4_Y_COUNT 0xFFC01D18 /* DMA1 Channel 4 Outer Loop Count */ | |
384 | #define DMA1_4_X_MODIFY 0xFFC01D14 /* DMA1 Channel 4 Inner Loop Addr Increment */ | |
385 | #define DMA1_4_Y_MODIFY 0xFFC01D1C /* DMA1 Channel 4 Outer Loop Addr Increment */ | |
386 | #define DMA1_4_CURR_DESC_PTR 0xFFC01D20 /* DMA1 Channel 4 Current Descriptor Pointer */ | |
387 | #define DMA1_4_CURR_ADDR 0xFFC01D24 /* DMA1 Channel 4 Current Address Pointer */ | |
388 | #define DMA1_4_CURR_X_COUNT 0xFFC01D30 /* DMA1 Channel 4 Current Inner Loop Count */ | |
389 | #define DMA1_4_CURR_Y_COUNT 0xFFC01D38 /* DMA1 Channel 4 Current Outer Loop Count */ | |
390 | #define DMA1_4_IRQ_STATUS 0xFFC01D28 /* DMA1 Channel 4 Interrupt/Status Register */ | |
391 | #define DMA1_4_PERIPHERAL_MAP 0xFFC01D2C /* DMA1 Channel 4 Peripheral Map Register */ | |
392 | ||
393 | #define DMA1_5_CONFIG 0xFFC01D48 /* DMA1 Channel 5 Configuration register */ | |
394 | #define DMA1_5_NEXT_DESC_PTR 0xFFC01D40 /* DMA1 Channel 5 Next Descripter Ptr Reg */ | |
395 | #define DMA1_5_START_ADDR 0xFFC01D44 /* DMA1 Channel 5 Start Address */ | |
396 | #define DMA1_5_X_COUNT 0xFFC01D50 /* DMA1 Channel 5 Inner Loop Count */ | |
397 | #define DMA1_5_Y_COUNT 0xFFC01D58 /* DMA1 Channel 5 Outer Loop Count */ | |
398 | #define DMA1_5_X_MODIFY 0xFFC01D54 /* DMA1 Channel 5 Inner Loop Addr Increment */ | |
399 | #define DMA1_5_Y_MODIFY 0xFFC01D5C /* DMA1 Channel 5 Outer Loop Addr Increment */ | |
400 | #define DMA1_5_CURR_DESC_PTR 0xFFC01D60 /* DMA1 Channel 5 Current Descriptor Pointer */ | |
401 | #define DMA1_5_CURR_ADDR 0xFFC01D64 /* DMA1 Channel 5 Current Address Pointer */ | |
402 | #define DMA1_5_CURR_X_COUNT 0xFFC01D70 /* DMA1 Channel 5 Current Inner Loop Count */ | |
403 | #define DMA1_5_CURR_Y_COUNT 0xFFC01D78 /* DMA1 Channel 5 Current Outer Loop Count */ | |
404 | #define DMA1_5_IRQ_STATUS 0xFFC01D68 /* DMA1 Channel 5 Interrupt/Status Register */ | |
405 | #define DMA1_5_PERIPHERAL_MAP 0xFFC01D6C /* DMA1 Channel 5 Peripheral Map Register */ | |
406 | ||
407 | #define DMA1_6_CONFIG 0xFFC01D88 /* DMA1 Channel 6 Configuration register */ | |
408 | #define DMA1_6_NEXT_DESC_PTR 0xFFC01D80 /* DMA1 Channel 6 Next Descripter Ptr Reg */ | |
409 | #define DMA1_6_START_ADDR 0xFFC01D84 /* DMA1 Channel 6 Start Address */ | |
410 | #define DMA1_6_X_COUNT 0xFFC01D90 /* DMA1 Channel 6 Inner Loop Count */ | |
411 | #define DMA1_6_Y_COUNT 0xFFC01D98 /* DMA1 Channel 6 Outer Loop Count */ | |
412 | #define DMA1_6_X_MODIFY 0xFFC01D94 /* DMA1 Channel 6 Inner Loop Addr Increment */ | |
413 | #define DMA1_6_Y_MODIFY 0xFFC01D9C /* DMA1 Channel 6 Outer Loop Addr Increment */ | |
414 | #define DMA1_6_CURR_DESC_PTR 0xFFC01DA0 /* DMA1 Channel 6 Current Descriptor Pointer */ | |
415 | #define DMA1_6_CURR_ADDR 0xFFC01DA4 /* DMA1 Channel 6 Current Address Pointer */ | |
416 | #define DMA1_6_CURR_X_COUNT 0xFFC01DB0 /* DMA1 Channel 6 Current Inner Loop Count */ | |
417 | #define DMA1_6_CURR_Y_COUNT 0xFFC01DB8 /* DMA1 Channel 6 Current Outer Loop Count */ | |
418 | #define DMA1_6_IRQ_STATUS 0xFFC01DA8 /* DMA1 Channel 6 Interrupt/Status Register */ | |
419 | #define DMA1_6_PERIPHERAL_MAP 0xFFC01DAC /* DMA1 Channel 6 Peripheral Map Register */ | |
420 | ||
421 | #define DMA1_7_CONFIG 0xFFC01DC8 /* DMA1 Channel 7 Configuration register */ | |
422 | #define DMA1_7_NEXT_DESC_PTR 0xFFC01DC0 /* DMA1 Channel 7 Next Descripter Ptr Reg */ | |
423 | #define DMA1_7_START_ADDR 0xFFC01DC4 /* DMA1 Channel 7 Start Address */ | |
424 | #define DMA1_7_X_COUNT 0xFFC01DD0 /* DMA1 Channel 7 Inner Loop Count */ | |
425 | #define DMA1_7_Y_COUNT 0xFFC01DD8 /* DMA1 Channel 7 Outer Loop Count */ | |
426 | #define DMA1_7_X_MODIFY 0xFFC01DD4 /* DMA1 Channel 7 Inner Loop Addr Increment */ | |
427 | #define DMA1_7_Y_MODIFY 0xFFC01DDC /* DMA1 Channel 7 Outer Loop Addr Increment */ | |
428 | #define DMA1_7_CURR_DESC_PTR 0xFFC01DE0 /* DMA1 Channel 7 Current Descriptor Pointer */ | |
429 | #define DMA1_7_CURR_ADDR 0xFFC01DE4 /* DMA1 Channel 7 Current Address Pointer */ | |
430 | #define DMA1_7_CURR_X_COUNT 0xFFC01DF0 /* DMA1 Channel 7 Current Inner Loop Count */ | |
431 | #define DMA1_7_CURR_Y_COUNT 0xFFC01DF8 /* DMA1 Channel 7 Current Outer Loop Count */ | |
432 | #define DMA1_7_IRQ_STATUS 0xFFC01DE8 /* DMA1 Channel 7 Interrupt/Status Register */ | |
433 | #define DMA1_7_PERIPHERAL_MAP 0xFFC01DEC /* DMA1 Channel 7 Peripheral Map Register */ | |
434 | ||
435 | #define DMA1_8_CONFIG 0xFFC01E08 /* DMA1 Channel 8 Configuration register */ | |
436 | #define DMA1_8_NEXT_DESC_PTR 0xFFC01E00 /* DMA1 Channel 8 Next Descripter Ptr Reg */ | |
437 | #define DMA1_8_START_ADDR 0xFFC01E04 /* DMA1 Channel 8 Start Address */ | |
438 | #define DMA1_8_X_COUNT 0xFFC01E10 /* DMA1 Channel 8 Inner Loop Count */ | |
439 | #define DMA1_8_Y_COUNT 0xFFC01E18 /* DMA1 Channel 8 Outer Loop Count */ | |
440 | #define DMA1_8_X_MODIFY 0xFFC01E14 /* DMA1 Channel 8 Inner Loop Addr Increment */ | |
441 | #define DMA1_8_Y_MODIFY 0xFFC01E1C /* DMA1 Channel 8 Outer Loop Addr Increment */ | |
442 | #define DMA1_8_CURR_DESC_PTR 0xFFC01E20 /* DMA1 Channel 8 Current Descriptor Pointer */ | |
443 | #define DMA1_8_CURR_ADDR 0xFFC01E24 /* DMA1 Channel 8 Current Address Pointer */ | |
444 | #define DMA1_8_CURR_X_COUNT 0xFFC01E30 /* DMA1 Channel 8 Current Inner Loop Count */ | |
445 | #define DMA1_8_CURR_Y_COUNT 0xFFC01E38 /* DMA1 Channel 8 Current Outer Loop Count */ | |
446 | #define DMA1_8_IRQ_STATUS 0xFFC01E28 /* DMA1 Channel 8 Interrupt/Status Register */ | |
447 | #define DMA1_8_PERIPHERAL_MAP 0xFFC01E2C /* DMA1 Channel 8 Peripheral Map Register */ | |
448 | ||
449 | #define DMA1_9_CONFIG 0xFFC01E48 /* DMA1 Channel 9 Configuration register */ | |
450 | #define DMA1_9_NEXT_DESC_PTR 0xFFC01E40 /* DMA1 Channel 9 Next Descripter Ptr Reg */ | |
451 | #define DMA1_9_START_ADDR 0xFFC01E44 /* DMA1 Channel 9 Start Address */ | |
452 | #define DMA1_9_X_COUNT 0xFFC01E50 /* DMA1 Channel 9 Inner Loop Count */ | |
453 | #define DMA1_9_Y_COUNT 0xFFC01E58 /* DMA1 Channel 9 Outer Loop Count */ | |
454 | #define DMA1_9_X_MODIFY 0xFFC01E54 /* DMA1 Channel 9 Inner Loop Addr Increment */ | |
455 | #define DMA1_9_Y_MODIFY 0xFFC01E5C /* DMA1 Channel 9 Outer Loop Addr Increment */ | |
456 | #define DMA1_9_CURR_DESC_PTR 0xFFC01E60 /* DMA1 Channel 9 Current Descriptor Pointer */ | |
457 | #define DMA1_9_CURR_ADDR 0xFFC01E64 /* DMA1 Channel 9 Current Address Pointer */ | |
458 | #define DMA1_9_CURR_X_COUNT 0xFFC01E70 /* DMA1 Channel 9 Current Inner Loop Count */ | |
459 | #define DMA1_9_CURR_Y_COUNT 0xFFC01E78 /* DMA1 Channel 9 Current Outer Loop Count */ | |
460 | #define DMA1_9_IRQ_STATUS 0xFFC01E68 /* DMA1 Channel 9 Interrupt/Status Register */ | |
461 | #define DMA1_9_PERIPHERAL_MAP 0xFFC01E6C /* DMA1 Channel 9 Peripheral Map Register */ | |
462 | ||
463 | #define DMA1_10_CONFIG 0xFFC01E88 /* DMA1 Channel 10 Configuration register */ | |
464 | #define DMA1_10_NEXT_DESC_PTR 0xFFC01E80 /* DMA1 Channel 10 Next Descripter Ptr Reg */ | |
465 | #define DMA1_10_START_ADDR 0xFFC01E84 /* DMA1 Channel 10 Start Address */ | |
466 | #define DMA1_10_X_COUNT 0xFFC01E90 /* DMA1 Channel 10 Inner Loop Count */ | |
467 | #define DMA1_10_Y_COUNT 0xFFC01E98 /* DMA1 Channel 10 Outer Loop Count */ | |
468 | #define DMA1_10_X_MODIFY 0xFFC01E94 /* DMA1 Channel 10 Inner Loop Addr Increment */ | |
469 | #define DMA1_10_Y_MODIFY 0xFFC01E9C /* DMA1 Channel 10 Outer Loop Addr Increment */ | |
470 | #define DMA1_10_CURR_DESC_PTR 0xFFC01EA0 /* DMA1 Channel 10 Current Descriptor Pointer */ | |
471 | #define DMA1_10_CURR_ADDR 0xFFC01EA4 /* DMA1 Channel 10 Current Address Pointer */ | |
472 | #define DMA1_10_CURR_X_COUNT 0xFFC01EB0 /* DMA1 Channel 10 Current Inner Loop Count */ | |
473 | #define DMA1_10_CURR_Y_COUNT 0xFFC01EB8 /* DMA1 Channel 10 Current Outer Loop Count */ | |
474 | #define DMA1_10_IRQ_STATUS 0xFFC01EA8 /* DMA1 Channel 10 Interrupt/Status Register */ | |
475 | #define DMA1_10_PERIPHERAL_MAP 0xFFC01EAC /* DMA1 Channel 10 Peripheral Map Register */ | |
476 | ||
477 | #define DMA1_11_CONFIG 0xFFC01EC8 /* DMA1 Channel 11 Configuration register */ | |
478 | #define DMA1_11_NEXT_DESC_PTR 0xFFC01EC0 /* DMA1 Channel 11 Next Descripter Ptr Reg */ | |
479 | #define DMA1_11_START_ADDR 0xFFC01EC4 /* DMA1 Channel 11 Start Address */ | |
480 | #define DMA1_11_X_COUNT 0xFFC01ED0 /* DMA1 Channel 11 Inner Loop Count */ | |
481 | #define DMA1_11_Y_COUNT 0xFFC01ED8 /* DMA1 Channel 11 Outer Loop Count */ | |
482 | #define DMA1_11_X_MODIFY 0xFFC01ED4 /* DMA1 Channel 11 Inner Loop Addr Increment */ | |
483 | #define DMA1_11_Y_MODIFY 0xFFC01EDC /* DMA1 Channel 11 Outer Loop Addr Increment */ | |
484 | #define DMA1_11_CURR_DESC_PTR 0xFFC01EE0 /* DMA1 Channel 11 Current Descriptor Pointer */ | |
485 | #define DMA1_11_CURR_ADDR 0xFFC01EE4 /* DMA1 Channel 11 Current Address Pointer */ | |
486 | #define DMA1_11_CURR_X_COUNT 0xFFC01EF0 /* DMA1 Channel 11 Current Inner Loop Count */ | |
487 | #define DMA1_11_CURR_Y_COUNT 0xFFC01EF8 /* DMA1 Channel 11 Current Outer Loop Count */ | |
488 | #define DMA1_11_IRQ_STATUS 0xFFC01EE8 /* DMA1 Channel 11 Interrupt/Status Register */ | |
489 | #define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC /* DMA1 Channel 11 Peripheral Map Register */ | |
490 | ||
491 | /* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */ | |
492 | #define MDMA1_D0_CONFIG 0xFFC01F08 /*MemDMA1 Stream 0 Destination Configuration */ | |
493 | #define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00 /*MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */ | |
494 | #define MDMA1_D0_START_ADDR 0xFFC01F04 /*MemDMA1 Stream 0 Destination Start Address */ | |
495 | #define MDMA1_D0_X_COUNT 0xFFC01F10 /*MemDMA1 Stream 0 Destination Inner-Loop Count */ | |
496 | #define MDMA1_D0_Y_COUNT 0xFFC01F18 /*MemDMA1 Stream 0 Destination Outer-Loop Count */ | |
497 | #define MDMA1_D0_X_MODIFY 0xFFC01F14 /*MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */ | |
498 | #define MDMA1_D0_Y_MODIFY 0xFFC01F1C /*MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */ | |
499 | #define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20 /*MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */ | |
500 | #define MDMA1_D0_CURR_ADDR 0xFFC01F24 /*MemDMA1 Stream 0 Destination Current Address */ | |
501 | #define MDMA1_D0_CURR_X_COUNT 0xFFC01F30 /*MemDMA1 Stream 0 Dest Current Inner-Loop Count */ | |
502 | #define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38 /*MemDMA1 Stream 0 Dest Current Outer-Loop Count */ | |
503 | #define MDMA1_D0_IRQ_STATUS 0xFFC01F28 /*MemDMA1 Stream 0 Destination Interrupt/Status */ | |
504 | #define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C /*MemDMA1 Stream 0 Destination Peripheral Map */ | |
505 | ||
506 | #define MDMA1_S0_CONFIG 0xFFC01F48 /*MemDMA1 Stream 0 Source Configuration */ | |
507 | #define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40 /*MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */ | |
508 | #define MDMA1_S0_START_ADDR 0xFFC01F44 /*MemDMA1 Stream 0 Source Start Address */ | |
509 | #define MDMA1_S0_X_COUNT 0xFFC01F50 /*MemDMA1 Stream 0 Source Inner-Loop Count */ | |
510 | #define MDMA1_S0_Y_COUNT 0xFFC01F58 /*MemDMA1 Stream 0 Source Outer-Loop Count */ | |
511 | #define MDMA1_S0_X_MODIFY 0xFFC01F54 /*MemDMA1 Stream 0 Source Inner-Loop Address-Increment */ | |
512 | #define MDMA1_S0_Y_MODIFY 0xFFC01F5C /*MemDMA1 Stream 0 Source Outer-Loop Address-Increment */ | |
513 | #define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60 /*MemDMA1 Stream 0 Source Current Descriptor Ptr reg */ | |
514 | #define MDMA1_S0_CURR_ADDR 0xFFC01F64 /*MemDMA1 Stream 0 Source Current Address */ | |
515 | #define MDMA1_S0_CURR_X_COUNT 0xFFC01F70 /*MemDMA1 Stream 0 Source Current Inner-Loop Count */ | |
516 | #define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78 /*MemDMA1 Stream 0 Source Current Outer-Loop Count */ | |
517 | #define MDMA1_S0_IRQ_STATUS 0xFFC01F68 /*MemDMA1 Stream 0 Source Interrupt/Status */ | |
518 | #define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C /*MemDMA1 Stream 0 Source Peripheral Map */ | |
519 | ||
520 | #define MDMA1_D1_CONFIG 0xFFC01F88 /*MemDMA1 Stream 1 Destination Configuration */ | |
521 | #define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80 /*MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */ | |
522 | #define MDMA1_D1_START_ADDR 0xFFC01F84 /*MemDMA1 Stream 1 Destination Start Address */ | |
523 | #define MDMA1_D1_X_COUNT 0xFFC01F90 /*MemDMA1 Stream 1 Destination Inner-Loop Count */ | |
524 | #define MDMA1_D1_Y_COUNT 0xFFC01F98 /*MemDMA1 Stream 1 Destination Outer-Loop Count */ | |
525 | #define MDMA1_D1_X_MODIFY 0xFFC01F94 /*MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */ | |
526 | #define MDMA1_D1_Y_MODIFY 0xFFC01F9C /*MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */ | |
527 | #define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0 /*MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */ | |
528 | #define MDMA1_D1_CURR_ADDR 0xFFC01FA4 /*MemDMA1 Stream 1 Dest Current Address */ | |
529 | #define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0 /*MemDMA1 Stream 1 Dest Current Inner-Loop Count */ | |
530 | #define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8 /*MemDMA1 Stream 1 Dest Current Outer-Loop Count */ | |
531 | #define MDMA1_D1_IRQ_STATUS 0xFFC01FA8 /*MemDMA1 Stream 1 Dest Interrupt/Status */ | |
532 | #define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC /*MemDMA1 Stream 1 Dest Peripheral Map */ | |
533 | ||
534 | #define MDMA1_S1_CONFIG 0xFFC01FC8 /*MemDMA1 Stream 1 Source Configuration */ | |
535 | #define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0 /*MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */ | |
536 | #define MDMA1_S1_START_ADDR 0xFFC01FC4 /*MemDMA1 Stream 1 Source Start Address */ | |
537 | #define MDMA1_S1_X_COUNT 0xFFC01FD0 /*MemDMA1 Stream 1 Source Inner-Loop Count */ | |
538 | #define MDMA1_S1_Y_COUNT 0xFFC01FD8 /*MemDMA1 Stream 1 Source Outer-Loop Count */ | |
539 | #define MDMA1_S1_X_MODIFY 0xFFC01FD4 /*MemDMA1 Stream 1 Source Inner-Loop Address-Increment */ | |
540 | #define MDMA1_S1_Y_MODIFY 0xFFC01FDC /*MemDMA1 Stream 1 Source Outer-Loop Address-Increment */ | |
541 | #define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0 /*MemDMA1 Stream 1 Source Current Descriptor Ptr reg */ | |
542 | #define MDMA1_S1_CURR_ADDR 0xFFC01FE4 /*MemDMA1 Stream 1 Source Current Address */ | |
543 | #define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0 /*MemDMA1 Stream 1 Source Current Inner-Loop Count */ | |
544 | #define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8 /*MemDMA1 Stream 1 Source Current Outer-Loop Count */ | |
545 | #define MDMA1_S1_IRQ_STATUS 0xFFC01FE8 /*MemDMA1 Stream 1 Source Interrupt/Status */ | |
546 | #define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC /*MemDMA1 Stream 1 Source Peripheral Map */ | |
547 | ||
548 | /* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */ | |
549 | #define DMA2_0_CONFIG 0xFFC00C08 /* DMA2 Channel 0 Configuration register */ | |
550 | #define DMA2_0_NEXT_DESC_PTR 0xFFC00C00 /* DMA2 Channel 0 Next Descripter Ptr Reg */ | |
551 | #define DMA2_0_START_ADDR 0xFFC00C04 /* DMA2 Channel 0 Start Address */ | |
552 | #define DMA2_0_X_COUNT 0xFFC00C10 /* DMA2 Channel 0 Inner Loop Count */ | |
553 | #define DMA2_0_Y_COUNT 0xFFC00C18 /* DMA2 Channel 0 Outer Loop Count */ | |
554 | #define DMA2_0_X_MODIFY 0xFFC00C14 /* DMA2 Channel 0 Inner Loop Addr Increment */ | |
555 | #define DMA2_0_Y_MODIFY 0xFFC00C1C /* DMA2 Channel 0 Outer Loop Addr Increment */ | |
556 | #define DMA2_0_CURR_DESC_PTR 0xFFC00C20 /* DMA2 Channel 0 Current Descriptor Pointer */ | |
557 | #define DMA2_0_CURR_ADDR 0xFFC00C24 /* DMA2 Channel 0 Current Address Pointer */ | |
558 | #define DMA2_0_CURR_X_COUNT 0xFFC00C30 /* DMA2 Channel 0 Current Inner Loop Count */ | |
559 | #define DMA2_0_CURR_Y_COUNT 0xFFC00C38 /* DMA2 Channel 0 Current Outer Loop Count */ | |
560 | #define DMA2_0_IRQ_STATUS 0xFFC00C28 /* DMA2 Channel 0 Interrupt/Status Register */ | |
561 | #define DMA2_0_PERIPHERAL_MAP 0xFFC00C2C /* DMA2 Channel 0 Peripheral Map Register */ | |
562 | ||
563 | #define DMA2_1_CONFIG 0xFFC00C48 /* DMA2 Channel 1 Configuration register */ | |
564 | #define DMA2_1_NEXT_DESC_PTR 0xFFC00C40 /* DMA2 Channel 1 Next Descripter Ptr Reg */ | |
565 | #define DMA2_1_START_ADDR 0xFFC00C44 /* DMA2 Channel 1 Start Address */ | |
566 | #define DMA2_1_X_COUNT 0xFFC00C50 /* DMA2 Channel 1 Inner Loop Count */ | |
567 | #define DMA2_1_Y_COUNT 0xFFC00C58 /* DMA2 Channel 1 Outer Loop Count */ | |
568 | #define DMA2_1_X_MODIFY 0xFFC00C54 /* DMA2 Channel 1 Inner Loop Addr Increment */ | |
569 | #define DMA2_1_Y_MODIFY 0xFFC00C5C /* DMA2 Channel 1 Outer Loop Addr Increment */ | |
570 | #define DMA2_1_CURR_DESC_PTR 0xFFC00C60 /* DMA2 Channel 1 Current Descriptor Pointer */ | |
571 | #define DMA2_1_CURR_ADDR 0xFFC00C64 /* DMA2 Channel 1 Current Address Pointer */ | |
572 | #define DMA2_1_CURR_X_COUNT 0xFFC00C70 /* DMA2 Channel 1 Current Inner Loop Count */ | |
573 | #define DMA2_1_CURR_Y_COUNT 0xFFC00C78 /* DMA2 Channel 1 Current Outer Loop Count */ | |
574 | #define DMA2_1_IRQ_STATUS 0xFFC00C68 /* DMA2 Channel 1 Interrupt/Status Register */ | |
575 | #define DMA2_1_PERIPHERAL_MAP 0xFFC00C6C /* DMA2 Channel 1 Peripheral Map Register */ | |
576 | ||
577 | #define DMA2_2_CONFIG 0xFFC00C88 /* DMA2 Channel 2 Configuration register */ | |
578 | #define DMA2_2_NEXT_DESC_PTR 0xFFC00C80 /* DMA2 Channel 2 Next Descripter Ptr Reg */ | |
579 | #define DMA2_2_START_ADDR 0xFFC00C84 /* DMA2 Channel 2 Start Address */ | |
580 | #define DMA2_2_X_COUNT 0xFFC00C90 /* DMA2 Channel 2 Inner Loop Count */ | |
581 | #define DMA2_2_Y_COUNT 0xFFC00C98 /* DMA2 Channel 2 Outer Loop Count */ | |
582 | #define DMA2_2_X_MODIFY 0xFFC00C94 /* DMA2 Channel 2 Inner Loop Addr Increment */ | |
583 | #define DMA2_2_Y_MODIFY 0xFFC00C9C /* DMA2 Channel 2 Outer Loop Addr Increment */ | |
584 | #define DMA2_2_CURR_DESC_PTR 0xFFC00CA0 /* DMA2 Channel 2 Current Descriptor Pointer */ | |
585 | #define DMA2_2_CURR_ADDR 0xFFC00CA4 /* DMA2 Channel 2 Current Address Pointer */ | |
586 | #define DMA2_2_CURR_X_COUNT 0xFFC00CB0 /* DMA2 Channel 2 Current Inner Loop Count */ | |
587 | #define DMA2_2_CURR_Y_COUNT 0xFFC00CB8 /* DMA2 Channel 2 Current Outer Loop Count */ | |
588 | #define DMA2_2_IRQ_STATUS 0xFFC00CA8 /* DMA2 Channel 2 Interrupt/Status Register */ | |
589 | #define DMA2_2_PERIPHERAL_MAP 0xFFC00CAC /* DMA2 Channel 2 Peripheral Map Register */ | |
590 | ||
591 | #define DMA2_3_CONFIG 0xFFC00CC8 /* DMA2 Channel 3 Configuration register */ | |
592 | #define DMA2_3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA2 Channel 3 Next Descripter Ptr Reg */ | |
593 | #define DMA2_3_START_ADDR 0xFFC00CC4 /* DMA2 Channel 3 Start Address */ | |
594 | #define DMA2_3_X_COUNT 0xFFC00CD0 /* DMA2 Channel 3 Inner Loop Count */ | |
595 | #define DMA2_3_Y_COUNT 0xFFC00CD8 /* DMA2 Channel 3 Outer Loop Count */ | |
596 | #define DMA2_3_X_MODIFY 0xFFC00CD4 /* DMA2 Channel 3 Inner Loop Addr Increment */ | |
597 | #define DMA2_3_Y_MODIFY 0xFFC00CDC /* DMA2 Channel 3 Outer Loop Addr Increment */ | |
598 | #define DMA2_3_CURR_DESC_PTR 0xFFC00CE0 /* DMA2 Channel 3 Current Descriptor Pointer */ | |
599 | #define DMA2_3_CURR_ADDR 0xFFC00CE4 /* DMA2 Channel 3 Current Address Pointer */ | |
600 | #define DMA2_3_CURR_X_COUNT 0xFFC00CF0 /* DMA2 Channel 3 Current Inner Loop Count */ | |
601 | #define DMA2_3_CURR_Y_COUNT 0xFFC00CF8 /* DMA2 Channel 3 Current Outer Loop Count */ | |
602 | #define DMA2_3_IRQ_STATUS 0xFFC00CE8 /* DMA2 Channel 3 Interrupt/Status Register */ | |
603 | #define DMA2_3_PERIPHERAL_MAP 0xFFC00CEC /* DMA2 Channel 3 Peripheral Map Register */ | |
604 | ||
605 | #define DMA2_4_CONFIG 0xFFC00D08 /* DMA2 Channel 4 Configuration register */ | |
606 | #define DMA2_4_NEXT_DESC_PTR 0xFFC00D00 /* DMA2 Channel 4 Next Descripter Ptr Reg */ | |
607 | #define DMA2_4_START_ADDR 0xFFC00D04 /* DMA2 Channel 4 Start Address */ | |
608 | #define DMA2_4_X_COUNT 0xFFC00D10 /* DMA2 Channel 4 Inner Loop Count */ | |
609 | #define DMA2_4_Y_COUNT 0xFFC00D18 /* DMA2 Channel 4 Outer Loop Count */ | |
610 | #define DMA2_4_X_MODIFY 0xFFC00D14 /* DMA2 Channel 4 Inner Loop Addr Increment */ | |
611 | #define DMA2_4_Y_MODIFY 0xFFC00D1C /* DMA2 Channel 4 Outer Loop Addr Increment */ | |
612 | #define DMA2_4_CURR_DESC_PTR 0xFFC00D20 /* DMA2 Channel 4 Current Descriptor Pointer */ | |
613 | #define DMA2_4_CURR_ADDR 0xFFC00D24 /* DMA2 Channel 4 Current Address Pointer */ | |
614 | #define DMA2_4_CURR_X_COUNT 0xFFC00D30 /* DMA2 Channel 4 Current Inner Loop Count */ | |
615 | #define DMA2_4_CURR_Y_COUNT 0xFFC00D38 /* DMA2 Channel 4 Current Outer Loop Count */ | |
616 | #define DMA2_4_IRQ_STATUS 0xFFC00D28 /* DMA2 Channel 4 Interrupt/Status Register */ | |
617 | #define DMA2_4_PERIPHERAL_MAP 0xFFC00D2C /* DMA2 Channel 4 Peripheral Map Register */ | |
618 | ||
619 | #define DMA2_5_CONFIG 0xFFC00D48 /* DMA2 Channel 5 Configuration register */ | |
620 | #define DMA2_5_NEXT_DESC_PTR 0xFFC00D40 /* DMA2 Channel 5 Next Descripter Ptr Reg */ | |
621 | #define DMA2_5_START_ADDR 0xFFC00D44 /* DMA2 Channel 5 Start Address */ | |
622 | #define DMA2_5_X_COUNT 0xFFC00D50 /* DMA2 Channel 5 Inner Loop Count */ | |
623 | #define DMA2_5_Y_COUNT 0xFFC00D58 /* DMA2 Channel 5 Outer Loop Count */ | |
624 | #define DMA2_5_X_MODIFY 0xFFC00D54 /* DMA2 Channel 5 Inner Loop Addr Increment */ | |
625 | #define DMA2_5_Y_MODIFY 0xFFC00D5C /* DMA2 Channel 5 Outer Loop Addr Increment */ | |
626 | #define DMA2_5_CURR_DESC_PTR 0xFFC00D60 /* DMA2 Channel 5 Current Descriptor Pointer */ | |
627 | #define DMA2_5_CURR_ADDR 0xFFC00D64 /* DMA2 Channel 5 Current Address Pointer */ | |
628 | #define DMA2_5_CURR_X_COUNT 0xFFC00D70 /* DMA2 Channel 5 Current Inner Loop Count */ | |
629 | #define DMA2_5_CURR_Y_COUNT 0xFFC00D78 /* DMA2 Channel 5 Current Outer Loop Count */ | |
630 | #define DMA2_5_IRQ_STATUS 0xFFC00D68 /* DMA2 Channel 5 Interrupt/Status Register */ | |
631 | #define DMA2_5_PERIPHERAL_MAP 0xFFC00D6C /* DMA2 Channel 5 Peripheral Map Register */ | |
632 | ||
633 | #define DMA2_6_CONFIG 0xFFC00D88 /* DMA2 Channel 6 Configuration register */ | |
634 | #define DMA2_6_NEXT_DESC_PTR 0xFFC00D80 /* DMA2 Channel 6 Next Descripter Ptr Reg */ | |
635 | #define DMA2_6_START_ADDR 0xFFC00D84 /* DMA2 Channel 6 Start Address */ | |
636 | #define DMA2_6_X_COUNT 0xFFC00D90 /* DMA2 Channel 6 Inner Loop Count */ | |
637 | #define DMA2_6_Y_COUNT 0xFFC00D98 /* DMA2 Channel 6 Outer Loop Count */ | |
638 | #define DMA2_6_X_MODIFY 0xFFC00D94 /* DMA2 Channel 6 Inner Loop Addr Increment */ | |
639 | #define DMA2_6_Y_MODIFY 0xFFC00D9C /* DMA2 Channel 6 Outer Loop Addr Increment */ | |
640 | #define DMA2_6_CURR_DESC_PTR 0xFFC00DA0 /* DMA2 Channel 6 Current Descriptor Pointer */ | |
641 | #define DMA2_6_CURR_ADDR 0xFFC00DA4 /* DMA2 Channel 6 Current Address Pointer */ | |
642 | #define DMA2_6_CURR_X_COUNT 0xFFC00DB0 /* DMA2 Channel 6 Current Inner Loop Count */ | |
643 | #define DMA2_6_CURR_Y_COUNT 0xFFC00DB8 /* DMA2 Channel 6 Current Outer Loop Count */ | |
644 | #define DMA2_6_IRQ_STATUS 0xFFC00DA8 /* DMA2 Channel 6 Interrupt/Status Register */ | |
645 | #define DMA2_6_PERIPHERAL_MAP 0xFFC00DAC /* DMA2 Channel 6 Peripheral Map Register */ | |
646 | ||
647 | #define DMA2_7_CONFIG 0xFFC00DC8 /* DMA2 Channel 7 Configuration register */ | |
648 | #define DMA2_7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA2 Channel 7 Next Descripter Ptr Reg */ | |
649 | #define DMA2_7_START_ADDR 0xFFC00DC4 /* DMA2 Channel 7 Start Address */ | |
650 | #define DMA2_7_X_COUNT 0xFFC00DD0 /* DMA2 Channel 7 Inner Loop Count */ | |
651 | #define DMA2_7_Y_COUNT 0xFFC00DD8 /* DMA2 Channel 7 Outer Loop Count */ | |
652 | #define DMA2_7_X_MODIFY 0xFFC00DD4 /* DMA2 Channel 7 Inner Loop Addr Increment */ | |
653 | #define DMA2_7_Y_MODIFY 0xFFC00DDC /* DMA2 Channel 7 Outer Loop Addr Increment */ | |
654 | #define DMA2_7_CURR_DESC_PTR 0xFFC00DE0 /* DMA2 Channel 7 Current Descriptor Pointer */ | |
655 | #define DMA2_7_CURR_ADDR 0xFFC00DE4 /* DMA2 Channel 7 Current Address Pointer */ | |
656 | #define DMA2_7_CURR_X_COUNT 0xFFC00DF0 /* DMA2 Channel 7 Current Inner Loop Count */ | |
657 | #define DMA2_7_CURR_Y_COUNT 0xFFC00DF8 /* DMA2 Channel 7 Current Outer Loop Count */ | |
658 | #define DMA2_7_IRQ_STATUS 0xFFC00DE8 /* DMA2 Channel 7 Interrupt/Status Register */ | |
659 | #define DMA2_7_PERIPHERAL_MAP 0xFFC00DEC /* DMA2 Channel 7 Peripheral Map Register */ | |
660 | ||
661 | #define DMA2_8_CONFIG 0xFFC00E08 /* DMA2 Channel 8 Configuration register */ | |
662 | #define DMA2_8_NEXT_DESC_PTR 0xFFC00E00 /* DMA2 Channel 8 Next Descripter Ptr Reg */ | |
663 | #define DMA2_8_START_ADDR 0xFFC00E04 /* DMA2 Channel 8 Start Address */ | |
664 | #define DMA2_8_X_COUNT 0xFFC00E10 /* DMA2 Channel 8 Inner Loop Count */ | |
665 | #define DMA2_8_Y_COUNT 0xFFC00E18 /* DMA2 Channel 8 Outer Loop Count */ | |
666 | #define DMA2_8_X_MODIFY 0xFFC00E14 /* DMA2 Channel 8 Inner Loop Addr Increment */ | |
667 | #define DMA2_8_Y_MODIFY 0xFFC00E1C /* DMA2 Channel 8 Outer Loop Addr Increment */ | |
668 | #define DMA2_8_CURR_DESC_PTR 0xFFC00E20 /* DMA2 Channel 8 Current Descriptor Pointer */ | |
669 | #define DMA2_8_CURR_ADDR 0xFFC00E24 /* DMA2 Channel 8 Current Address Pointer */ | |
670 | #define DMA2_8_CURR_X_COUNT 0xFFC00E30 /* DMA2 Channel 8 Current Inner Loop Count */ | |
671 | #define DMA2_8_CURR_Y_COUNT 0xFFC00E38 /* DMA2 Channel 8 Current Outer Loop Count */ | |
672 | #define DMA2_8_IRQ_STATUS 0xFFC00E28 /* DMA2 Channel 8 Interrupt/Status Register */ | |
673 | #define DMA2_8_PERIPHERAL_MAP 0xFFC00E2C /* DMA2 Channel 8 Peripheral Map Register */ | |
674 | ||
675 | #define DMA2_9_CONFIG 0xFFC00E48 /* DMA2 Channel 9 Configuration register */ | |
676 | #define DMA2_9_NEXT_DESC_PTR 0xFFC00E40 /* DMA2 Channel 9 Next Descripter Ptr Reg */ | |
677 | #define DMA2_9_START_ADDR 0xFFC00E44 /* DMA2 Channel 9 Start Address */ | |
678 | #define DMA2_9_X_COUNT 0xFFC00E50 /* DMA2 Channel 9 Inner Loop Count */ | |
679 | #define DMA2_9_Y_COUNT 0xFFC00E58 /* DMA2 Channel 9 Outer Loop Count */ | |
680 | #define DMA2_9_X_MODIFY 0xFFC00E54 /* DMA2 Channel 9 Inner Loop Addr Increment */ | |
681 | #define DMA2_9_Y_MODIFY 0xFFC00E5C /* DMA2 Channel 9 Outer Loop Addr Increment */ | |
682 | #define DMA2_9_CURR_DESC_PTR 0xFFC00E60 /* DMA2 Channel 9 Current Descriptor Pointer */ | |
683 | #define DMA2_9_CURR_ADDR 0xFFC00E64 /* DMA2 Channel 9 Current Address Pointer */ | |
684 | #define DMA2_9_CURR_X_COUNT 0xFFC00E70 /* DMA2 Channel 9 Current Inner Loop Count */ | |
685 | #define DMA2_9_CURR_Y_COUNT 0xFFC00E78 /* DMA2 Channel 9 Current Outer Loop Count */ | |
686 | #define DMA2_9_IRQ_STATUS 0xFFC00E68 /* DMA2 Channel 9 Interrupt/Status Register */ | |
687 | #define DMA2_9_PERIPHERAL_MAP 0xFFC00E6C /* DMA2 Channel 9 Peripheral Map Register */ | |
688 | ||
689 | #define DMA2_10_CONFIG 0xFFC00E88 /* DMA2 Channel 10 Configuration register */ | |
690 | #define DMA2_10_NEXT_DESC_PTR 0xFFC00E80 /* DMA2 Channel 10 Next Descripter Ptr Reg */ | |
691 | #define DMA2_10_START_ADDR 0xFFC00E84 /* DMA2 Channel 10 Start Address */ | |
692 | #define DMA2_10_X_COUNT 0xFFC00E90 /* DMA2 Channel 10 Inner Loop Count */ | |
693 | #define DMA2_10_Y_COUNT 0xFFC00E98 /* DMA2 Channel 10 Outer Loop Count */ | |
694 | #define DMA2_10_X_MODIFY 0xFFC00E94 /* DMA2 Channel 10 Inner Loop Addr Increment */ | |
695 | #define DMA2_10_Y_MODIFY 0xFFC00E9C /* DMA2 Channel 10 Outer Loop Addr Increment */ | |
696 | #define DMA2_10_CURR_DESC_PTR 0xFFC00EA0 /* DMA2 Channel 10 Current Descriptor Pointer */ | |
697 | #define DMA2_10_CURR_ADDR 0xFFC00EA4 /* DMA2 Channel 10 Current Address Pointer */ | |
698 | #define DMA2_10_CURR_X_COUNT 0xFFC00EB0 /* DMA2 Channel 10 Current Inner Loop Count */ | |
699 | #define DMA2_10_CURR_Y_COUNT 0xFFC00EB8 /* DMA2 Channel 10 Current Outer Loop Count */ | |
700 | #define DMA2_10_IRQ_STATUS 0xFFC00EA8 /* DMA2 Channel 10 Interrupt/Status Register */ | |
701 | #define DMA2_10_PERIPHERAL_MAP 0xFFC00EAC /* DMA2 Channel 10 Peripheral Map Register */ | |
702 | ||
703 | #define DMA2_11_CONFIG 0xFFC00EC8 /* DMA2 Channel 11 Configuration register */ | |
704 | #define DMA2_11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA2 Channel 11 Next Descripter Ptr Reg */ | |
705 | #define DMA2_11_START_ADDR 0xFFC00EC4 /* DMA2 Channel 11 Start Address */ | |
706 | #define DMA2_11_X_COUNT 0xFFC00ED0 /* DMA2 Channel 11 Inner Loop Count */ | |
707 | #define DMA2_11_Y_COUNT 0xFFC00ED8 /* DMA2 Channel 11 Outer Loop Count */ | |
708 | #define DMA2_11_X_MODIFY 0xFFC00ED4 /* DMA2 Channel 11 Inner Loop Addr Increment */ | |
709 | #define DMA2_11_Y_MODIFY 0xFFC00EDC /* DMA2 Channel 11 Outer Loop Addr Increment */ | |
710 | #define DMA2_11_CURR_DESC_PTR 0xFFC00EE0 /* DMA2 Channel 11 Current Descriptor Pointer */ | |
711 | #define DMA2_11_CURR_ADDR 0xFFC00EE4 /* DMA2 Channel 11 Current Address Pointer */ | |
712 | #define DMA2_11_CURR_X_COUNT 0xFFC00EF0 /* DMA2 Channel 11 Current Inner Loop Count */ | |
713 | #define DMA2_11_CURR_Y_COUNT 0xFFC00EF8 /* DMA2 Channel 11 Current Outer Loop Count */ | |
714 | #define DMA2_11_IRQ_STATUS 0xFFC00EE8 /* DMA2 Channel 11 Interrupt/Status Register */ | |
715 | #define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC /* DMA2 Channel 11 Peripheral Map Register */ | |
716 | ||
717 | /* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */ | |
718 | #define MDMA2_D0_CONFIG 0xFFC00F08 /*MemDMA2 Stream 0 Destination Configuration register */ | |
719 | #define MDMA2_D0_NEXT_DESC_PTR 0xFFC00F00 /*MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */ | |
720 | #define MDMA2_D0_START_ADDR 0xFFC00F04 /*MemDMA2 Stream 0 Destination Start Address */ | |
721 | #define MDMA2_D0_X_COUNT 0xFFC00F10 /*MemDMA2 Stream 0 Dest Inner-Loop Count register */ | |
722 | #define MDMA2_D0_Y_COUNT 0xFFC00F18 /*MemDMA2 Stream 0 Dest Outer-Loop Count register */ | |
723 | #define MDMA2_D0_X_MODIFY 0xFFC00F14 /*MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */ | |
724 | #define MDMA2_D0_Y_MODIFY 0xFFC00F1C /*MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */ | |
725 | #define MDMA2_D0_CURR_DESC_PTR 0xFFC00F20 /*MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */ | |
726 | #define MDMA2_D0_CURR_ADDR 0xFFC00F24 /*MemDMA2 Stream 0 Destination Current Address */ | |
727 | #define MDMA2_D0_CURR_X_COUNT 0xFFC00F30 /*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */ | |
728 | #define MDMA2_D0_CURR_Y_COUNT 0xFFC00F38 /*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */ | |
729 | #define MDMA2_D0_IRQ_STATUS 0xFFC00F28 /*MemDMA2 Stream 0 Dest Interrupt/Status Register */ | |
730 | #define MDMA2_D0_PERIPHERAL_MAP 0xFFC00F2C /*MemDMA2 Stream 0 Destination Peripheral Map register */ | |
731 | ||
732 | #define MDMA2_S0_CONFIG 0xFFC00F48 /*MemDMA2 Stream 0 Source Configuration register */ | |
733 | #define MDMA2_S0_NEXT_DESC_PTR 0xFFC00F40 /*MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */ | |
734 | #define MDMA2_S0_START_ADDR 0xFFC00F44 /*MemDMA2 Stream 0 Source Start Address */ | |
735 | #define MDMA2_S0_X_COUNT 0xFFC00F50 /*MemDMA2 Stream 0 Source Inner-Loop Count register */ | |
736 | #define MDMA2_S0_Y_COUNT 0xFFC00F58 /*MemDMA2 Stream 0 Source Outer-Loop Count register */ | |
737 | #define MDMA2_S0_X_MODIFY 0xFFC00F54 /*MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */ | |
738 | #define MDMA2_S0_Y_MODIFY 0xFFC00F5C /*MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */ | |
739 | #define MDMA2_S0_CURR_DESC_PTR 0xFFC00F60 /*MemDMA2 Stream 0 Source Current Descriptor Ptr reg */ | |
740 | #define MDMA2_S0_CURR_ADDR 0xFFC00F64 /*MemDMA2 Stream 0 Source Current Address */ | |
741 | #define MDMA2_S0_CURR_X_COUNT 0xFFC00F70 /*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */ | |
742 | #define MDMA2_S0_CURR_Y_COUNT 0xFFC00F78 /*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */ | |
743 | #define MDMA2_S0_IRQ_STATUS 0xFFC00F68 /*MemDMA2 Stream 0 Source Interrupt/Status Register */ | |
744 | #define MDMA2_S0_PERIPHERAL_MAP 0xFFC00F6C /*MemDMA2 Stream 0 Source Peripheral Map register */ | |
745 | ||
746 | #define MDMA2_D1_CONFIG 0xFFC00F88 /*MemDMA2 Stream 1 Destination Configuration register */ | |
747 | #define MDMA2_D1_NEXT_DESC_PTR 0xFFC00F80 /*MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */ | |
748 | #define MDMA2_D1_START_ADDR 0xFFC00F84 /*MemDMA2 Stream 1 Destination Start Address */ | |
749 | #define MDMA2_D1_X_COUNT 0xFFC00F90 /*MemDMA2 Stream 1 Dest Inner-Loop Count register */ | |
750 | #define MDMA2_D1_Y_COUNT 0xFFC00F98 /*MemDMA2 Stream 1 Dest Outer-Loop Count register */ | |
751 | #define MDMA2_D1_X_MODIFY 0xFFC00F94 /*MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */ | |
752 | #define MDMA2_D1_Y_MODIFY 0xFFC00F9C /*MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */ | |
753 | #define MDMA2_D1_CURR_DESC_PTR 0xFFC00FA0 /*MemDMA2 Stream 1 Destination Current Descriptor Ptr */ | |
754 | #define MDMA2_D1_CURR_ADDR 0xFFC00FA4 /*MemDMA2 Stream 1 Destination Current Address reg */ | |
755 | #define MDMA2_D1_CURR_X_COUNT 0xFFC00FB0 /*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */ | |
756 | #define MDMA2_D1_CURR_Y_COUNT 0xFFC00FB8 /*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */ | |
757 | #define MDMA2_D1_IRQ_STATUS 0xFFC00FA8 /*MemDMA2 Stream 1 Destination Interrupt/Status Reg */ | |
758 | #define MDMA2_D1_PERIPHERAL_MAP 0xFFC00FAC /*MemDMA2 Stream 1 Destination Peripheral Map register */ | |
759 | ||
760 | #define MDMA2_S1_CONFIG 0xFFC00FC8 /*MemDMA2 Stream 1 Source Configuration register */ | |
761 | #define MDMA2_S1_NEXT_DESC_PTR 0xFFC00FC0 /*MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */ | |
762 | #define MDMA2_S1_START_ADDR 0xFFC00FC4 /*MemDMA2 Stream 1 Source Start Address */ | |
763 | #define MDMA2_S1_X_COUNT 0xFFC00FD0 /*MemDMA2 Stream 1 Source Inner-Loop Count register */ | |
764 | #define MDMA2_S1_Y_COUNT 0xFFC00FD8 /*MemDMA2 Stream 1 Source Outer-Loop Count register */ | |
765 | #define MDMA2_S1_X_MODIFY 0xFFC00FD4 /*MemDMA2 Stream 1 Src Inner-Loop Address-Increment */ | |
766 | #define MDMA2_S1_Y_MODIFY 0xFFC00FDC /*MemDMA2 Stream 1 Source Outer-Loop Address-Increment */ | |
767 | #define MDMA2_S1_CURR_DESC_PTR 0xFFC00FE0 /*MemDMA2 Stream 1 Source Current Descriptor Ptr reg */ | |
768 | #define MDMA2_S1_CURR_ADDR 0xFFC00FE4 /*MemDMA2 Stream 1 Source Current Address */ | |
769 | #define MDMA2_S1_CURR_X_COUNT 0xFFC00FF0 /*MemDMA2 Stream 1 Source Current Inner-Loop Count */ | |
770 | #define MDMA2_S1_CURR_Y_COUNT 0xFFC00FF8 /*MemDMA2 Stream 1 Source Current Outer-Loop Count */ | |
771 | #define MDMA2_S1_IRQ_STATUS 0xFFC00FE8 /*MemDMA2 Stream 1 Source Interrupt/Status Register */ | |
772 | #define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC /*MemDMA2 Stream 1 Source Peripheral Map register */ | |
773 | ||
f5879fda GY |
774 | #define MDMA_D0_NEXT_DESC_PTR MDMA1_D0_NEXT_DESC_PTR |
775 | #define MDMA_D0_START_ADDR MDMA1_D0_START_ADDR | |
776 | #define MDMA_D0_CONFIG MDMA1_D0_CONFIG | |
777 | #define MDMA_D0_X_COUNT MDMA1_D0_X_COUNT | |
778 | #define MDMA_D0_X_MODIFY MDMA1_D0_X_MODIFY | |
779 | #define MDMA_D0_Y_COUNT MDMA1_D0_Y_COUNT | |
780 | #define MDMA_D0_Y_MODIFY MDMA1_D0_Y_MODIFY | |
781 | #define MDMA_D0_CURR_DESC_PTR MDMA1_D0_CURR_DESC_PTR | |
782 | #define MDMA_D0_CURR_ADDR MDMA1_D0_CURR_ADDR | |
783 | #define MDMA_D0_IRQ_STATUS MDMA1_D0_IRQ_STATUS | |
784 | #define MDMA_D0_PERIPHERAL_MAP MDMA1_D0_PERIPHERAL_MAP | |
785 | #define MDMA_D0_CURR_X_COUNT MDMA1_D0_CURR_X_COUNT | |
786 | #define MDMA_D0_CURR_Y_COUNT MDMA1_D0_CURR_Y_COUNT | |
787 | ||
788 | #define MDMA_S0_NEXT_DESC_PTR MDMA1_S0_NEXT_DESC_PTR | |
789 | #define MDMA_S0_START_ADDR MDMA1_S0_START_ADDR | |
790 | #define MDMA_S0_CONFIG MDMA1_S0_CONFIG | |
791 | #define MDMA_S0_X_COUNT MDMA1_S0_X_COUNT | |
792 | #define MDMA_S0_X_MODIFY MDMA1_S0_X_MODIFY | |
793 | #define MDMA_S0_Y_COUNT MDMA1_S0_Y_COUNT | |
794 | #define MDMA_S0_Y_MODIFY MDMA1_S0_Y_MODIFY | |
795 | #define MDMA_S0_CURR_DESC_PTR MDMA1_S0_CURR_DESC_PTR | |
796 | #define MDMA_S0_CURR_ADDR MDMA1_S0_CURR_ADDR | |
797 | #define MDMA_S0_IRQ_STATUS MDMA1_S0_IRQ_STATUS | |
798 | #define MDMA_S0_PERIPHERAL_MAP MDMA1_S0_PERIPHERAL_MAP | |
799 | #define MDMA_S0_CURR_X_COUNT MDMA1_S0_CURR_X_COUNT | |
800 | #define MDMA_S0_CURR_Y_COUNT MDMA1_S0_CURR_Y_COUNT | |
801 | ||
802 | #define MDMA_D1_NEXT_DESC_PTR MDMA1_D1_NEXT_DESC_PTR | |
803 | #define MDMA_D1_START_ADDR MDMA1_D1_START_ADDR | |
804 | #define MDMA_D1_CONFIG MDMA1_D1_CONFIG | |
805 | #define MDMA_D1_X_COUNT MDMA1_D1_X_COUNT | |
806 | #define MDMA_D1_X_MODIFY MDMA1_D1_X_MODIFY | |
807 | #define MDMA_D1_Y_COUNT MDMA1_D1_Y_COUNT | |
808 | #define MDMA_D1_Y_MODIFY MDMA1_D1_Y_MODIFY | |
809 | #define MDMA_D1_CURR_DESC_PTR MDMA1_D1_CURR_DESC_PTR | |
810 | #define MDMA_D1_CURR_ADDR MDMA1_D1_CURR_ADDR | |
811 | #define MDMA_D1_IRQ_STATUS MDMA1_D1_IRQ_STATUS | |
812 | #define MDMA_D1_PERIPHERAL_MAP MDMA1_D1_PERIPHERAL_MAP | |
813 | #define MDMA_D1_CURR_X_COUNT MDMA1_D1_CURR_X_COUNT | |
814 | #define MDMA_D1_CURR_Y_COUNT MDMA1_D1_CURR_Y_COUNT | |
815 | ||
816 | #define MDMA_S1_NEXT_DESC_PTR MDMA1_S1_NEXT_DESC_PTR | |
817 | #define MDMA_S1_START_ADDR MDMA1_S1_START_ADDR | |
818 | #define MDMA_S1_CONFIG MDMA1_S1_CONFIG | |
819 | #define MDMA_S1_X_COUNT MDMA1_S1_X_COUNT | |
820 | #define MDMA_S1_X_MODIFY MDMA1_S1_X_MODIFY | |
821 | #define MDMA_S1_Y_COUNT MDMA1_S1_Y_COUNT | |
822 | #define MDMA_S1_Y_MODIFY MDMA1_S1_Y_MODIFY | |
823 | #define MDMA_S1_CURR_DESC_PTR MDMA1_S1_CURR_DESC_PTR | |
824 | #define MDMA_S1_CURR_ADDR MDMA1_S1_CURR_ADDR | |
825 | #define MDMA_S1_IRQ_STATUS MDMA1_S1_IRQ_STATUS | |
826 | #define MDMA_S1_PERIPHERAL_MAP MDMA1_S1_PERIPHERAL_MAP | |
827 | #define MDMA_S1_CURR_X_COUNT MDMA1_S1_CURR_X_COUNT | |
828 | #define MDMA_S1_CURR_Y_COUNT MDMA1_S1_CURR_Y_COUNT | |
829 | ||
1394f032 BW |
830 | /* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */ |
831 | #define IMDMA_D0_CONFIG 0xFFC01808 /*IMDMA Stream 0 Destination Configuration */ | |
832 | #define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800 /*IMDMA Stream 0 Destination Next Descriptor Ptr Reg */ | |
833 | #define IMDMA_D0_START_ADDR 0xFFC01804 /*IMDMA Stream 0 Destination Start Address */ | |
834 | #define IMDMA_D0_X_COUNT 0xFFC01810 /*IMDMA Stream 0 Destination Inner-Loop Count */ | |
835 | #define IMDMA_D0_Y_COUNT 0xFFC01818 /*IMDMA Stream 0 Destination Outer-Loop Count */ | |
836 | #define IMDMA_D0_X_MODIFY 0xFFC01814 /*IMDMA Stream 0 Dest Inner-Loop Address-Increment */ | |
837 | #define IMDMA_D0_Y_MODIFY 0xFFC0181C /*IMDMA Stream 0 Dest Outer-Loop Address-Increment */ | |
838 | #define IMDMA_D0_CURR_DESC_PTR 0xFFC01820 /*IMDMA Stream 0 Destination Current Descriptor Ptr */ | |
839 | #define IMDMA_D0_CURR_ADDR 0xFFC01824 /*IMDMA Stream 0 Destination Current Address */ | |
840 | #define IMDMA_D0_CURR_X_COUNT 0xFFC01830 /*IMDMA Stream 0 Destination Current Inner-Loop Count */ | |
841 | #define IMDMA_D0_CURR_Y_COUNT 0xFFC01838 /*IMDMA Stream 0 Destination Current Outer-Loop Count */ | |
842 | #define IMDMA_D0_IRQ_STATUS 0xFFC01828 /*IMDMA Stream 0 Destination Interrupt/Status */ | |
843 | ||
844 | #define IMDMA_S0_CONFIG 0xFFC01848 /*IMDMA Stream 0 Source Configuration */ | |
845 | #define IMDMA_S0_NEXT_DESC_PTR 0xFFC01840 /*IMDMA Stream 0 Source Next Descriptor Ptr Reg */ | |
846 | #define IMDMA_S0_START_ADDR 0xFFC01844 /*IMDMA Stream 0 Source Start Address */ | |
847 | #define IMDMA_S0_X_COUNT 0xFFC01850 /*IMDMA Stream 0 Source Inner-Loop Count */ | |
848 | #define IMDMA_S0_Y_COUNT 0xFFC01858 /*IMDMA Stream 0 Source Outer-Loop Count */ | |
849 | #define IMDMA_S0_X_MODIFY 0xFFC01854 /*IMDMA Stream 0 Source Inner-Loop Address-Increment */ | |
850 | #define IMDMA_S0_Y_MODIFY 0xFFC0185C /*IMDMA Stream 0 Source Outer-Loop Address-Increment */ | |
851 | #define IMDMA_S0_CURR_DESC_PTR 0xFFC01860 /*IMDMA Stream 0 Source Current Descriptor Ptr reg */ | |
852 | #define IMDMA_S0_CURR_ADDR 0xFFC01864 /*IMDMA Stream 0 Source Current Address */ | |
853 | #define IMDMA_S0_CURR_X_COUNT 0xFFC01870 /*IMDMA Stream 0 Source Current Inner-Loop Count */ | |
854 | #define IMDMA_S0_CURR_Y_COUNT 0xFFC01878 /*IMDMA Stream 0 Source Current Outer-Loop Count */ | |
855 | #define IMDMA_S0_IRQ_STATUS 0xFFC01868 /*IMDMA Stream 0 Source Interrupt/Status */ | |
856 | ||
857 | #define IMDMA_D1_CONFIG 0xFFC01888 /*IMDMA Stream 1 Destination Configuration */ | |
858 | #define IMDMA_D1_NEXT_DESC_PTR 0xFFC01880 /*IMDMA Stream 1 Destination Next Descriptor Ptr Reg */ | |
859 | #define IMDMA_D1_START_ADDR 0xFFC01884 /*IMDMA Stream 1 Destination Start Address */ | |
860 | #define IMDMA_D1_X_COUNT 0xFFC01890 /*IMDMA Stream 1 Destination Inner-Loop Count */ | |
861 | #define IMDMA_D1_Y_COUNT 0xFFC01898 /*IMDMA Stream 1 Destination Outer-Loop Count */ | |
862 | #define IMDMA_D1_X_MODIFY 0xFFC01894 /*IMDMA Stream 1 Dest Inner-Loop Address-Increment */ | |
863 | #define IMDMA_D1_Y_MODIFY 0xFFC0189C /*IMDMA Stream 1 Dest Outer-Loop Address-Increment */ | |
864 | #define IMDMA_D1_CURR_DESC_PTR 0xFFC018A0 /*IMDMA Stream 1 Destination Current Descriptor Ptr */ | |
865 | #define IMDMA_D1_CURR_ADDR 0xFFC018A4 /*IMDMA Stream 1 Destination Current Address */ | |
866 | #define IMDMA_D1_CURR_X_COUNT 0xFFC018B0 /*IMDMA Stream 1 Destination Current Inner-Loop Count */ | |
867 | #define IMDMA_D1_CURR_Y_COUNT 0xFFC018B8 /*IMDMA Stream 1 Destination Current Outer-Loop Count */ | |
868 | #define IMDMA_D1_IRQ_STATUS 0xFFC018A8 /*IMDMA Stream 1 Destination Interrupt/Status */ | |
869 | ||
870 | #define IMDMA_S1_CONFIG 0xFFC018C8 /*IMDMA Stream 1 Source Configuration */ | |
871 | #define IMDMA_S1_NEXT_DESC_PTR 0xFFC018C0 /*IMDMA Stream 1 Source Next Descriptor Ptr Reg */ | |
872 | #define IMDMA_S1_START_ADDR 0xFFC018C4 /*IMDMA Stream 1 Source Start Address */ | |
873 | #define IMDMA_S1_X_COUNT 0xFFC018D0 /*IMDMA Stream 1 Source Inner-Loop Count */ | |
874 | #define IMDMA_S1_Y_COUNT 0xFFC018D8 /*IMDMA Stream 1 Source Outer-Loop Count */ | |
875 | #define IMDMA_S1_X_MODIFY 0xFFC018D4 /*IMDMA Stream 1 Source Inner-Loop Address-Increment */ | |
876 | #define IMDMA_S1_Y_MODIFY 0xFFC018DC /*IMDMA Stream 1 Source Outer-Loop Address-Increment */ | |
877 | #define IMDMA_S1_CURR_DESC_PTR 0xFFC018E0 /*IMDMA Stream 1 Source Current Descriptor Ptr reg */ | |
878 | #define IMDMA_S1_CURR_ADDR 0xFFC018E4 /*IMDMA Stream 1 Source Current Address */ | |
879 | #define IMDMA_S1_CURR_X_COUNT 0xFFC018F0 /*IMDMA Stream 1 Source Current Inner-Loop Count */ | |
880 | #define IMDMA_S1_CURR_Y_COUNT 0xFFC018F8 /*IMDMA Stream 1 Source Current Outer-Loop Count */ | |
881 | #define IMDMA_S1_IRQ_STATUS 0xFFC018E8 /*IMDMA Stream 1 Source Interrupt/Status */ | |
882 | ||
883 | /*********************************************************************************** */ | |
884 | /* System MMR Register Bits */ | |
885 | /******************************************************************************* */ | |
886 | ||
887 | /* ********************* PLL AND RESET MASKS ************************ */ | |
888 | ||
889 | /* PLL_CTL Masks */ | |
890 | #define PLL_CLKIN 0x00000000 /* Pass CLKIN to PLL */ | |
891 | #define PLL_CLKIN_DIV2 0x00000001 /* Pass CLKIN/2 to PLL */ | |
892 | #define PLL_OFF 0x00000002 /* Shut off PLL clocks */ | |
893 | #define STOPCK_OFF 0x00000008 /* Core clock off */ | |
894 | #define PDWN 0x00000020 /* Put the PLL in a Deep Sleep state */ | |
895 | #define BYPASS 0x00000100 /* Bypass the PLL */ | |
896 | ||
897 | /* CHIPID Masks */ | |
898 | #define CHIPID_VERSION 0xF0000000 | |
899 | #define CHIPID_FAMILY 0x0FFFF000 | |
900 | #define CHIPID_MANUFACTURE 0x00000FFE | |
901 | ||
c2f95279 MH |
902 | /* VR_CTL Masks */ |
903 | #define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */ | |
904 | #define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ | |
905 | #define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ | |
906 | #define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ | |
907 | #define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ | |
908 | ||
909 | #define GAIN 0x000C /* Voltage Level Gain */ | |
910 | #define GAIN_5 0x0000 /* GAIN = 5*/ | |
911 | #define GAIN_10 0x0004 /* GAIN = 1*/ | |
912 | #define GAIN_20 0x0008 /* GAIN = 2*/ | |
913 | #define GAIN_50 0x000C /* GAIN = 5*/ | |
914 | ||
915 | #define VLEV 0x00F0 /* Internal Voltage Level */ | |
916 | #define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ | |
917 | #define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ | |
918 | #define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ | |
919 | #define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ | |
920 | #define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ | |
921 | #define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ | |
922 | #define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ | |
923 | #define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ | |
924 | #define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ | |
925 | #define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ | |
926 | ||
927 | #define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ | |
928 | #define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */ | |
929 | ||
1394f032 BW |
930 | /* PLL_DIV Masks */ |
931 | #define SCLK_DIV(x) (x) /* SCLK = VCO / x */ | |
932 | ||
8e39df21 MH |
933 | #define CSEL 0x30 /* Core Select */ |
934 | #define SSEL 0xf /* System Select */ | |
1394f032 BW |
935 | #define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */ |
936 | #define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */ | |
937 | #define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */ | |
938 | #define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */ | |
939 | ||
940 | /* PLL_STAT Masks */ | |
941 | #define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ | |
942 | #define FULL_ON 0x0002 /* Processor In Full On Mode */ | |
943 | #define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ | |
944 | #define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ | |
945 | ||
c51b4488 GY |
946 | /* SICA_SYSCR Masks */ |
947 | #define COREB_SRAM_INIT 0x0020 | |
948 | ||
1394f032 | 949 | /* SWRST Mask */ |
fa43cd8b MF |
950 | #define SYSTEM_RESET 0x0007 /* Initiates a system software reset */ |
951 | #define DOUBLE_FAULT_A 0x0008 /* Core A Double Fault Causes Reset */ | |
952 | #define DOUBLE_FAULT_B 0x0010 /* Core B Double Fault Causes Reset */ | |
b33d5187 MF |
953 | #define SWRST_DBL_FAULT_A 0x0800 /* SWRST Core A Double Fault */ |
954 | #define SWRST_DBL_FAULT_B 0x1000 /* SWRST Core B Double Fault */ | |
fa43cd8b MF |
955 | #define SWRST_WDT_B 0x2000 /* SWRST Watchdog B */ |
956 | #define SWRST_WDT_A 0x4000 /* SWRST Watchdog A */ | |
957 | #define SWRST_OCCURRED 0x8000 /* SWRST Status */ | |
1394f032 BW |
958 | |
959 | /* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */ | |
960 | ||
961 | /* SICu_IARv Masks */ | |
962 | /* u = A or B */ | |
963 | /* v = 0 to 7 */ | |
964 | /* w = 0 or 1 */ | |
965 | ||
966 | /* Per_number = 0 to 63 */ | |
967 | /* IVG_number = 7 to 15 */ | |
968 | #define Peripheral_IVG(Per_number, IVG_number) \ | |
969 | ((IVG_number) - 7) << (((Per_number) % 8) * 4) /* Peripheral #Per_number assigned IVG #IVG_number */ | |
970 | /* Usage: r0.l = lo(Peripheral_IVG(62, 10)); */ | |
971 | /* r0.h = hi(Peripheral_IVG(62, 10)); */ | |
972 | ||
973 | /* SICx_IMASKw Masks */ | |
974 | /* masks are 32 bit wide, so two writes reguired for "64 bit" wide registers */ | |
975 | #define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ | |
976 | #define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ | |
977 | #define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */ | |
978 | #define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */ | |
979 | ||
980 | /* SIC_IWR Masks */ | |
981 | #define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ | |
982 | #define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ | |
983 | /* x = pos 0 to 31, for 32-63 use value-32 */ | |
984 | #define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ | |
985 | #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ | |
986 | ||
1394f032 BW |
987 | /* ***************************** UART CONTROLLER MASKS ********************** */ |
988 | ||
989 | /* UART_LCR Register */ | |
990 | ||
991 | #define DLAB 0x80 | |
992 | #define SB 0x40 | |
993 | #define STP 0x20 | |
994 | #define EPS 0x10 | |
995 | #define PEN 0x08 | |
996 | #define STB 0x04 | |
997 | #define WLS(x) ((x-5) & 0x03) | |
998 | ||
999 | #define DLAB_P 0x07 | |
1000 | #define SB_P 0x06 | |
1001 | #define STP_P 0x05 | |
1002 | #define EPS_P 0x04 | |
1003 | #define PEN_P 0x03 | |
1004 | #define STB_P 0x02 | |
1005 | #define WLS_P1 0x01 | |
1006 | #define WLS_P0 0x00 | |
1007 | ||
1008 | /* UART_MCR Register */ | |
1009 | #define LOOP_ENA 0x10 | |
1010 | #define LOOP_ENA_P 0x04 | |
1011 | ||
1012 | /* UART_LSR Register */ | |
1013 | #define TEMT 0x40 | |
1014 | #define THRE 0x20 | |
1015 | #define BI 0x10 | |
1016 | #define FE 0x08 | |
1017 | #define PE 0x04 | |
1018 | #define OE 0x02 | |
1019 | #define DR 0x01 | |
1020 | ||
1021 | #define TEMP_P 0x06 | |
1022 | #define THRE_P 0x05 | |
1023 | #define BI_P 0x04 | |
1024 | #define FE_P 0x03 | |
1025 | #define PE_P 0x02 | |
1026 | #define OE_P 0x01 | |
1027 | #define DR_P 0x00 | |
1028 | ||
1029 | /* UART_IER Register */ | |
1030 | #define ELSI 0x04 | |
1031 | #define ETBEI 0x02 | |
1032 | #define ERBFI 0x01 | |
1033 | ||
1034 | #define ELSI_P 0x02 | |
1035 | #define ETBEI_P 0x01 | |
1036 | #define ERBFI_P 0x00 | |
1037 | ||
1038 | /* UART_IIR Register */ | |
1039 | #define STATUS(x) ((x << 1) & 0x06) | |
1040 | #define NINT 0x01 | |
1041 | #define STATUS_P1 0x02 | |
1042 | #define STATUS_P0 0x01 | |
1043 | #define NINT_P 0x00 | |
1044 | #define IIR_TX_READY 0x02 /* UART_THR empty */ | |
1045 | #define IIR_RX_READY 0x04 /* Receive data ready */ | |
1046 | #define IIR_LINE_CHANGE 0x06 /* Receive line status */ | |
1047 | #define IIR_STATUS 0x06 | |
1048 | ||
1049 | /* UART_GCTL Register */ | |
1050 | #define FFE 0x20 | |
1051 | #define FPE 0x10 | |
1052 | #define RPOLC 0x08 | |
1053 | #define TPOLC 0x04 | |
1054 | #define IREN 0x02 | |
1055 | #define UCEN 0x01 | |
1056 | ||
1057 | #define FFE_P 0x05 | |
1058 | #define FPE_P 0x04 | |
1059 | #define RPOLC_P 0x03 | |
1060 | #define TPOLC_P 0x02 | |
1061 | #define IREN_P 0x01 | |
1062 | #define UCEN_P 0x00 | |
1063 | ||
1064 | /* ********** SERIAL PORT MASKS ********************** */ | |
1065 | ||
1066 | /* SPORTx_TCR1 Masks */ | |
1067 | #define TSPEN 0x0001 /* TX enable */ | |
1068 | #define ITCLK 0x0002 /* Internal TX Clock Select */ | |
1069 | #define TDTYPE 0x000C /* TX Data Formatting Select */ | |
1070 | #define TLSBIT 0x0010 /* TX Bit Order */ | |
1071 | #define ITFS 0x0200 /* Internal TX Frame Sync Select */ | |
1072 | #define TFSR 0x0400 /* TX Frame Sync Required Select */ | |
1073 | #define DITFS 0x0800 /* Data Independent TX Frame Sync Select */ | |
1074 | #define LTFS 0x1000 /* Low TX Frame Sync Select */ | |
1075 | #define LATFS 0x2000 /* Late TX Frame Sync Select */ | |
1076 | #define TCKFE 0x4000 /* TX Clock Falling Edge Select */ | |
1077 | ||
1078 | /* SPORTx_TCR2 Masks */ | |
1079 | #define SLEN 0x001F /*TX Word Length */ | |
1080 | #define TXSE 0x0100 /*TX Secondary Enable */ | |
1081 | #define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */ | |
1082 | #define TRFST 0x0400 /*TX Right-First Data Order */ | |
1083 | ||
1084 | /* SPORTx_RCR1 Masks */ | |
1085 | #define RSPEN 0x0001 /* RX enable */ | |
1086 | #define IRCLK 0x0002 /* Internal RX Clock Select */ | |
1087 | #define RDTYPE 0x000C /* RX Data Formatting Select */ | |
1088 | #define RULAW 0x0008 /* u-Law enable */ | |
1089 | #define RALAW 0x000C /* A-Law enable */ | |
1090 | #define RLSBIT 0x0010 /* RX Bit Order */ | |
1091 | #define IRFS 0x0200 /* Internal RX Frame Sync Select */ | |
1092 | #define RFSR 0x0400 /* RX Frame Sync Required Select */ | |
1093 | #define LRFS 0x1000 /* Low RX Frame Sync Select */ | |
1094 | #define LARFS 0x2000 /* Late RX Frame Sync Select */ | |
1095 | #define RCKFE 0x4000 /* RX Clock Falling Edge Select */ | |
1096 | ||
1097 | /* SPORTx_RCR2 Masks */ | |
1098 | #define SLEN 0x001F /*RX Word Length */ | |
1099 | #define RXSE 0x0100 /*RX Secondary Enable */ | |
1100 | #define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */ | |
1101 | #define RRFST 0x0400 /*Right-First Data Order */ | |
1102 | ||
1103 | /*SPORTx_STAT Masks */ | |
1104 | #define RXNE 0x0001 /*RX FIFO Not Empty Status */ | |
1105 | #define RUVF 0x0002 /*RX Underflow Status */ | |
1106 | #define ROVF 0x0004 /*RX Overflow Status */ | |
1107 | #define TXF 0x0008 /*TX FIFO Full Status */ | |
1108 | #define TUVF 0x0010 /*TX Underflow Status */ | |
1109 | #define TOVF 0x0020 /*TX Overflow Status */ | |
1110 | #define TXHRE 0x0040 /*TX Hold Register Empty */ | |
1111 | ||
1112 | /*SPORTx_MCMC1 Masks */ | |
1113 | #define SP_WSIZE 0x0000F000 /*Multichannel Window Size Field */ | |
1114 | #define SP_WOFF 0x000003FF /*Multichannel Window Offset Field */ | |
1115 | ||
1116 | /*SPORTx_MCMC2 Masks */ | |
1117 | #define MCCRM 0x00000003 /*Multichannel Clock Recovery Mode */ | |
1118 | #define MCDTXPE 0x00000004 /*Multichannel DMA Transmit Packing */ | |
1119 | #define MCDRXPE 0x00000008 /*Multichannel DMA Receive Packing */ | |
1120 | #define MCMEN 0x00000010 /*Multichannel Frame Mode Enable */ | |
1121 | #define FSDR 0x00000080 /*Multichannel Frame Sync to Data Relationship */ | |
1122 | #define MFD 0x0000F000 /*Multichannel Frame Delay */ | |
1123 | ||
1124 | /* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ | |
1125 | ||
1126 | /* PPI_CONTROL Masks */ | |
1127 | #define PORT_EN 0x00000001 /* PPI Port Enable */ | |
1128 | #define PORT_DIR 0x00000002 /* PPI Port Direction */ | |
1129 | #define XFR_TYPE 0x0000000C /* PPI Transfer Type */ | |
1130 | #define PORT_CFG 0x00000030 /* PPI Port Configuration */ | |
1131 | #define FLD_SEL 0x00000040 /* PPI Active Field Select */ | |
1132 | #define PACK_EN 0x00000080 /* PPI Packing Mode */ | |
1133 | #define DMA32 0x00000100 /* PPI 32-bit DMA Enable */ | |
1134 | #define SKIP_EN 0x00000200 /* PPI Skip Element Enable */ | |
1135 | #define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */ | |
1136 | #define DLENGTH 0x00003800 /* PPI Data Length */ | |
1137 | #define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */ | |
1138 | #define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */ | |
1139 | #define POL 0x0000C000 /* PPI Signal Polarities */ | |
772c258f MH |
1140 | #define POLC 0x4000 /* PPI Clock Polarity */ |
1141 | #define POLS 0x8000 /* PPI Frame Sync Polarity */ | |
1394f032 BW |
1142 | |
1143 | /* PPI_STATUS Masks */ | |
1144 | #define FLD 0x00000400 /* Field Indicator */ | |
1145 | #define FT_ERR 0x00000800 /* Frame Track Error */ | |
1146 | #define OVR 0x00001000 /* FIFO Overflow Error */ | |
1147 | #define UNDR 0x00002000 /* FIFO Underrun Error */ | |
1148 | #define ERR_DET 0x00004000 /* Error Detected Indicator */ | |
1149 | #define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */ | |
1150 | ||
1151 | /* ********** DMA CONTROLLER MASKS *********************8 */ | |
1152 | ||
1153 | /* DMAx_CONFIG, MDMA_yy_CONFIG, IMDMA_yy_CONFIG Masks */ | |
1154 | #define DMAEN 0x00000001 /* Channel Enable */ | |
1155 | #define WNR 0x00000002 /* Channel Direction (W/R*) */ | |
1156 | #define WDSIZE_8 0x00000000 /* Word Size 8 bits */ | |
1157 | #define WDSIZE_16 0x00000004 /* Word Size 16 bits */ | |
1158 | #define WDSIZE_32 0x00000008 /* Word Size 32 bits */ | |
1159 | #define DMA2D 0x00000010 /* 2D/1D* Mode */ | |
1160 | #define RESTART 0x00000020 /* Restart */ | |
1161 | #define DI_SEL 0x00000040 /* Data Interrupt Select */ | |
1162 | #define DI_EN 0x00000080 /* Data Interrupt Enable */ | |
1163 | #define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ | |
1164 | #define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ | |
1165 | #define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ | |
1166 | #define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ | |
1167 | #define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ | |
1168 | #define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ | |
1169 | #define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ | |
1170 | #define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ | |
1171 | #define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ | |
1172 | #define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ | |
1173 | #define NDSIZE 0x00000900 /* Next Descriptor Size */ | |
1174 | #define DMAFLOW 0x00007000 /* Flow Control */ | |
1175 | #define DMAFLOW_STOP 0x0000 /* Stop Mode */ | |
1176 | #define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ | |
1177 | #define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ | |
1178 | #define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ | |
1179 | #define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ | |
1180 | ||
1181 | #define DMAEN_P 0 /* Channel Enable */ | |
1182 | #define WNR_P 1 /* Channel Direction (W/R*) */ | |
1183 | #define DMA2D_P 4 /* 2D/1D* Mode */ | |
1184 | #define RESTART_P 5 /* Restart */ | |
1185 | #define DI_SEL_P 6 /* Data Interrupt Select */ | |
1186 | #define DI_EN_P 7 /* Data Interrupt Enable */ | |
1187 | ||
1188 | /* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS, IMDMA_yy_IRQ_STATUS Masks */ | |
1189 | ||
1190 | #define DMA_DONE 0x00000001 /* DMA Done Indicator */ | |
1191 | #define DMA_ERR 0x00000002 /* DMA Error Indicator */ | |
1192 | #define DFETCH 0x00000004 /* Descriptor Fetch Indicator */ | |
1193 | #define DMA_RUN 0x00000008 /* DMA Running Indicator */ | |
1194 | ||
1195 | #define DMA_DONE_P 0 /* DMA Done Indicator */ | |
1196 | #define DMA_ERR_P 1 /* DMA Error Indicator */ | |
1197 | #define DFETCH_P 2 /* Descriptor Fetch Indicator */ | |
1198 | #define DMA_RUN_P 3 /* DMA Running Indicator */ | |
1199 | ||
1200 | /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks */ | |
1201 | ||
1202 | #define CTYPE 0x00000040 /* DMA Channel Type Indicator */ | |
1203 | #define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */ | |
1204 | #define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */ | |
1205 | #define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */ | |
1206 | #define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */ | |
1207 | #define PCAPWR 0x00000400 /* DMA Write Operation Indicator */ | |
1208 | #define PCAPRD 0x00000800 /* DMA Read Operation Indicator */ | |
1209 | #define PMAP 0x00007000 /* DMA Peripheral Map Field */ | |
1210 | ||
1211 | /* ************* GENERAL PURPOSE TIMER MASKS ******************** */ | |
1212 | ||
1213 | /* PWM Timer bit definitions */ | |
1214 | ||
1215 | /* TIMER_ENABLE Register */ | |
1216 | #define TIMEN0 0x0001 | |
1217 | #define TIMEN1 0x0002 | |
1218 | #define TIMEN2 0x0004 | |
1219 | #define TIMEN3 0x0008 | |
1220 | #define TIMEN4 0x0010 | |
1221 | #define TIMEN5 0x0020 | |
1222 | #define TIMEN6 0x0040 | |
1223 | #define TIMEN7 0x0080 | |
1224 | #define TIMEN8 0x0001 | |
1225 | #define TIMEN9 0x0002 | |
1226 | #define TIMEN10 0x0004 | |
1227 | #define TIMEN11 0x0008 | |
1228 | ||
1229 | #define TIMEN0_P 0x00 | |
1230 | #define TIMEN1_P 0x01 | |
1231 | #define TIMEN2_P 0x02 | |
1232 | #define TIMEN3_P 0x03 | |
1233 | #define TIMEN4_P 0x04 | |
1234 | #define TIMEN5_P 0x05 | |
1235 | #define TIMEN6_P 0x06 | |
1236 | #define TIMEN7_P 0x07 | |
1237 | #define TIMEN8_P 0x00 | |
1238 | #define TIMEN9_P 0x01 | |
1239 | #define TIMEN10_P 0x02 | |
1240 | #define TIMEN11_P 0x03 | |
1241 | ||
1242 | /* TIMER_DISABLE Register */ | |
1243 | #define TIMDIS0 0x0001 | |
1244 | #define TIMDIS1 0x0002 | |
1245 | #define TIMDIS2 0x0004 | |
1246 | #define TIMDIS3 0x0008 | |
1247 | #define TIMDIS4 0x0010 | |
1248 | #define TIMDIS5 0x0020 | |
1249 | #define TIMDIS6 0x0040 | |
1250 | #define TIMDIS7 0x0080 | |
1251 | #define TIMDIS8 0x0001 | |
1252 | #define TIMDIS9 0x0002 | |
1253 | #define TIMDIS10 0x0004 | |
1254 | #define TIMDIS11 0x0008 | |
1255 | ||
1256 | #define TIMDIS0_P 0x00 | |
1257 | #define TIMDIS1_P 0x01 | |
1258 | #define TIMDIS2_P 0x02 | |
1259 | #define TIMDIS3_P 0x03 | |
1260 | #define TIMDIS4_P 0x04 | |
1261 | #define TIMDIS5_P 0x05 | |
1262 | #define TIMDIS6_P 0x06 | |
1263 | #define TIMDIS7_P 0x07 | |
1264 | #define TIMDIS8_P 0x00 | |
1265 | #define TIMDIS9_P 0x01 | |
1266 | #define TIMDIS10_P 0x02 | |
1267 | #define TIMDIS11_P 0x03 | |
1268 | ||
1269 | /* TIMER_STATUS Register */ | |
1270 | #define TIMIL0 0x00000001 | |
1271 | #define TIMIL1 0x00000002 | |
1272 | #define TIMIL2 0x00000004 | |
1273 | #define TIMIL3 0x00000008 | |
1274 | #define TIMIL4 0x00010000 | |
1275 | #define TIMIL5 0x00020000 | |
1276 | #define TIMIL6 0x00040000 | |
1277 | #define TIMIL7 0x00080000 | |
1278 | #define TIMIL8 0x0001 | |
1279 | #define TIMIL9 0x0002 | |
1280 | #define TIMIL10 0x0004 | |
1281 | #define TIMIL11 0x0008 | |
19381f02 BW |
1282 | #define TOVF_ERR0 0x00000010 |
1283 | #define TOVF_ERR1 0x00000020 | |
1284 | #define TOVF_ERR2 0x00000040 | |
1285 | #define TOVF_ERR3 0x00000080 | |
1286 | #define TOVF_ERR4 0x00100000 | |
1287 | #define TOVF_ERR5 0x00200000 | |
1288 | #define TOVF_ERR6 0x00400000 | |
1289 | #define TOVF_ERR7 0x00800000 | |
1290 | #define TOVF_ERR8 0x0010 | |
1291 | #define TOVF_ERR9 0x0020 | |
1292 | #define TOVF_ERR10 0x0040 | |
1293 | #define TOVF_ERR11 0x0080 | |
1394f032 BW |
1294 | #define TRUN0 0x00001000 |
1295 | #define TRUN1 0x00002000 | |
1296 | #define TRUN2 0x00004000 | |
1297 | #define TRUN3 0x00008000 | |
1298 | #define TRUN4 0x10000000 | |
1299 | #define TRUN5 0x20000000 | |
1300 | #define TRUN6 0x40000000 | |
1301 | #define TRUN7 0x80000000 | |
1302 | #define TRUN8 0x1000 | |
1303 | #define TRUN9 0x2000 | |
1304 | #define TRUN10 0x4000 | |
1305 | #define TRUN11 0x8000 | |
1306 | ||
1307 | #define TIMIL0_P 0x00 | |
1308 | #define TIMIL1_P 0x01 | |
1309 | #define TIMIL2_P 0x02 | |
1310 | #define TIMIL3_P 0x03 | |
1311 | #define TIMIL4_P 0x10 | |
1312 | #define TIMIL5_P 0x11 | |
1313 | #define TIMIL6_P 0x12 | |
1314 | #define TIMIL7_P 0x13 | |
1315 | #define TIMIL8_P 0x00 | |
1316 | #define TIMIL9_P 0x01 | |
1317 | #define TIMIL10_P 0x02 | |
1318 | #define TIMIL11_P 0x03 | |
19381f02 BW |
1319 | #define TOVF_ERR0_P 0x04 |
1320 | #define TOVF_ERR1_P 0x05 | |
1321 | #define TOVF_ERR2_P 0x06 | |
1322 | #define TOVF_ERR3_P 0x07 | |
1323 | #define TOVF_ERR4_P 0x14 | |
1324 | #define TOVF_ERR5_P 0x15 | |
1325 | #define TOVF_ERR6_P 0x16 | |
1326 | #define TOVF_ERR7_P 0x17 | |
1327 | #define TOVF_ERR8_P 0x04 | |
1328 | #define TOVF_ERR9_P 0x05 | |
1329 | #define TOVF_ERR10_P 0x06 | |
1330 | #define TOVF_ERR11_P 0x07 | |
1394f032 BW |
1331 | #define TRUN0_P 0x0C |
1332 | #define TRUN1_P 0x0D | |
1333 | #define TRUN2_P 0x0E | |
1334 | #define TRUN3_P 0x0F | |
1335 | #define TRUN4_P 0x1C | |
1336 | #define TRUN5_P 0x1D | |
1337 | #define TRUN6_P 0x1E | |
1338 | #define TRUN7_P 0x1F | |
1339 | #define TRUN8_P 0x0C | |
1340 | #define TRUN9_P 0x0D | |
1341 | #define TRUN10_P 0x0E | |
1342 | #define TRUN11_P 0x0F | |
1343 | ||
19381f02 BW |
1344 | /* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ |
1345 | #define TOVL_ERR0 TOVF_ERR0 | |
1346 | #define TOVL_ERR1 TOVF_ERR1 | |
1347 | #define TOVL_ERR2 TOVF_ERR2 | |
1348 | #define TOVL_ERR3 TOVF_ERR3 | |
1349 | #define TOVL_ERR4 TOVF_ERR4 | |
1350 | #define TOVL_ERR5 TOVF_ERR5 | |
1351 | #define TOVL_ERR6 TOVF_ERR6 | |
1352 | #define TOVL_ERR7 TOVF_ERR7 | |
1353 | #define TOVL_ERR8 TOVF_ERR8 | |
1354 | #define TOVL_ERR9 TOVF_ERR9 | |
1355 | #define TOVL_ERR10 TOVF_ERR10 | |
1356 | #define TOVL_ERR11 TOVF_ERR11 | |
1357 | #define TOVL_ERR0_P TOVF_ERR0_P | |
1358 | #define TOVL_ERR1_P TOVF_ERR1_P | |
1359 | #define TOVL_ERR2_P TOVF_ERR2_P | |
1360 | #define TOVL_ERR3_P TOVF_ERR3_P | |
1361 | #define TOVL_ERR4_P TOVF_ERR4_P | |
1362 | #define TOVL_ERR5_P TOVF_ERR5_P | |
1363 | #define TOVL_ERR6_P TOVF_ERR6_P | |
1364 | #define TOVL_ERR7_P TOVF_ERR7_P | |
1365 | #define TOVL_ERR8_P TOVF_ERR8_P | |
1366 | #define TOVL_ERR9_P TOVF_ERR9_P | |
1367 | #define TOVL_ERR10_P TOVF_ERR10_P | |
1368 | #define TOVL_ERR11_P TOVF_ERR11_P | |
1369 | ||
1394f032 BW |
1370 | /* TIMERx_CONFIG Registers */ |
1371 | #define PWM_OUT 0x0001 | |
1372 | #define WDTH_CAP 0x0002 | |
1373 | #define EXT_CLK 0x0003 | |
1374 | #define PULSE_HI 0x0004 | |
1375 | #define PERIOD_CNT 0x0008 | |
1376 | #define IRQ_ENA 0x0010 | |
1377 | #define TIN_SEL 0x0020 | |
1378 | #define OUT_DIS 0x0040 | |
1379 | #define CLK_SEL 0x0080 | |
1380 | #define TOGGLE_HI 0x0100 | |
1381 | #define EMU_RUN 0x0200 | |
1382 | #define ERR_TYP(x) ((x & 0x03) << 14) | |
1383 | ||
1384 | #define TMODE_P0 0x00 | |
1385 | #define TMODE_P1 0x01 | |
1386 | #define PULSE_HI_P 0x02 | |
1387 | #define PERIOD_CNT_P 0x03 | |
1388 | #define IRQ_ENA_P 0x04 | |
1389 | #define TIN_SEL_P 0x05 | |
1390 | #define OUT_DIS_P 0x06 | |
1391 | #define CLK_SEL_P 0x07 | |
1392 | #define TOGGLE_HI_P 0x08 | |
1393 | #define EMU_RUN_P 0x09 | |
1394 | #define ERR_TYP_P0 0x0E | |
1395 | #define ERR_TYP_P1 0x0F | |
1396 | ||
1397 | /*/ ****************** PROGRAMMABLE FLAG MASKS ********************* */ | |
1398 | ||
1399 | /* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */ | |
1400 | #define PF0 0x0001 | |
1401 | #define PF1 0x0002 | |
1402 | #define PF2 0x0004 | |
1403 | #define PF3 0x0008 | |
1404 | #define PF4 0x0010 | |
1405 | #define PF5 0x0020 | |
1406 | #define PF6 0x0040 | |
1407 | #define PF7 0x0080 | |
1408 | #define PF8 0x0100 | |
1409 | #define PF9 0x0200 | |
1410 | #define PF10 0x0400 | |
1411 | #define PF11 0x0800 | |
1412 | #define PF12 0x1000 | |
1413 | #define PF13 0x2000 | |
1414 | #define PF14 0x4000 | |
1415 | #define PF15 0x8000 | |
1416 | ||
1417 | /* General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS */ | |
1418 | #define PF0_P 0 | |
1419 | #define PF1_P 1 | |
1420 | #define PF2_P 2 | |
1421 | #define PF3_P 3 | |
1422 | #define PF4_P 4 | |
1423 | #define PF5_P 5 | |
1424 | #define PF6_P 6 | |
1425 | #define PF7_P 7 | |
1426 | #define PF8_P 8 | |
1427 | #define PF9_P 9 | |
1428 | #define PF10_P 10 | |
1429 | #define PF11_P 11 | |
1430 | #define PF12_P 12 | |
1431 | #define PF13_P 13 | |
1432 | #define PF14_P 14 | |
1433 | #define PF15_P 15 | |
1434 | ||
1435 | /* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */ | |
1436 | ||
1437 | /* SPI_CTL Masks */ | |
1438 | #define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */ | |
1439 | #define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */ | |
1440 | #define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */ | |
1441 | #define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */ | |
1442 | #define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */ | |
1443 | #define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */ | |
1444 | #define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */ | |
1445 | #define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */ | |
1446 | #define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */ | |
1447 | #define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */ | |
1448 | #define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */ | |
1449 | #define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */ | |
1450 | ||
1451 | /* SPI_FLG Masks */ | |
1452 | #define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ | |
1453 | #define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ | |
1454 | #define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ | |
1455 | #define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ | |
1456 | #define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ | |
1457 | #define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ | |
1458 | #define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ | |
1459 | #define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ | |
1460 | #define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ | |
1461 | #define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ | |
1462 | #define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ | |
1463 | #define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ | |
1464 | #define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ | |
1465 | #define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ | |
1466 | ||
1467 | /* SPI_FLG Bit Positions */ | |
1468 | #define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ | |
1469 | #define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ | |
1470 | #define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ | |
1471 | #define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ | |
1472 | #define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ | |
1473 | #define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ | |
1474 | #define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ | |
1475 | #define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ | |
1476 | #define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ | |
1477 | #define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ | |
1478 | #define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ | |
1479 | #define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ | |
1480 | #define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ | |
1481 | #define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ | |
1482 | ||
1483 | /* SPI_STAT Masks */ | |
1484 | #define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */ | |
1485 | #define MODF 0x00000002 /* Set (=1) in a master device when some other device tries to become master */ | |
1486 | #define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */ | |
1487 | #define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */ | |
1488 | #define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */ | |
1489 | #define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */ | |
1490 | #define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */ | |
1491 | ||
1492 | /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ | |
1493 | ||
1494 | /* AMGCTL Masks */ | |
1495 | #define AMCKEN 0x0001 /* Enable CLKOUT */ | |
1496 | #define AMBEN_B0 0x0002 /* Enable Asynchronous Memory Bank 0 only */ | |
1497 | #define AMBEN_B0_B1 0x0004 /* Enable Asynchronous Memory Banks 0 & 1 only */ | |
1498 | #define AMBEN_B0_B1_B2 0x0006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */ | |
1499 | #define AMBEN_ALL 0x0008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */ | |
1500 | #define B0_PEN 0x0010 /* Enable 16-bit packing Bank 0 */ | |
1501 | #define B1_PEN 0x0020 /* Enable 16-bit packing Bank 1 */ | |
1502 | #define B2_PEN 0x0040 /* Enable 16-bit packing Bank 2 */ | |
1503 | #define B3_PEN 0x0080 /* Enable 16-bit packing Bank 3 */ | |
1504 | ||
1505 | /* AMGCTL Bit Positions */ | |
1506 | #define AMCKEN_P 0x00000000 /* Enable CLKOUT */ | |
1507 | #define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */ | |
1508 | #define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */ | |
1509 | #define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */ | |
1510 | #define B0_PEN_P 0x004 /* Enable 16-bit packing Bank 0 */ | |
1511 | #define B1_PEN_P 0x005 /* Enable 16-bit packing Bank 1 */ | |
1512 | #define B2_PEN_P 0x006 /* Enable 16-bit packing Bank 2 */ | |
1513 | #define B3_PEN_P 0x007 /* Enable 16-bit packing Bank 3 */ | |
1514 | ||
1515 | /* AMBCTL0 Masks */ | |
1516 | #define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */ | |
1517 | #define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */ | |
1518 | #define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */ | |
1519 | #define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */ | |
1520 | #define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */ | |
1521 | #define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */ | |
1522 | #define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */ | |
1523 | #define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */ | |
1524 | #define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */ | |
1525 | #define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */ | |
1526 | #define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */ | |
1527 | #define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */ | |
1528 | #define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */ | |
1529 | #define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */ | |
1530 | #define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */ | |
1531 | #define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */ | |
1532 | #define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */ | |
1533 | #define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */ | |
1534 | #define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */ | |
1535 | #define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */ | |
1536 | #define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */ | |
1537 | #define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */ | |
1538 | #define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */ | |
1539 | #define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */ | |
1540 | #define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */ | |
1541 | #define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */ | |
1542 | #define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */ | |
1543 | #define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */ | |
1544 | #define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */ | |
1545 | #define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */ | |
1546 | #define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */ | |
1547 | #define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */ | |
1548 | #define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */ | |
1549 | #define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */ | |
1550 | #define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */ | |
1551 | #define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */ | |
1552 | #define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */ | |
1553 | #define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */ | |
1554 | #define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */ | |
1555 | #define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */ | |
1556 | #define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */ | |
1557 | #define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */ | |
1558 | #define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */ | |
1559 | #define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */ | |
1560 | #define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */ | |
1561 | #define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */ | |
1562 | #define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */ | |
1563 | #define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */ | |
1564 | #define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */ | |
1565 | #define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */ | |
1566 | #define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ | |
1567 | #define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ | |
1568 | #define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ | |
1569 | #define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ | |
1570 | #define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ | |
1571 | #define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ | |
1572 | #define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ | |
1573 | #define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ | |
1574 | #define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */ | |
1575 | #define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */ | |
1576 | #define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */ | |
1577 | #define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */ | |
1578 | #define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */ | |
1579 | #define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */ | |
1580 | #define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */ | |
1581 | #define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */ | |
1582 | #define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */ | |
1583 | #define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */ | |
1584 | #define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */ | |
1585 | #define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */ | |
1586 | #define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */ | |
1587 | #define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */ | |
1588 | #define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */ | |
1589 | #define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */ | |
1590 | #define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */ | |
1591 | #define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */ | |
1592 | #define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */ | |
1593 | #define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */ | |
1594 | #define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */ | |
1595 | #define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */ | |
1596 | #define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */ | |
1597 | #define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */ | |
1598 | #define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */ | |
1599 | #define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */ | |
1600 | #define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */ | |
1601 | #define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */ | |
1602 | #define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */ | |
1603 | #define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */ | |
1604 | ||
1605 | /* AMBCTL1 Masks */ | |
1606 | #define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */ | |
1607 | #define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */ | |
1608 | #define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */ | |
1609 | #define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */ | |
1610 | #define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */ | |
1611 | #define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */ | |
1612 | #define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ | |
1613 | #define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ | |
1614 | #define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ | |
1615 | #define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ | |
1616 | #define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ | |
1617 | #define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ | |
1618 | #define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ | |
1619 | #define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ | |
1620 | #define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */ | |
1621 | #define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */ | |
1622 | #define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */ | |
1623 | #define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */ | |
1624 | #define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */ | |
1625 | #define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */ | |
1626 | #define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */ | |
1627 | #define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */ | |
1628 | #define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */ | |
1629 | #define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */ | |
1630 | #define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */ | |
1631 | #define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */ | |
1632 | #define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */ | |
1633 | #define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */ | |
1634 | #define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */ | |
1635 | #define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */ | |
1636 | #define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */ | |
1637 | #define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */ | |
1638 | #define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */ | |
1639 | #define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */ | |
1640 | #define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */ | |
1641 | #define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */ | |
1642 | #define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */ | |
1643 | #define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */ | |
1644 | #define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */ | |
1645 | #define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */ | |
1646 | #define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */ | |
1647 | #define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */ | |
1648 | #define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */ | |
1649 | #define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */ | |
1650 | #define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */ | |
1651 | #define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */ | |
1652 | #define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */ | |
1653 | #define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */ | |
1654 | #define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */ | |
1655 | #define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */ | |
1656 | #define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ | |
1657 | #define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ | |
1658 | #define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ | |
1659 | #define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ | |
1660 | #define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ | |
1661 | #define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ | |
1662 | #define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ | |
1663 | #define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ | |
1664 | #define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */ | |
1665 | #define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */ | |
1666 | #define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */ | |
1667 | #define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */ | |
1668 | #define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */ | |
1669 | #define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */ | |
1670 | #define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */ | |
1671 | #define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */ | |
1672 | #define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */ | |
1673 | #define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */ | |
1674 | #define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */ | |
1675 | #define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */ | |
1676 | #define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */ | |
1677 | #define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */ | |
1678 | #define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */ | |
1679 | #define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */ | |
1680 | #define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */ | |
1681 | #define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */ | |
1682 | #define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */ | |
1683 | #define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */ | |
1684 | #define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */ | |
1685 | #define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */ | |
1686 | #define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */ | |
1687 | #define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */ | |
1688 | #define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */ | |
1689 | #define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */ | |
1690 | #define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */ | |
1691 | #define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */ | |
1692 | #define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */ | |
1693 | #define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */ | |
1694 | ||
1695 | /* ********************** SDRAM CONTROLLER MASKS *************************** */ | |
1696 | ||
1697 | /* EBIU_SDGCTL Masks */ | |
1698 | #define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */ | |
1699 | #define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */ | |
1700 | #define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */ | |
1701 | #define PFE 0x00000010 /* Enable SDRAM prefetch */ | |
1702 | #define PFP 0x00000020 /* Prefetch has priority over AMC requests */ | |
1703 | #define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ | |
1704 | #define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ | |
1705 | #define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ | |
1706 | #define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ | |
1707 | #define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ | |
1708 | #define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ | |
1709 | #define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ | |
1710 | #define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ | |
1711 | #define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ | |
1712 | #define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ | |
1713 | #define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ | |
1714 | #define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ | |
1715 | #define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ | |
1716 | #define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ | |
1717 | #define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ | |
1718 | #define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ | |
1719 | #define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ | |
1720 | #define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ | |
1721 | #define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ | |
1722 | #define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ | |
1723 | #define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ | |
1724 | #define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ | |
1725 | #define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ | |
1726 | #define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ | |
1727 | #define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ | |
1728 | #define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ | |
1729 | #define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ | |
1730 | #define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ | |
1731 | #define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ | |
1732 | #define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ | |
1733 | #define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ | |
1734 | #define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ | |
1735 | #define PUPSD 0x00200000 /*Power-up start delay */ | |
1736 | #define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */ | |
1737 | #define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */ | |
1738 | #define SRFS 0x01000000 /* Start SDRAM self-refresh mode */ | |
1739 | #define EBUFE 0x02000000 /* Enable external buffering timing */ | |
1740 | #define FBBRW 0x04000000 /* Fast back-to-back read write enable */ | |
1741 | #define EMREN 0x10000000 /* Extended mode register enable */ | |
1742 | #define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */ | |
1743 | #define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */ | |
1744 | ||
1745 | /* EBIU_SDBCTL Masks */ | |
1746 | #define EB0_E 0x00000001 /* Enable SDRAM external bank 0 */ | |
1747 | #define EB0_SZ_16 0x00000000 /* SDRAM external bank size = 16MB */ | |
1748 | #define EB0_SZ_32 0x00000002 /* SDRAM external bank size = 32MB */ | |
1749 | #define EB0_SZ_64 0x00000004 /* SDRAM external bank size = 64MB */ | |
1750 | #define EB0_SZ_128 0x00000006 /* SDRAM external bank size = 128MB */ | |
1751 | #define EB0_CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ | |
1752 | #define EB0_CAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */ | |
1753 | #define EB0_CAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */ | |
1754 | #define EB0_CAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */ | |
1755 | ||
1756 | #define EB1_E 0x00000100 /* Enable SDRAM external bank 1 */ | |
1757 | #define EB1__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */ | |
1758 | #define EB1__SZ_32 0x00000200 /* SDRAM external bank size = 32MB */ | |
1759 | #define EB1__SZ_64 0x00000400 /* SDRAM external bank size = 64MB */ | |
1760 | #define EB1__SZ_128 0x00000600 /* SDRAM external bank size = 128MB */ | |
1761 | #define EB1__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ | |
1762 | #define EB1__CAW_9 0x00001000 /* SDRAM external bank column address width = 9 bits */ | |
1763 | #define EB1__CAW_10 0x00002000 /* SDRAM external bank column address width = 9 bits */ | |
1764 | #define EB1__CAW_11 0x00003000 /* SDRAM external bank column address width = 9 bits */ | |
1765 | ||
1766 | #define EB2__E 0x00010000 /* Enable SDRAM external bank 2 */ | |
1767 | #define EB2__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */ | |
1768 | #define EB2__SZ_32 0x00020000 /* SDRAM external bank size = 32MB */ | |
1769 | #define EB2__SZ_64 0x00040000 /* SDRAM external bank size = 64MB */ | |
1770 | #define EB2__SZ_128 0x00060000 /* SDRAM external bank size = 128MB */ | |
1771 | #define EB2__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ | |
1772 | #define EB2__CAW_9 0x00100000 /* SDRAM external bank column address width = 9 bits */ | |
1773 | #define EB2__CAW_10 0x00200000 /* SDRAM external bank column address width = 9 bits */ | |
1774 | #define EB2__CAW_11 0x00300000 /* SDRAM external bank column address width = 9 bits */ | |
1775 | ||
1776 | #define EB3__E 0x01000000 /* Enable SDRAM external bank 3 */ | |
1777 | #define EB3__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */ | |
1778 | #define EB3__SZ_32 0x02000000 /* SDRAM external bank size = 32MB */ | |
1779 | #define EB3__SZ_64 0x04000000 /* SDRAM external bank size = 64MB */ | |
1780 | #define EB3__SZ_128 0x06000000 /* SDRAM external bank size = 128MB */ | |
1781 | #define EB3__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ | |
1782 | #define EB3__CAW_9 0x10000000 /* SDRAM external bank column address width = 9 bits */ | |
1783 | #define EB3__CAW_10 0x20000000 /* SDRAM external bank column address width = 9 bits */ | |
1784 | #define EB3__CAW_11 0x30000000 /* SDRAM external bank column address width = 9 bits */ | |
1785 | ||
1786 | /* EBIU_SDSTAT Masks */ | |
1787 | #define SDCI 0x00000001 /* SDRAM controller is idle */ | |
1788 | #define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */ | |
1789 | #define SDPUA 0x00000004 /* SDRAM power up active */ | |
1790 | #define SDRS 0x00000008 /* SDRAM is in reset state */ | |
1791 | #define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */ | |
1792 | #define BGSTAT 0x00000020 /* Bus granted */ | |
1793 | ||
1394f032 | 1794 | #endif /* _DEF_BF561_H */ |