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Blackfin: update anomaly lists
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / blackfin / mach-bf537 / boards / stamp.c
CommitLineData
1394f032
BW		 1/*
2 * File: arch/blackfin/mach-bf537/boards/stamp.c
3 * Based on: arch/blackfin/mach-bf533/boards/ezkit.c
4 * Author: Aidan Williams <aidan@nicta.com.au>
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2005 National ICT Australia (NICTA)
11 * Copyright 2004-2006 Analog Devices Inc.
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see the file COPYING, or write
27 * to the Free Software Foundation, Inc.,
28 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 */
30
31#include <linux/device.h>
fc68911e 32#include <linux/kernel.h>
1394f032
BW		 33#include <linux/platform_device.h>
34#include <linux/mtd/mtd.h>
fc68911e 35#include <linux/mtd/nand.h>
1394f032 36#include <linux/mtd/partitions.h>
fc68911e 37#include <linux/mtd/plat-ram.h>
de8c43f2 38#include <linux/mtd/physmap.h>
1394f032
BW		 39#include <linux/spi/spi.h>
40#include <linux/spi/flash.h>
41#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
f02bcec5 42#include <linux/usb/isp1362.h>
1394f032 43#endif
0a87e3e9 44#include <linux/ata_platform.h>
1394f032
BW		 45#include <linux/irq.h>
46#include <linux/interrupt.h>
81d9c7f2 47#include <linux/i2c.h>
27f5d75a 48#include <linux/usb/sl811.h>
f79ea4cb 49#include <linux/spi/mmc_spi.h>
c6c4d7bb 50#include <asm/dma.h>
1f83b8f1 51#include <asm/bfin5xx_spi.h>
c6c4d7bb 52#include <asm/reboot.h>
5d448dd5 53#include <asm/portmux.h>
14b03204 54#include <asm/dpmc.h>
1394f032
BW		 55
56/*
57 * Name the Board for the /proc/cpuinfo
58 */
fe85cad2 59const char bfin_board_name[] = "ADI BF537-STAMP";
1394f032
BW		 60
61/*
62 * Driver needs to know address, irq and flag pin.
63 */
64
1394f032 65#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
3f375690
MH		 66#include <linux/usb/isp1760.h>
67static struct resource bfin_isp1760_resources[] = {
1394f032 68 [0] = {
3f375690
MH		 69 .start = 0x203C0000,
70 .end = 0x203C0000 + 0x000fffff,
1394f032
BW		 71 .flags = IORESOURCE_MEM,
72 },
73 [1] = {
3f375690
MH		 74 .start = IRQ_PF7,
75 .end = IRQ_PF7,
6a6be3d1 76 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
1394f032
BW		 77 },
78};
79
3f375690
MH		 80static struct isp1760_platform_data isp1760_priv = {
81 .is_isp1761 = 0,
3f375690
MH		 82 .bus_width_16 = 1,
83 .port1_otg = 0,
84 .analog_oc = 0,
85 .dack_polarity_high = 0,
86 .dreq_polarity_high = 0,
1394f032
BW		 87};
88
3f375690
MH		 89static struct platform_device bfin_isp1760_device = {
90 .name = "isp1760-hcd",
91 .id = 0,
92 .dev = {
93 .platform_data = &isp1760_priv,
94 },
95 .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
96 .resource = bfin_isp1760_resources,
1394f032 97};
1394f032
BW		 98#endif
99
2463ef22
MH		 100#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
101#include <linux/input.h>
102#include <linux/gpio_keys.h>
103
104static struct gpio_keys_button bfin_gpio_keys_table[] = {
105 {BTN_0, GPIO_PF2, 1, "gpio-keys: BTN0"},
106 {BTN_1, GPIO_PF3, 1, "gpio-keys: BTN1"},
107 {BTN_2, GPIO_PF4, 1, "gpio-keys: BTN2"},
108 {BTN_3, GPIO_PF5, 1, "gpio-keys: BTN3"},
109};
110
111static struct gpio_keys_platform_data bfin_gpio_keys_data = {
112 .buttons = bfin_gpio_keys_table,
113 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
114};
115
116static struct platform_device bfin_device_gpiokeys = {
117 .name = "gpio-keys",
118 .dev = {
119 .platform_data = &bfin_gpio_keys_data,
120 },
121};
122#endif
123
cad2ab65
MF		 124static struct resource bfin_gpios_resources = {
125 .start = 0,
126 .end = MAX_BLACKFIN_GPIOS - 1,
127 .flags = IORESOURCE_IRQ,
128};
129
130static struct platform_device bfin_gpios_device = {
131 .name = "simple-gpio",
132 .id = -1,
133 .num_resources = 1,
134 .resource = &bfin_gpios_resources,
135};
136
1394f032
BW		 137#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
138static struct resource bfin_pcmcia_cf_resources[] = {
139 {
140 .start = 0x20310000, /* IO PORT */
141 .end = 0x20312000,
142 .flags = IORESOURCE_MEM,
1f83b8f1 143 }, {
d2d50aa9 144 .start = 0x20311000, /* Attribute Memory */
1394f032
BW		 145 .end = 0x20311FFF,
146 .flags = IORESOURCE_MEM,
1f83b8f1 147 }, {
1394f032
BW		 148 .start = IRQ_PF4,
149 .end = IRQ_PF4,
150 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
1f83b8f1 151 }, {
1394f032
BW		 152 .start = 6, /* Card Detect PF6 */
153 .end = 6,
154 .flags = IORESOURCE_IRQ,
155 },
156};
157
158static struct platform_device bfin_pcmcia_cf_device = {
159 .name = "bfin_cf_pcmcia",
160 .id = -1,
161 .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
162 .resource = bfin_pcmcia_cf_resources,
163};
164#endif
165
166#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
167static struct platform_device rtc_device = {
168 .name = "rtc-bfin",
169 .id = -1,
170};
171#endif
172
173#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
61f09b5a
MH		 174#include <linux/smc91x.h>
175
176static struct smc91x_platdata smc91x_info = {
177 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
178 .leda = RPC_LED_100_10,
179 .ledb = RPC_LED_TX_RX,
180};
181
1394f032
BW		 182static struct resource smc91x_resources[] = {
183 {
184 .name = "smc91x-regs",
185 .start = 0x20300300,
186 .end = 0x20300300 + 16,
187 .flags = IORESOURCE_MEM,
1f83b8f1 188 }, {
1394f032
BW		 189
190 .start = IRQ_PF7,
191 .end = IRQ_PF7,
192 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
193 },
194};
195static struct platform_device smc91x_device = {
196 .name = "smc91x",
197 .id = 0,
198 .num_resources = ARRAY_SIZE(smc91x_resources),
199 .resource = smc91x_resources,
61f09b5a
MH		 200 .dev = {
201 .platform_data = &smc91x_info,
202 },
1394f032
BW		 203};
204#endif
205
f40d24d9
AL		 206#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
207static struct resource dm9000_resources[] = {
208 [0] = {
209 .start = 0x203FB800,
b3dec4a4 210 .end = 0x203FB800 + 1,
f40d24d9
AL		 211 .flags = IORESOURCE_MEM,
212 },
213 [1] = {
b3dec4a4
BS		 214 .start = 0x203FB804,
215 .end = 0x203FB804 + 1,
216 .flags = IORESOURCE_MEM,
217 },
218 [2] = {
f40d24d9
AL		 219 .start = IRQ_PF9,
220 .end = IRQ_PF9,
221 .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
222 },
223};
224
225static struct platform_device dm9000_device = {
226 .name = "dm9000",
227 .id = -1,
228 .num_resources = ARRAY_SIZE(dm9000_resources),
229 .resource = dm9000_resources,
230};
231#endif
232
561cc18b
MH		 233#if defined(CONFIG_AX88180) || defined(CONFIG_AX88180_MODULE)
234static struct resource ax88180_resources[] = {
235 [0] = {
236 .start = 0x20300000,
237 .end = 0x20300000 + 0x8000,
238 .flags = IORESOURCE_MEM,
239 },
240 [1] = {
241 .start = IRQ_PF7,
242 .end = IRQ_PF7,
243 .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL),
244 },
245};
246
247static struct platform_device ax88180_device = {
248 .name = "ax88180",
249 .id = -1,
250 .num_resources = ARRAY_SIZE(ax88180_resources),
251 .resource = ax88180_resources,
252};
253#endif
254
1394f032
BW		 255#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
256static struct resource sl811_hcd_resources[] = {
257 {
258 .start = 0x20340000,
259 .end = 0x20340000,
260 .flags = IORESOURCE_MEM,
1f83b8f1 261 }, {
1394f032
BW		 262 .start = 0x20340004,
263 .end = 0x20340004,
264 .flags = IORESOURCE_MEM,
1f83b8f1 265 }, {
1394f032
BW		 266 .start = CONFIG_USB_SL811_BFIN_IRQ,
267 .end = CONFIG_USB_SL811_BFIN_IRQ,
268 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
269 },
270};
271
272#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
273void sl811_port_power(struct device *dev, int is_on)
274{
c6c4d7bb 275 gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS");
acbcd263 276 gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS, is_on);
1394f032
BW		 277}
278#endif
279
280static struct sl811_platform_data sl811_priv = {
281 .potpg = 10,
282 .power = 250, /* == 500mA */
283#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
284 .port_power = &sl811_port_power,
285#endif
286};
287
288static struct platform_device sl811_hcd_device = {
289 .name = "sl811-hcd",
290 .id = 0,
291 .dev = {
292 .platform_data = &sl811_priv,
293 },
294 .num_resources = ARRAY_SIZE(sl811_hcd_resources),
295 .resource = sl811_hcd_resources,
296};
297#endif
298
299#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
300static struct resource isp1362_hcd_resources[] = {
301 {
302 .start = 0x20360000,
303 .end = 0x20360000,
304 .flags = IORESOURCE_MEM,
1f83b8f1 305 }, {
1394f032
BW		 306 .start = 0x20360004,
307 .end = 0x20360004,
308 .flags = IORESOURCE_MEM,
1f83b8f1 309 }, {
1394f032
BW		 310 .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
311 .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
312 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
313 },
314};
315
316static struct isp1362_platform_data isp1362_priv = {
317 .sel15Kres = 1,
318 .clknotstop = 0,
319 .oc_enable = 0,
320 .int_act_high = 0,
321 .int_edge_triggered = 0,
322 .remote_wakeup_connected = 0,
323 .no_power_switching = 1,
324 .power_switching_mode = 0,
325};
326
327static struct platform_device isp1362_hcd_device = {
328 .name = "isp1362-hcd",
329 .id = 0,
330 .dev = {
331 .platform_data = &isp1362_priv,
332 },
333 .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
334 .resource = isp1362_hcd_resources,
335};
336#endif
337
338#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
65319628
GY		 339static struct platform_device bfin_mii_bus = {
340 .name = "bfin_mii_bus",
341};
342
1394f032
BW		 343static struct platform_device bfin_mac_device = {
344 .name = "bfin_mac",
65319628 345 .dev.platform_data = &bfin_mii_bus,
1394f032
BW		 346};
347#endif
348
349#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
350static struct resource net2272_bfin_resources[] = {
351 {
352 .start = 0x20300000,
353 .end = 0x20300000 + 0x100,
354 .flags = IORESOURCE_MEM,
1f83b8f1 355 }, {
1394f032
BW		 356 .start = IRQ_PF7,
357 .end = IRQ_PF7,
358 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
359 },
360};
361
362static struct platform_device net2272_bfin_device = {
363 .name = "net2272",
364 .id = -1,
365 .num_resources = ARRAY_SIZE(net2272_bfin_resources),
366 .resource = net2272_bfin_resources,
367};
368#endif
369
fc68911e
MF		 370#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
371#ifdef CONFIG_MTD_PARTITIONS
372const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL };
373
374static struct mtd_partition bfin_plat_nand_partitions[] = {
375 {
aa582977 376 .name = "linux kernel(nand)",
fc68911e
MF		 377 .size = 0x400000,
378 .offset = 0,
379 }, {
aa582977 380 .name = "file system(nand)",
fc68911e
MF		 381 .size = MTDPART_SIZ_FULL,
382 .offset = MTDPART_OFS_APPEND,
383 },
384};
385#endif
386
387#define BFIN_NAND_PLAT_CLE 2
388#define BFIN_NAND_PLAT_ALE 1
389static void bfin_plat_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
390{
391 struct nand_chip *this = mtd->priv;
392
393 if (cmd == NAND_CMD_NONE)
394 return;
395
396 if (ctrl & NAND_CLE)
397 writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_CLE));
398 else
399 writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_ALE));
400}
401
402#define BFIN_NAND_PLAT_READY GPIO_PF3
403static int bfin_plat_nand_dev_ready(struct mtd_info *mtd)
404{
405 return gpio_get_value(BFIN_NAND_PLAT_READY);
406}
407
408static struct platform_nand_data bfin_plat_nand_data = {
409 .chip = {
410 .chip_delay = 30,
411#ifdef CONFIG_MTD_PARTITIONS
412 .part_probe_types = part_probes,
413 .partitions = bfin_plat_nand_partitions,
414 .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions),
415#endif
416 },
417 .ctrl = {
418 .cmd_ctrl = bfin_plat_nand_cmd_ctrl,
419 .dev_ready = bfin_plat_nand_dev_ready,
420 },
421};
422
423#define MAX(x, y) (x > y ? x : y)
424static struct resource bfin_plat_nand_resources = {
425 .start = 0x20212000,
426 .end = 0x20212000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)),
427 .flags = IORESOURCE_IO,
428};
429
430static struct platform_device bfin_async_nand_device = {
431 .name = "gen_nand",
432 .id = -1,
433 .num_resources = 1,
434 .resource = &bfin_plat_nand_resources,
435 .dev = {
436 .platform_data = &bfin_plat_nand_data,
437 },
438};
439
440static void bfin_plat_nand_init(void)
441{
442 gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat");
443}
444#else
445static void bfin_plat_nand_init(void) {}
446#endif
447
793dc27b 448#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
de8c43f2
MF		 449static struct mtd_partition stamp_partitions[] = {
450 {
aa582977 451 .name = "bootloader(nor)",
edf05641 452 .size = 0x40000,
de8c43f2
MF		 453 .offset = 0,
454 }, {
aa582977 455 .name = "linux kernel(nor)",
6ecb5b6d 456 .size = 0x180000,
de8c43f2
MF		 457 .offset = MTDPART_OFS_APPEND,
458 }, {
aa582977 459 .name = "file system(nor)",
6ecb5b6d 460 .size = 0x400000 - 0x40000 - 0x180000 - 0x10000,
de8c43f2
MF		 461 .offset = MTDPART_OFS_APPEND,
462 }, {
aa582977 463 .name = "MAC Address(nor)",
de8c43f2
MF		 464 .size = MTDPART_SIZ_FULL,
465 .offset = 0x3F0000,
466 .mask_flags = MTD_WRITEABLE,
467 }
468};
469
470static struct physmap_flash_data stamp_flash_data = {
471 .width = 2,
472 .parts = stamp_partitions,
473 .nr_parts = ARRAY_SIZE(stamp_partitions),
474};
475
476static struct resource stamp_flash_resource = {
477 .start = 0x20000000,
478 .end = 0x203fffff,
479 .flags = IORESOURCE_MEM,
480};
481
482static struct platform_device stamp_flash_device = {
483 .name = "physmap-flash",
484 .id = 0,
485 .dev = {
486 .platform_data = &stamp_flash_data,
487 },
488 .num_resources = 1,
489 .resource = &stamp_flash_resource,
490};
793dc27b 491#endif
de8c43f2 492
1394f032
BW		 493#if defined(CONFIG_MTD_M25P80) \
494 || defined(CONFIG_MTD_M25P80_MODULE)
495static struct mtd_partition bfin_spi_flash_partitions[] = {
496 {
aa582977 497 .name = "bootloader(spi)",
edf05641 498 .size = 0x00040000,
1394f032
BW		 499 .offset = 0,
500 .mask_flags = MTD_CAP_ROM
1f83b8f1 501 }, {
aa582977 502 .name = "linux kernel(spi)",
6ecb5b6d 503 .size = 0x180000,
edf05641 504 .offset = MTDPART_OFS_APPEND,
1f83b8f1 505 }, {
aa582977 506 .name = "file system(spi)",
edf05641
MF		 507 .size = MTDPART_SIZ_FULL,
508 .offset = MTDPART_OFS_APPEND,
1394f032
BW		 509 }
510};
511
512static struct flash_platform_data bfin_spi_flash_data = {
513 .name = "m25p80",
514 .parts = bfin_spi_flash_partitions,
515 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
88a8078b 516 /* .type = "m25p64", */
1394f032
BW		 517};
518
519/* SPI flash chip (m25p64) */
520static struct bfin5xx_spi_chip spi_flash_chip_info = {
521 .enable_dma = 0, /* use dma transfer with this chip*/
522 .bits_per_word = 8,
523};
524#endif
525
a261eec0
MF		 526#if defined(CONFIG_BFIN_SPI_ADC) \
527 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
1394f032
BW		 528/* SPI ADC chip */
529static struct bfin5xx_spi_chip spi_adc_chip_info = {
530 .enable_dma = 1, /* use dma transfer with this chip*/
531 .bits_per_word = 16,
532};
533#endif
534
535#if defined(CONFIG_SND_BLACKFIN_AD1836) \
536 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
537static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
538 .enable_dma = 0,
539 .bits_per_word = 16,
540};
541#endif
542
d4b834c1
BS		 543#if defined(CONFIG_SND_BF5XX_SOC_AD1938) \
544 || defined(CONFIG_SND_BF5XX_SOC_AD1938_MODULE)
545static struct bfin5xx_spi_chip ad1938_spi_chip_info = {
546 .enable_dma = 0,
547 .bits_per_word = 8,
548 .cs_gpio = GPIO_PF5,
549};
550#endif
551
1394f032
BW		 552#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
553static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
554 .enable_dma = 0,
555 .bits_per_word = 16,
556};
557#endif
558
427f277e
BS		 559#if defined(CONFIG_INPUT_EVAL_AD7147EBZ)
560#include <linux/input.h>
561#include <linux/input/ad714x.h>
562static struct bfin5xx_spi_chip ad7147_spi_chip_info = {
563 .enable_dma = 0,
564 .bits_per_word = 16,
565};
566
567static struct ad714x_slider_plat slider_plat[] = {
568 {
569 .start_stage = 0,
570 .end_stage = 7,
571 .max_coord = 128,
572 },
573};
574
575static struct ad714x_button_plat button_plat[] = {
576 {
577 .keycode = BTN_FORWARD,
578 .l_mask = 0,
579 .h_mask = 0x600,
580 },
581 {
582 .keycode = BTN_LEFT,
583 .l_mask = 0,
584 .h_mask = 0x500,
585 },
586 {
587 .keycode = BTN_MIDDLE,
588 .l_mask = 0,
589 .h_mask = 0x800,
590 },
591 {
592 .keycode = BTN_RIGHT,
593 .l_mask = 0x100,
594 .h_mask = 0x400,
595 },
596 {
597 .keycode = BTN_BACK,
598 .l_mask = 0x200,
599 .h_mask = 0x400,
600 },
601};
602static struct ad714x_platform_data ad7147_platfrom_data = {
603 .slider_num = 1,
604 .button_num = 5,
605 .slider = slider_plat,
606 .button = button_plat,
607 .stage_cfg_reg = {
608 {0xFBFF, 0x1FFF, 0, 0x2626, 1600, 1600, 1600, 1600},
609 {0xEFFF, 0x1FFF, 0, 0x2626, 1650, 1650, 1650, 1650},
610 {0xFFFF, 0x1FFE, 0, 0x2626, 1650, 1650, 1650, 1650},
611 {0xFFFF, 0x1FFB, 0, 0x2626, 1650, 1650, 1650, 1650},
612 {0xFFFF, 0x1FEF, 0, 0x2626, 1650, 1650, 1650, 1650},
613 {0xFFFF, 0x1FBF, 0, 0x2626, 1650, 1650, 1650, 1650},
614 {0xFFFF, 0x1EFF, 0, 0x2626, 1650, 1650, 1650, 1650},
615 {0xFFFF, 0x1BFF, 0, 0x2626, 1600, 1600, 1600, 1600},
616 {0xFF7B, 0x3FFF, 0x506, 0x2626, 1100, 1100, 1150, 1150},
617 {0xFDFE, 0x3FFF, 0x606, 0x2626, 1100, 1100, 1150, 1150},
618 {0xFEBA, 0x1FFF, 0x1400, 0x2626, 1200, 1200, 1300, 1300},
619 {0xFFEF, 0x1FFF, 0x0, 0x2626, 1100, 1100, 1150, 1150},
620 },
621 .sys_cfg_reg = {0x2B2, 0x0, 0x3233, 0x819, 0x832, 0xCFF, 0xCFF, 0x0},
622};
623#endif
624
625#if defined(CONFIG_INPUT_EVAL_AD7142EB)
626#include <linux/input.h>
627#include <linux/input/ad714x.h>
628static struct ad714x_button_plat button_plat[] = {
629 {
630 .keycode = BTN_1,
631 .l_mask = 0,
632 .h_mask = 0x1,
633 },
634 {
635 .keycode = BTN_2,
636 .l_mask = 0,
637 .h_mask = 0x2,
638 },
639 {
640 .keycode = BTN_3,
641 .l_mask = 0,
642 .h_mask = 0x4,
643 },
644 {
645 .keycode = BTN_4,
646 .l_mask = 0x0,
647 .h_mask = 0x8,
648 },
649};
650static struct ad714x_platform_data ad7142_platfrom_data = {
651 .button_num = 4,
652 .button = button_plat,
653 .stage_cfg_reg = {
654 /* fixme: figure out right setting for all comoponent according
655 * to hardware feature of EVAL-AD7142EB board */
656 {0xE7FF, 0x3FFF, 0x0005, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A},
657 {0xFDBF, 0x3FFF, 0x0001, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A},
658 {0xFFFF, 0x2DFF, 0x0001, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A},
659 {0xFFFF, 0x37BF, 0x0001, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A},
660 {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
661 {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
662 {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
663 {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
664 {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
665 {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
666 {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
667 {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
668 },
669 .sys_cfg_reg = {0x0B2, 0x0, 0x690, 0x664, 0x290F, 0xF, 0xF, 0x0},
670};
671#endif
672
f79ea4cb
YL		 673#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
674#define MMC_SPI_CARD_DETECT_INT IRQ_PF5
675
676static int bfin_mmc_spi_init(struct device *dev,
677 irqreturn_t (*detect_int)(int, void *), void *data)
678{
679 return request_irq(MMC_SPI_CARD_DETECT_INT, detect_int,
680 IRQF_TRIGGER_FALLING, "mmc-spi-detect", data);
681}
682
683static void bfin_mmc_spi_exit(struct device *dev, void *data)
684{
685 free_irq(MMC_SPI_CARD_DETECT_INT, data);
686}
687
688static struct mmc_spi_platform_data bfin_mmc_spi_pdata = {
689 .init = bfin_mmc_spi_init,
690 .exit = bfin_mmc_spi_exit,
691 .detect_delay = 100, /* msecs */
692};
693
694static struct bfin5xx_spi_chip mmc_spi_chip_info = {
695 .enable_dma = 0,
696 .bits_per_word = 8,
e68d1ebc 697 .pio_interrupt = 0,
f79ea4cb
YL		 698};
699#endif
700
1394f032
BW		 701#if defined(CONFIG_PBX)
702static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
703 .ctl_reg = 0x4, /* send zero */
704 .enable_dma = 0,
705 .bits_per_word = 8,
706 .cs_change_per_word = 1,
707};
708#endif
709
1394f032 710#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
46aa04f9 711#include <linux/spi/ad7877.h>
1394f032 712static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
1394f032
BW		 713 .enable_dma = 0,
714 .bits_per_word = 16,
715};
716
717static const struct ad7877_platform_data bfin_ad7877_ts_info = {
718 .model = 7877,
719 .vref_delay_usecs = 50, /* internal, no capacitor */
720 .x_plate_ohms = 419,
721 .y_plate_ohms = 486,
722 .pressure_max = 1000,
723 .pressure_min = 0,
724 .stopacq_polarity = 1,
725 .first_conversion_delay = 3,
726 .acquisition_time = 1,
727 .averaging = 1,
728 .pen_down_acc_interval = 1,
729};
730#endif
731
46aa04f9
MH		 732#if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
733#include <linux/spi/ad7879.h>
46aa04f9
MH		 734static const struct ad7879_platform_data bfin_ad7879_ts_info = {
735 .model = 7879, /* Model = AD7879 */
736 .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
737 .pressure_max = 10000,
738 .pressure_min = 0,
739 .first_conversion_delay = 3, /* wait 512us before do a first conversion */
740 .acquisition_time = 1, /* 4us acquisition time per sample */
741 .median = 2, /* do 8 measurements */
742 .averaging = 1, /* take the average of 4 middle samples */
743 .pen_down_acc_interval = 255, /* 9.4 ms */
744 .gpio_output = 1, /* configure AUX/VBAT/GPIO as GPIO output */
745 .gpio_default = 1, /* During initialization set GPIO = HIGH */
746};
747#endif
748
ffc4d8bc
MH		 749#if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE)
750#include <linux/input.h>
751#include <linux/spi/adxl34x.h>
752static const struct adxl34x_platform_data adxl34x_info = {
753 .x_axis_offset = 0,
754 .y_axis_offset = 0,
755 .z_axis_offset = 0,
756 .tap_threshold = 0x31,
757 .tap_duration = 0x10,
758 .tap_latency = 0x60,
759 .tap_window = 0xF0,
760 .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
761 .act_axis_control = 0xFF,
762 .activity_threshold = 5,
763 .inactivity_threshold = 3,
764 .inactivity_time = 4,
765 .free_fall_threshold = 0x7,
766 .free_fall_time = 0x20,
767 .data_rate = 0x8,
768 .data_range = ADXL_FULL_RES,
769
770 .ev_type = EV_ABS,
771 .ev_code_x = ABS_X, /* EV_REL */
772 .ev_code_y = ABS_Y, /* EV_REL */
773 .ev_code_z = ABS_Z, /* EV_REL */
774
775 .ev_code_tap_x = BTN_TOUCH, /* EV_KEY */
776 .ev_code_tap_y = BTN_TOUCH, /* EV_KEY */
777 .ev_code_tap_z = BTN_TOUCH, /* EV_KEY */
778
779/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
780/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */
781 .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
782 .fifo_mode = ADXL_FIFO_STREAM,
783};
784#endif
785
f5150155
MH		 786#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
787static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
788 .enable_dma = 0,
789 .bits_per_word = 16,
790};
791#endif
792
6e668936
MH		 793#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
794static struct bfin5xx_spi_chip spidev_chip_info = {
795 .enable_dma = 0,
796 .bits_per_word = 8,
797};
798#endif
799
2043f3f7
MH		 800#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
801static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
802 .enable_dma = 0,
803 .bits_per_word = 8,
804};
805#endif
806
85a192e9
MH		 807#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE)
808static struct bfin5xx_spi_chip enc28j60_spi_chip_info = {
809 .enable_dma = 1,
810 .bits_per_word = 8,
811 .cs_gpio = GPIO_PF10,
812};
813#endif
814
8e9d5c7d
MH		 815#if defined(CONFIG_MTD_DATAFLASH) \
816 || defined(CONFIG_MTD_DATAFLASH_MODULE)
ceac2651
MH		 817
818static struct mtd_partition bfin_spi_dataflash_partitions[] = {
819 {
820 .name = "bootloader(spi)",
821 .size = 0x00040000,
822 .offset = 0,
823 .mask_flags = MTD_CAP_ROM
824 }, {
825 .name = "linux kernel(spi)",
6ecb5b6d 826 .size = 0x180000,
ceac2651
MH		 827 .offset = MTDPART_OFS_APPEND,
828 }, {
829 .name = "file system(spi)",
830 .size = MTDPART_SIZ_FULL,
831 .offset = MTDPART_OFS_APPEND,
832 }
833};
834
835static struct flash_platform_data bfin_spi_dataflash_data = {
836 .name = "SPI Dataflash",
837 .parts = bfin_spi_dataflash_partitions,
838 .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
839};
840
8e9d5c7d
MH		 841/* DataFlash chip */
842static struct bfin5xx_spi_chip data_flash_chip_info = {
843 .enable_dma = 0, /* use dma transfer with this chip*/
844 .bits_per_word = 8,
845};
846#endif
847
1394f032
BW		 848static struct spi_board_info bfin_spi_board_info[] __initdata = {
849#if defined(CONFIG_MTD_M25P80) \
850 || defined(CONFIG_MTD_M25P80_MODULE)
851 {
852 /* the modalias must be the same as spi device driver name */
853 .modalias = "m25p80", /* Name of spi_driver for this device */
854 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 855 .bus_num = 0, /* Framework bus number */
1394f032
BW		 856 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
857 .platform_data = &bfin_spi_flash_data,
858 .controller_data = &spi_flash_chip_info,
859 .mode = SPI_MODE_3,
860 },
861#endif
8e9d5c7d
MH		 862#if defined(CONFIG_MTD_DATAFLASH) \
863 || defined(CONFIG_MTD_DATAFLASH_MODULE)
864 { /* DataFlash chip */
865 .modalias = "mtd_dataflash",
ceac2651 866 .max_speed_hz = 33250000, /* max spi clock (SCK) speed in HZ */
8e9d5c7d
MH		 867 .bus_num = 0, /* Framework bus number */
868 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
ceac2651 869 .platform_data = &bfin_spi_dataflash_data,
8e9d5c7d
MH		 870 .controller_data = &data_flash_chip_info,
871 .mode = SPI_MODE_3,
872 },
873#endif
a261eec0
MF		 874#if defined(CONFIG_BFIN_SPI_ADC) \
875 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
1394f032
BW		 876 {
877 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
878 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 879 .bus_num = 0, /* Framework bus number */
1394f032
BW		 880 .chip_select = 1, /* Framework chip select. */
881 .platform_data = NULL, /* No spi_driver specific config */
882 .controller_data = &spi_adc_chip_info,
883 },
884#endif
885
886#if defined(CONFIG_SND_BLACKFIN_AD1836) \
887 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
888 {
889 .modalias = "ad1836-spi",
890 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 891 .bus_num = 0,
1394f032
BW		 892 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
893 .controller_data = &ad1836_spi_chip_info,
894 },
895#endif
d4b834c1
BS		 896
897#if defined(CONFIG_SND_BF5XX_SOC_AD1938) || defined(CONFIG_SND_BF5XX_SOC_AD1938_MODULE)
898 {
899 .modalias = "ad1938-spi",
900 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
901 .bus_num = 0,
902 .chip_select = 0,/* CONFIG_SND_BLACKFIN_SPI_PFBIT */
903 .controller_data = &ad1938_spi_chip_info,
904 .mode = SPI_MODE_3,
905 },
906#endif
907
1394f032
BW		 908#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
909 {
910 .modalias = "ad9960-spi",
911 .max_speed_hz = 10000000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 912 .bus_num = 0,
1394f032
BW		 913 .chip_select = 1,
914 .controller_data = &ad9960_spi_chip_info,
915 },
916#endif
427f277e
BS		 917
918#if defined(CONFIG_INPUT_EVAL_AD7147EBZ)
919 {
920 .modalias = "ad714x_captouch",
921 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
922 .irq = IRQ_PF4,
923 .bus_num = 0,
924 .chip_select = 5,
925 .mode = SPI_MODE_3,
926 .platform_data = &ad7147_platfrom_data,
927 .controller_data = &ad7147_spi_chip_info,
928 },
929#endif
930
f79ea4cb
YL		 931#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
932 {
933 .modalias = "mmc_spi",
934 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
935 .bus_num = 0,
936 .chip_select = 4,
937 .platform_data = &bfin_mmc_spi_pdata,
938 .controller_data = &mmc_spi_chip_info,
939 .mode = SPI_MODE_3,
940 },
941#endif
1394f032
BW		 942#if defined(CONFIG_PBX)
943 {
1f83b8f1
MF		 944 .modalias = "fxs-spi",
945 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb
BW		 946 .bus_num = 0,
947 .chip_select = 8 - CONFIG_J11_JUMPER,
1f83b8f1 948 .controller_data = &spi_si3xxx_chip_info,
1394f032
BW		 949 .mode = SPI_MODE_3,
950 },
951 {
1f83b8f1
MF		 952 .modalias = "fxo-spi",
953 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb
BW		 954 .bus_num = 0,
955 .chip_select = 8 - CONFIG_J19_JUMPER,
1f83b8f1 956 .controller_data = &spi_si3xxx_chip_info,
1394f032
BW		 957 .mode = SPI_MODE_3,
958 },
959#endif
1394f032
BW		 960#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
961 {
962 .modalias = "ad7877",
963 .platform_data = &bfin_ad7877_ts_info,
964 .irq = IRQ_PF6,
965 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
c7d48966 966 .bus_num = 0,
1394f032
BW		 967 .chip_select = 1,
968 .controller_data = &spi_ad7877_chip_info,
969 },
970#endif
f5150155 971#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
46aa04f9
MH		 972 {
973 .modalias = "ad7879",
974 .platform_data = &bfin_ad7879_ts_info,
975 .irq = IRQ_PF7,
976 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
977 .bus_num = 0,
978 .chip_select = 1,
979 .controller_data = &spi_ad7879_chip_info,
980 .mode = SPI_CPHA | SPI_CPOL,
981 },
982#endif
6e668936
MH		 983#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
984 {
985 .modalias = "spidev",
986 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
987 .bus_num = 0,
988 .chip_select = 1,
989 .controller_data = &spidev_chip_info,
990 },
991#endif
2043f3f7
MH		 992#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
993 {
994 .modalias = "bfin-lq035q1-spi",
995 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
996 .bus_num = 0,
46aa04f9 997 .chip_select = 2,
2043f3f7
MH		 998 .controller_data = &lq035q1_spi_chip_info,
999 .mode = SPI_CPHA | SPI_CPOL,
1000 },
1001#endif
85a192e9
MH		 1002#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE)
1003 {
1004 .modalias = "enc28j60",
1005 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
1006 .irq = IRQ_PF6,
1007 .bus_num = 0,
1008 .chip_select = 0, /* GPIO controlled SSEL */
1009 .controller_data = &enc28j60_spi_chip_info,
1010 .mode = SPI_MODE_0,
1011 },
1012#endif
1394f032
BW		 1013};
1014
5bda2723 1015#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
1394f032 1016/* SPI controller data */
c6c4d7bb 1017static struct bfin5xx_spi_master bfin_spi0_info = {
1394f032
BW		 1018 .num_chipselect = 8,
1019 .enable_dma = 1, /* master has the ability to do dma transfer */
5d448dd5 1020 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1394f032
BW		 1021};
1022
c6c4d7bb
BW		 1023/* SPI (0) */
1024static struct resource bfin_spi0_resource[] = {
1025 [0] = {
1026 .start = SPI0_REGBASE,
1027 .end = SPI0_REGBASE + 0xFF,
1028 .flags = IORESOURCE_MEM,
1029 },
1030 [1] = {
1031 .start = CH_SPI,
1032 .end = CH_SPI,
e68d1ebc
YL		 1033 .flags = IORESOURCE_DMA,
1034 },
1035 [2] = {
1036 .start = IRQ_SPI,
1037 .end = IRQ_SPI,
c6c4d7bb
BW		 1038 .flags = IORESOURCE_IRQ,
1039 },
1040};
1041
1042static struct platform_device bfin_spi0_device = {
1043 .name = "bfin-spi",
1044 .id = 0, /* Bus number */
1045 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
1046 .resource = bfin_spi0_resource,
1394f032 1047 .dev = {
c6c4d7bb 1048 .platform_data = &bfin_spi0_info, /* Passed to driver */
1394f032
BW		 1049 },
1050};
1051#endif /* spi master and devices */
1052
1e9aa955
CC		 1053#if defined(CONFIG_SPI_BFIN_SPORT) || defined(CONFIG_SPI_BFIN_SPORT_MODULE)
1054
1055/* SPORT SPI controller data */
1056static struct bfin5xx_spi_master bfin_sport_spi0_info = {
1057 .num_chipselect = 1, /* master only supports one device */
1058 .enable_dma = 0, /* master don't support DMA */
1059 .pin_req = {P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_DRPRI,
1060 P_SPORT0_RSCLK, P_SPORT0_TFS, P_SPORT0_RFS, 0},
1061};
1062
1063static struct resource bfin_sport_spi0_resource[] = {
1064 [0] = {
1065 .start = SPORT0_TCR1,
1066 .end = SPORT0_TCR1 + 0xFF,
1067 .flags = IORESOURCE_MEM,
1068 },
1069 [1] = {
1070 .start = IRQ_SPORT0_ERROR,
1071 .end = IRQ_SPORT0_ERROR,
1072 .flags = IORESOURCE_IRQ,
1073 },
1074};
1075
1076static struct platform_device bfin_sport_spi0_device = {
1077 .name = "bfin-sport-spi",
1078 .id = 1, /* Bus number */
1079 .num_resources = ARRAY_SIZE(bfin_sport_spi0_resource),
1080 .resource = bfin_sport_spi0_resource,
1081 .dev = {
1082 .platform_data = &bfin_sport_spi0_info, /* Passed to driver */
1083 },
1084};
1085
1086static struct bfin5xx_spi_master bfin_sport_spi1_info = {
1087 .num_chipselect = 1, /* master only supports one device */
1088 .enable_dma = 0, /* master don't support DMA */
1089 .pin_req = {P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_DRPRI,
1090 P_SPORT1_RSCLK, P_SPORT1_TFS, P_SPORT1_RFS, 0},
1091};
1092
1093static struct resource bfin_sport_spi1_resource[] = {
1094 [0] = {
1095 .start = SPORT1_TCR1,
1096 .end = SPORT1_TCR1 + 0xFF,
1097 .flags = IORESOURCE_MEM,
1098 },
1099 [1] = {
1100 .start = IRQ_SPORT1_ERROR,
1101 .end = IRQ_SPORT1_ERROR,
1102 .flags = IORESOURCE_IRQ,
1103 },
1104};
1105
1106static struct platform_device bfin_sport_spi1_device = {
1107 .name = "bfin-sport-spi",
1108 .id = 2, /* Bus number */
1109 .num_resources = ARRAY_SIZE(bfin_sport_spi1_resource),
1110 .resource = bfin_sport_spi1_resource,
1111 .dev = {
1112 .platform_data = &bfin_sport_spi1_info, /* Passed to driver */
1113 },
1114};
1115
1116#endif /* sport spi master and devices */
1117
1394f032
BW		 1118#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
1119static struct platform_device bfin_fb_device = {
c6c4d7bb
BW		 1120 .name = "bf537-lq035",
1121};
1122#endif
1123
1124#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
1125static struct platform_device bfin_fb_adv7393_device = {
1126 .name = "bfin-adv7393",
1394f032
BW		 1127};
1128#endif
1129
2043f3f7
MH		 1130#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
1131#include <asm/bfin-lq035q1.h>
1132
1133static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
1134 .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
46aa04f9 1135 .use_bl = 0, /* let something else control the LCD Blacklight */
2043f3f7
MH		 1136 .gpio_bl = GPIO_PF7,
1137};
1138
1139static struct resource bfin_lq035q1_resources[] = {
1140 {
1141 .start = IRQ_PPI_ERROR,
1142 .end = IRQ_PPI_ERROR,
1143 .flags = IORESOURCE_IRQ,
1144 },
1145};
1146
1147static struct platform_device bfin_lq035q1_device = {
1148 .name = "bfin-lq035q1",
1149 .id = -1,
1150 .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
1151 .resource = bfin_lq035q1_resources,
1152 .dev = {
1153 .platform_data = &bfin_lq035q1_data,
1154 },
1155};
1156#endif
1157
1394f032
BW		 1158#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
1159static struct resource bfin_uart_resources[] = {
233b28a9 1160#ifdef CONFIG_SERIAL_BFIN_UART0
1394f032
BW		 1161 {
1162 .start = 0xFFC00400,
1163 .end = 0xFFC004FF,
1164 .flags = IORESOURCE_MEM,
233b28a9
SZ		 1165 },
1166#endif
1167#ifdef CONFIG_SERIAL_BFIN_UART1
1168 {
1394f032
BW		 1169 .start = 0xFFC02000,
1170 .end = 0xFFC020FF,
1171 .flags = IORESOURCE_MEM,
1172 },
233b28a9 1173#endif
1394f032
BW		 1174};
1175
1176static struct platform_device bfin_uart_device = {
1177 .name = "bfin-uart",
1178 .id = 1,
1179 .num_resources = ARRAY_SIZE(bfin_uart_resources),
1180 .resource = bfin_uart_resources,
1181};
1182#endif
1183
5be36d22 1184#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
5be36d22 1185#ifdef CONFIG_BFIN_SIR0
42bd8bcb 1186static struct resource bfin_sir0_resources[] = {
5be36d22
GY		 1187 {
1188 .start = 0xFFC00400,
1189 .end = 0xFFC004FF,
1190 .flags = IORESOURCE_MEM,
1191 },
42bd8bcb
GY		 1192 {
1193 .start = IRQ_UART0_RX,
1194 .end = IRQ_UART0_RX+1,
1195 .flags = IORESOURCE_IRQ,
1196 },
1197 {
1198 .start = CH_UART0_RX,
1199 .end = CH_UART0_RX+1,
1200 .flags = IORESOURCE_DMA,
1201 },
1202};
1203
1204static struct platform_device bfin_sir0_device = {
1205 .name = "bfin_sir",
1206 .id = 0,
1207 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
1208 .resource = bfin_sir0_resources,
1209};
5be36d22
GY		 1210#endif
1211#ifdef CONFIG_BFIN_SIR1
42bd8bcb 1212static struct resource bfin_sir1_resources[] = {
5be36d22
GY		 1213 {
1214 .start = 0xFFC02000,
1215 .end = 0xFFC020FF,
1216 .flags = IORESOURCE_MEM,
1217 },
42bd8bcb
GY		 1218 {
1219 .start = IRQ_UART1_RX,
1220 .end = IRQ_UART1_RX+1,
1221 .flags = IORESOURCE_IRQ,
1222 },
1223 {
1224 .start = CH_UART1_RX,
1225 .end = CH_UART1_RX+1,
1226 .flags = IORESOURCE_DMA,
1227 },
5be36d22
GY		 1228};
1229
42bd8bcb 1230static struct platform_device bfin_sir1_device = {
5be36d22 1231 .name = "bfin_sir",
42bd8bcb
GY		 1232 .id = 1,
1233 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
1234 .resource = bfin_sir1_resources,
5be36d22
GY		 1235};
1236#endif
42bd8bcb 1237#endif
5be36d22 1238
1394f032 1239#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
c6c4d7bb
BW		 1240static struct resource bfin_twi0_resource[] = {
1241 [0] = {
1242 .start = TWI0_REGBASE,
1243 .end = TWI0_REGBASE,
1244 .flags = IORESOURCE_MEM,
1245 },
1246 [1] = {
1247 .start = IRQ_TWI,
1248 .end = IRQ_TWI,
1249 .flags = IORESOURCE_IRQ,
1250 },
1251};
1252
1394f032
BW		 1253static struct platform_device i2c_bfin_twi_device = {
1254 .name = "i2c-bfin-twi",
1255 .id = 0,
c6c4d7bb
BW		 1256 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
1257 .resource = bfin_twi0_resource,
1394f032
BW		 1258};
1259#endif
1260
51ed9ad7
MH		 1261#if defined(CONFIG_KEYBOARD_ADP5588) || defined(CONFIG_KEYBOARD_ADP5588_MODULE)
1262#include <linux/input.h>
f39d56ec 1263#include <linux/i2c/adp5588.h>
51ed9ad7
MH		 1264static const unsigned short adp5588_keymap[ADP5588_KEYMAPSIZE] = {
1265 [0] = KEY_GRAVE,
1266 [1] = KEY_1,
1267 [2] = KEY_2,
1268 [3] = KEY_3,
1269 [4] = KEY_4,
1270 [5] = KEY_5,
1271 [6] = KEY_6,
1272 [7] = KEY_7,
1273 [8] = KEY_8,
1274 [9] = KEY_9,
1275 [10] = KEY_0,
1276 [11] = KEY_MINUS,
1277 [12] = KEY_EQUAL,
1278 [13] = KEY_BACKSLASH,
1279 [15] = KEY_KP0,
1280 [16] = KEY_Q,
1281 [17] = KEY_W,
1282 [18] = KEY_E,
1283 [19] = KEY_R,
1284 [20] = KEY_T,
1285 [21] = KEY_Y,
1286 [22] = KEY_U,
1287 [23] = KEY_I,
1288 [24] = KEY_O,
1289 [25] = KEY_P,
1290 [26] = KEY_LEFTBRACE,
1291 [27] = KEY_RIGHTBRACE,
1292 [29] = KEY_KP1,
1293 [30] = KEY_KP2,
1294 [31] = KEY_KP3,
1295 [32] = KEY_A,
1296 [33] = KEY_S,
1297 [34] = KEY_D,
1298 [35] = KEY_F,
1299 [36] = KEY_G,
1300 [37] = KEY_H,
1301 [38] = KEY_J,
1302 [39] = KEY_K,
1303 [40] = KEY_L,
1304 [41] = KEY_SEMICOLON,
1305 [42] = KEY_APOSTROPHE,
1306 [43] = KEY_BACKSLASH,
1307 [45] = KEY_KP4,
1308 [46] = KEY_KP5,
1309 [47] = KEY_KP6,
1310 [48] = KEY_102ND,
1311 [49] = KEY_Z,
1312 [50] = KEY_X,
1313 [51] = KEY_C,
1314 [52] = KEY_V,
1315 [53] = KEY_B,
1316 [54] = KEY_N,
1317 [55] = KEY_M,
1318 [56] = KEY_COMMA,
1319 [57] = KEY_DOT,
1320 [58] = KEY_SLASH,
1321 [60] = KEY_KPDOT,
1322 [61] = KEY_KP7,
1323 [62] = KEY_KP8,
1324 [63] = KEY_KP9,
1325 [64] = KEY_SPACE,
1326 [65] = KEY_BACKSPACE,
1327 [66] = KEY_TAB,
1328 [67] = KEY_KPENTER,
1329 [68] = KEY_ENTER,
1330 [69] = KEY_ESC,
1331 [70] = KEY_DELETE,
1332 [74] = KEY_KPMINUS,
1333 [76] = KEY_UP,
1334 [77] = KEY_DOWN,
1335 [78] = KEY_RIGHT,
1336 [79] = KEY_LEFT,
1337};
1338
1339static struct adp5588_kpad_platform_data adp5588_kpad_data = {
1340 .rows = 8,
1341 .cols = 10,
1342 .keymap = adp5588_keymap,
1343 .keymapsize = ARRAY_SIZE(adp5588_keymap),
1344 .repeat = 0,
1345};
1346#endif
1347
3ea57218
MH		 1348#if defined(CONFIG_PMIC_ADP5520) || defined(CONFIG_PMIC_ADP5520_MODULE)
1349#include <linux/mfd/adp5520.h>
1350
1351 /*
1352 * ADP5520/5501 Backlight Data
1353 */
1354
1355static struct adp5520_backlight_platfrom_data adp5520_backlight_data = {
1356 .fade_in = FADE_T_1200ms,
1357 .fade_out = FADE_T_1200ms,
1358 .fade_led_law = BL_LAW_LINEAR,
1359 .en_ambl_sens = 1,
1360 .abml_filt = BL_AMBL_FILT_640ms,
1361 .l1_daylight_max = BL_CUR_mA(15),
1362 .l1_daylight_dim = BL_CUR_mA(0),
1363 .l2_office_max = BL_CUR_mA(7),
1364 .l2_office_dim = BL_CUR_mA(0),
1365 .l3_dark_max = BL_CUR_mA(3),
1366 .l3_dark_dim = BL_CUR_mA(0),
1367 .l2_trip = L2_COMP_CURR_uA(700),
1368 .l2_hyst = L2_COMP_CURR_uA(50),
1369 .l3_trip = L3_COMP_CURR_uA(80),
1370 .l3_hyst = L3_COMP_CURR_uA(20),
1371};
1372
1373 /*
1374 * ADP5520/5501 LEDs Data
1375 */
1376
1377#include <linux/leds.h>
1378
1379static struct led_info adp5520_leds[] = {
1380 {
1381 .name = "adp5520-led1",
1382 .default_trigger = "none",
1383 .flags = FLAG_ID_ADP5520_LED1_ADP5501_LED0 | LED_OFFT_600ms,
1384 },
1385#ifdef ADP5520_EN_ALL_LEDS
1386 {
1387 .name = "adp5520-led2",
1388 .default_trigger = "none",
1389 .flags = FLAG_ID_ADP5520_LED2_ADP5501_LED1,
1390 },
1391 {
1392 .name = "adp5520-led3",
1393 .default_trigger = "none",
1394 .flags = FLAG_ID_ADP5520_LED3_ADP5501_LED2,
1395 },
1396#endif
1397};
1398
1399static struct adp5520_leds_platfrom_data adp5520_leds_data = {
1400 .num_leds = ARRAY_SIZE(adp5520_leds),
1401 .leds = adp5520_leds,
1402 .fade_in = FADE_T_600ms,
1403 .fade_out = FADE_T_600ms,
1404 .led_on_time = LED_ONT_600ms,
1405};
1406
1407 /*
1408 * ADP5520 GPIO Data
1409 */
1410
1411static struct adp5520_gpio_platfrom_data adp5520_gpio_data = {
1412 .gpio_start = 50,
1413 .gpio_en_mask = GPIO_C1 | GPIO_C2 | GPIO_R2,
1414 .gpio_pullup_mask = GPIO_C1 | GPIO_C2 | GPIO_R2,
1415};
1416
1417 /*
1418 * ADP5520 Keypad Data
1419 */
1420
1421#include <linux/input.h>
1422static const unsigned short adp5520_keymap[ADP5520_KEYMAPSIZE] = {
1423 [KEY(0, 0)] = KEY_GRAVE,
1424 [KEY(0, 1)] = KEY_1,
1425 [KEY(0, 2)] = KEY_2,
1426 [KEY(0, 3)] = KEY_3,
1427 [KEY(1, 0)] = KEY_4,
1428 [KEY(1, 1)] = KEY_5,
1429 [KEY(1, 2)] = KEY_6,
1430 [KEY(1, 3)] = KEY_7,
1431 [KEY(2, 0)] = KEY_8,
1432 [KEY(2, 1)] = KEY_9,
1433 [KEY(2, 2)] = KEY_0,
1434 [KEY(2, 3)] = KEY_MINUS,
1435 [KEY(3, 0)] = KEY_EQUAL,
1436 [KEY(3, 1)] = KEY_BACKSLASH,
1437 [KEY(3, 2)] = KEY_BACKSPACE,
1438 [KEY(3, 3)] = KEY_ENTER,
1439};
1440
1441static struct adp5520_keys_platfrom_data adp5520_keys_data = {
1442 .rows_en_mask = ROW_R3 | ROW_R2 | ROW_R1 | ROW_R0,
1443 .cols_en_mask = COL_C3 | COL_C2 | COL_C1 | COL_C0,
1444 .keymap = adp5520_keymap,
1445 .keymapsize = ARRAY_SIZE(adp5520_keymap),
1446 .repeat = 0,
1447};
1448
1449 /*
1450 * ADP5520/5501 Multifuction Device Init Data
1451 */
1452
1453static struct adp5520_subdev_info adp5520_subdevs[] = {
1454 {
1455 .name = "adp5520-backlight",
1456 .id = ID_ADP5520,
1457 .platform_data = &adp5520_backlight_data,
1458 },
1459 {
1460 .name = "adp5520-led",
1461 .id = ID_ADP5520,
1462 .platform_data = &adp5520_leds_data,
1463 },
1464 {
1465 .name = "adp5520-gpio",
1466 .id = ID_ADP5520,
1467 .platform_data = &adp5520_gpio_data,
1468 },
1469 {
1470 .name = "adp5520-keys",
1471 .id = ID_ADP5520,
1472 .platform_data = &adp5520_keys_data,
1473 },
1474};
1475
1476static struct adp5520_platform_data adp5520_pdev_data = {
1477 .num_subdevs = ARRAY_SIZE(adp5520_subdevs),
1478 .subdevs = adp5520_subdevs,
1479};
1480
1481#endif
1482
81d9c7f2 1483static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
427f277e 1484#if defined(CONFIG_INPUT_EVAL_AD7142EB)
81d9c7f2 1485 {
427f277e 1486 I2C_BOARD_INFO("ad7142_captouch", 0x2C),
4c94c3e0 1487 .irq = IRQ_PG5,
427f277e 1488 .platform_data = (void *)&ad7142_platfrom_data,
81d9c7f2
BW		 1489 },
1490#endif
ebd58333 1491#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
81d9c7f2
BW		 1492 {
1493 I2C_BOARD_INFO("pcf8574_lcd", 0x22),
81d9c7f2
BW		 1494 },
1495#endif
204844eb 1496#if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE)
81d9c7f2
BW		 1497 {
1498 I2C_BOARD_INFO("pcf8574_keypad", 0x27),
f5150155
MH		 1499 .irq = IRQ_PG6,
1500 },
1501#endif
1502#if defined(CONFIG_TOUCHSCREEN_AD7879_I2C) || defined(CONFIG_TOUCHSCREEN_AD7879_I2C_MODULE)
1503 {
1504 I2C_BOARD_INFO("ad7879", 0x2F),
1505 .irq = IRQ_PG5,
1506 .platform_data = (void *)&bfin_ad7879_ts_info,
81d9c7f2
BW		 1507 },
1508#endif
51ed9ad7
MH		 1509#if defined(CONFIG_KEYBOARD_ADP5588) || defined(CONFIG_KEYBOARD_ADP5588_MODULE)
1510 {
1511 I2C_BOARD_INFO("adp5588-keys", 0x34),
1512 .irq = IRQ_PG0,
1513 .platform_data = (void *)&adp5588_kpad_data,
1514 },
1515#endif
3ea57218
MH		 1516#if defined(CONFIG_PMIC_ADP5520) || defined(CONFIG_PMIC_ADP5520_MODULE)
1517 {
1518 I2C_BOARD_INFO("pmic-adp5520", 0x32),
4f84b6e0 1519 .irq = IRQ_PG0,
3ea57218
MH		 1520 .platform_data = (void *)&adp5520_pdev_data,
1521 },
1522#endif
ffc4d8bc
MH		 1523#if defined(CONFIG_INPUT_ADXL34X_I2C) || defined(CONFIG_INPUT_ADXL34X_I2C_MODULE)
1524 {
1525 I2C_BOARD_INFO("adxl34x", 0x53),
1526 .irq = IRQ_PG3,
1527 .platform_data = (void *)&adxl34x_info,
1528 },
1529#endif
81d9c7f2 1530};
81d9c7f2 1531
1394f032
BW		 1532#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
1533static struct platform_device bfin_sport0_uart_device = {
1534 .name = "bfin-sport-uart",
1535 .id = 0,
1536};
1537
1538static struct platform_device bfin_sport1_uart_device = {
1539 .name = "bfin-sport-uart",
1540 .id = 1,
1541};
1542#endif
1543
c6c4d7bb 1544#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
2c8beb2c
MH		 1545#define CF_IDE_NAND_CARD_USE_HDD_INTERFACE
1546/* #define CF_IDE_NAND_CARD_USE_CF_IN_COMMON_MEMORY_MODE */
c6c4d7bb 1547
2c8beb2c
MH		 1548#ifdef CF_IDE_NAND_CARD_USE_HDD_INTERFACE
1549#define PATA_INT IRQ_PF5
c6c4d7bb
BW		 1550static struct pata_platform_info bfin_pata_platform_data = {
1551 .ioport_shift = 1,
64e5c512 1552 .irq_flags = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
c6c4d7bb
BW		 1553};
1554
1555static struct resource bfin_pata_resources[] = {
1556 {
1557 .start = 0x20314020,
1558 .end = 0x2031403F,
1559 .flags = IORESOURCE_MEM,
1560 },
1561 {
1562 .start = 0x2031401C,
1563 .end = 0x2031401F,
1564 .flags = IORESOURCE_MEM,
1565 },
1566 {
1567 .start = PATA_INT,
1568 .end = PATA_INT,
1569 .flags = IORESOURCE_IRQ,
1570 },
1571};
2c8beb2c
MH		 1572#elif defined(CF_IDE_NAND_CARD_USE_CF_IN_COMMON_MEMORY_MODE)
1573static struct pata_platform_info bfin_pata_platform_data = {
1574 .ioport_shift = 0,
1575};
648882d9
MH		 1576/* CompactFlash Storage Card Memory Mapped Adressing
1577 * /REG = A11 = 1
1578 */
2c8beb2c
MH		 1579static struct resource bfin_pata_resources[] = {
1580 {
648882d9
MH		 1581 .start = 0x20211800,
1582 .end = 0x20211807,
2c8beb2c
MH		 1583 .flags = IORESOURCE_MEM,
1584 },
1585 {
648882d9
MH		 1586 .start = 0x2021180E, /* Device Ctl */
1587 .end = 0x2021180E,
2c8beb2c
MH		 1588 .flags = IORESOURCE_MEM,
1589 },
1590};
1591#endif
c6c4d7bb
BW		 1592
1593static struct platform_device bfin_pata_device = {
1594 .name = "pata_platform",
1595 .id = -1,
1596 .num_resources = ARRAY_SIZE(bfin_pata_resources),
1597 .resource = bfin_pata_resources,
1598 .dev = {
1599 .platform_data = &bfin_pata_platform_data,
1600 }
1601};
1602#endif
1603
14b03204
MH		 1604static const unsigned int cclk_vlev_datasheet[] =
1605{
1606 VRPAIR(VLEV_085, 250000000),
1607 VRPAIR(VLEV_090, 376000000),
1608 VRPAIR(VLEV_095, 426000000),
1609 VRPAIR(VLEV_100, 426000000),
1610 VRPAIR(VLEV_105, 476000000),
1611 VRPAIR(VLEV_110, 476000000),
1612 VRPAIR(VLEV_115, 476000000),
1613 VRPAIR(VLEV_120, 500000000),
1614 VRPAIR(VLEV_125, 533000000),
1615 VRPAIR(VLEV_130, 600000000),
1616};
1617
1618static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
1619 .tuple_tab = cclk_vlev_datasheet,
1620 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
1621 .vr_settling_time = 25 /* us */,
1622};
1623
1624static struct platform_device bfin_dpmc = {
1625 .name = "bfin dpmc",
1626 .dev = {
1627 .platform_data = &bfin_dmpc_vreg_data,
1628 },
1629};
1630
1394f032 1631static struct platform_device *stamp_devices[] __initdata = {
14b03204
MH		 1632
1633 &bfin_dpmc,
1634
1394f032
BW		 1635#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
1636 &bfin_pcmcia_cf_device,
1637#endif
1638
1639#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
1640 &rtc_device,
1641#endif
1642
1643#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
1644 &sl811_hcd_device,
1645#endif
1646
1647#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
1648 &isp1362_hcd_device,
1649#endif
1650
3f375690
MH		 1651#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
1652 &bfin_isp1760_device,
1653#endif
1654
1394f032
BW		 1655#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
1656 &smc91x_device,
1657#endif
1658
f40d24d9
AL		 1659#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
1660 &dm9000_device,
1661#endif
1662
561cc18b
MH		 1663#if defined(CONFIG_AX88180) || defined(CONFIG_AX88180_MODULE)
1664 &ax88180_device,
1665#endif
1666
1394f032 1667#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
65319628 1668 &bfin_mii_bus,
1394f032
BW		 1669 &bfin_mac_device,
1670#endif
1671
1672#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
1673 &net2272_bfin_device,
1674#endif
1675
1676#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
c6c4d7bb 1677 &bfin_spi0_device,
1394f032
BW		 1678#endif
1679
1e9aa955
CC		 1680#if defined(CONFIG_SPI_BFIN_SPORT) || defined(CONFIG_SPI_BFIN_SPORT_MODULE)
1681 &bfin_sport_spi0_device,
1682 &bfin_sport_spi1_device,
1683#endif
1684
1394f032
BW		 1685#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
1686 &bfin_fb_device,
1687#endif
1688
2043f3f7
MH		 1689#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
1690 &bfin_lq035q1_device,
1691#endif
1692
c6c4d7bb
BW		 1693#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
1694 &bfin_fb_adv7393_device,
1695#endif
1696
1394f032
BW		 1697#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
1698 &bfin_uart_device,
1699#endif
1700
5be36d22 1701#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
42bd8bcb
GY		 1702#ifdef CONFIG_BFIN_SIR0
1703 &bfin_sir0_device,
1704#endif
1705#ifdef CONFIG_BFIN_SIR1
1706 &bfin_sir1_device,
1707#endif
5be36d22
GY		 1708#endif
1709
1394f032
BW		 1710#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
1711 &i2c_bfin_twi_device,
1712#endif
1713
1714#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
1715 &bfin_sport0_uart_device,
1716 &bfin_sport1_uart_device,
1717#endif
c6c4d7bb
BW		 1718
1719#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
1720 &bfin_pata_device,
1721#endif
2463ef22
MH		 1722
1723#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
1724 &bfin_device_gpiokeys,
1725#endif
cad2ab65
MF		 1726
1727 &bfin_gpios_device,
793dc27b 1728
fc68911e
MF		 1729#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
1730 &bfin_async_nand_device,
1731#endif
1732
793dc27b 1733#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
de8c43f2 1734 &stamp_flash_device,
793dc27b 1735#endif
1394f032
BW		 1736};
1737
1738static int __init stamp_init(void)
1739{
b85d858b 1740 printk(KERN_INFO "%s(): registering device resources\n", __func__);
81d9c7f2
BW		 1741 i2c_register_board_info(0, bfin_i2c_board_info,
1742 ARRAY_SIZE(bfin_i2c_board_info));
fc68911e 1743 bfin_plat_nand_init();
1394f032 1744 platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
5bda2723 1745 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
c6c4d7bb 1746
1394f032
BW		 1747 return 0;
1748}
1749
1750arch_initcall(stamp_init);
c6c4d7bb
BW		 1751
1752void native_machine_restart(char *cmd)
1753{
1754 /* workaround reboot hang when booting from SPI */
1755 if ((bfin_read_SYSCR() & 0x7) == 0x3)
b52dae31 1756 bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
c6c4d7bb 1757}
137b1529
MF		 1758
1759/*
1760 * Currently the MAC address is saved in Flash by U-Boot
1761 */
1762#define FLASH_MAC 0x203f0000
9862cc52 1763void bfin_get_ether_addr(char *addr)
137b1529
MF		 1764{
1765 *(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC);
1766 *(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4);
1767}
9862cc52 1768EXPORT_SYMBOL(bfin_get_ether_addr);
kernel source for telekom puls (alcatel/mediatek)