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Blackfin arch: Zero out bss region in L1/L2 memory.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / blackfin / mach-bf537 / boards / stamp.c
CommitLineData
1394f032
BW		 1/*
2 * File: arch/blackfin/mach-bf537/boards/stamp.c
3 * Based on: arch/blackfin/mach-bf533/boards/ezkit.c
4 * Author: Aidan Williams <aidan@nicta.com.au>
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2005 National ICT Australia (NICTA)
11 * Copyright 2004-2006 Analog Devices Inc.
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see the file COPYING, or write
27 * to the Free Software Foundation, Inc.,
28 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 */
30
31#include <linux/device.h>
fc68911e 32#include <linux/kernel.h>
1394f032
BW		 33#include <linux/platform_device.h>
34#include <linux/mtd/mtd.h>
fc68911e 35#include <linux/mtd/nand.h>
1394f032 36#include <linux/mtd/partitions.h>
fc68911e 37#include <linux/mtd/plat-ram.h>
de8c43f2 38#include <linux/mtd/physmap.h>
1394f032
BW		 39#include <linux/spi/spi.h>
40#include <linux/spi/flash.h>
41#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
f02bcec5 42#include <linux/usb/isp1362.h>
1394f032 43#endif
0a87e3e9 44#include <linux/ata_platform.h>
1394f032
BW		 45#include <linux/irq.h>
46#include <linux/interrupt.h>
81d9c7f2 47#include <linux/i2c.h>
27f5d75a 48#include <linux/usb/sl811.h>
c6c4d7bb 49#include <asm/dma.h>
1f83b8f1 50#include <asm/bfin5xx_spi.h>
c6c4d7bb 51#include <asm/reboot.h>
5d448dd5 52#include <asm/portmux.h>
14b03204 53#include <asm/dpmc.h>
1394f032
BW		 54
55/*
56 * Name the Board for the /proc/cpuinfo
57 */
066954a3 58const char bfin_board_name[] = "ADDS-BF537-STAMP";
1394f032
BW		 59
60/*
61 * Driver needs to know address, irq and flag pin.
62 */
63
64#define ISP1761_BASE 0x203C0000
65#define ISP1761_IRQ IRQ_PF7
66
67#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
68static struct resource bfin_isp1761_resources[] = {
69 [0] = {
70 .name = "isp1761-regs",
71 .start = ISP1761_BASE + 0x00000000,
72 .end = ISP1761_BASE + 0x000fffff,
73 .flags = IORESOURCE_MEM,
74 },
75 [1] = {
76 .start = ISP1761_IRQ,
77 .end = ISP1761_IRQ,
78 .flags = IORESOURCE_IRQ,
79 },
80};
81
82static struct platform_device bfin_isp1761_device = {
83 .name = "isp1761",
84 .id = 0,
85 .num_resources = ARRAY_SIZE(bfin_isp1761_resources),
86 .resource = bfin_isp1761_resources,
87};
88
89static struct platform_device *bfin_isp1761_devices[] = {
90 &bfin_isp1761_device,
91};
92
93int __init bfin_isp1761_init(void)
94{
1f83b8f1 95 unsigned int num_devices = ARRAY_SIZE(bfin_isp1761_devices);
1394f032 96
b85d858b 97 printk(KERN_INFO "%s(): registering device resources\n", __func__);
1394f032
BW		 98 set_irq_type(ISP1761_IRQ, IRQF_TRIGGER_FALLING);
99
100 return platform_add_devices(bfin_isp1761_devices, num_devices);
101}
102
103void __exit bfin_isp1761_exit(void)
104{
105 platform_device_unregister(&bfin_isp1761_device);
106}
107
108arch_initcall(bfin_isp1761_init);
109#endif
110
2463ef22
MH		 111#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
112#include <linux/input.h>
113#include <linux/gpio_keys.h>
114
115static struct gpio_keys_button bfin_gpio_keys_table[] = {
116 {BTN_0, GPIO_PF2, 1, "gpio-keys: BTN0"},
117 {BTN_1, GPIO_PF3, 1, "gpio-keys: BTN1"},
118 {BTN_2, GPIO_PF4, 1, "gpio-keys: BTN2"},
119 {BTN_3, GPIO_PF5, 1, "gpio-keys: BTN3"},
120};
121
122static struct gpio_keys_platform_data bfin_gpio_keys_data = {
123 .buttons = bfin_gpio_keys_table,
124 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
125};
126
127static struct platform_device bfin_device_gpiokeys = {
128 .name = "gpio-keys",
129 .dev = {
130 .platform_data = &bfin_gpio_keys_data,
131 },
132};
133#endif
134
cad2ab65
MF		 135static struct resource bfin_gpios_resources = {
136 .start = 0,
137 .end = MAX_BLACKFIN_GPIOS - 1,
138 .flags = IORESOURCE_IRQ,
139};
140
141static struct platform_device bfin_gpios_device = {
142 .name = "simple-gpio",
143 .id = -1,
144 .num_resources = 1,
145 .resource = &bfin_gpios_resources,
146};
147
1394f032
BW		 148#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
149static struct resource bfin_pcmcia_cf_resources[] = {
150 {
151 .start = 0x20310000, /* IO PORT */
152 .end = 0x20312000,
153 .flags = IORESOURCE_MEM,
1f83b8f1 154 }, {
d2d50aa9 155 .start = 0x20311000, /* Attribute Memory */
1394f032
BW		 156 .end = 0x20311FFF,
157 .flags = IORESOURCE_MEM,
1f83b8f1 158 }, {
1394f032
BW		 159 .start = IRQ_PF4,
160 .end = IRQ_PF4,
161 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
1f83b8f1 162 }, {
1394f032
BW		 163 .start = 6, /* Card Detect PF6 */
164 .end = 6,
165 .flags = IORESOURCE_IRQ,
166 },
167};
168
169static struct platform_device bfin_pcmcia_cf_device = {
170 .name = "bfin_cf_pcmcia",
171 .id = -1,
172 .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
173 .resource = bfin_pcmcia_cf_resources,
174};
175#endif
176
177#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
178static struct platform_device rtc_device = {
179 .name = "rtc-bfin",
180 .id = -1,
181};
182#endif
183
184#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
185static struct resource smc91x_resources[] = {
186 {
187 .name = "smc91x-regs",
188 .start = 0x20300300,
189 .end = 0x20300300 + 16,
190 .flags = IORESOURCE_MEM,
1f83b8f1 191 }, {
1394f032
BW		 192
193 .start = IRQ_PF7,
194 .end = IRQ_PF7,
195 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
196 },
197};
198static struct platform_device smc91x_device = {
199 .name = "smc91x",
200 .id = 0,
201 .num_resources = ARRAY_SIZE(smc91x_resources),
202 .resource = smc91x_resources,
203};
204#endif
205
f40d24d9
AL		 206#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
207static struct resource dm9000_resources[] = {
208 [0] = {
209 .start = 0x203FB800,
210 .end = 0x203FB800 + 8,
211 .flags = IORESOURCE_MEM,
212 },
213 [1] = {
214 .start = IRQ_PF9,
215 .end = IRQ_PF9,
216 .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
217 },
218};
219
220static struct platform_device dm9000_device = {
221 .name = "dm9000",
222 .id = -1,
223 .num_resources = ARRAY_SIZE(dm9000_resources),
224 .resource = dm9000_resources,
225};
226#endif
227
561cc18b
MH		 228#if defined(CONFIG_AX88180) || defined(CONFIG_AX88180_MODULE)
229static struct resource ax88180_resources[] = {
230 [0] = {
231 .start = 0x20300000,
232 .end = 0x20300000 + 0x8000,
233 .flags = IORESOURCE_MEM,
234 },
235 [1] = {
236 .start = IRQ_PF7,
237 .end = IRQ_PF7,
238 .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL),
239 },
240};
241
242static struct platform_device ax88180_device = {
243 .name = "ax88180",
244 .id = -1,
245 .num_resources = ARRAY_SIZE(ax88180_resources),
246 .resource = ax88180_resources,
247};
248#endif
249
1394f032
BW		 250#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
251static struct resource sl811_hcd_resources[] = {
252 {
253 .start = 0x20340000,
254 .end = 0x20340000,
255 .flags = IORESOURCE_MEM,
1f83b8f1 256 }, {
1394f032
BW		 257 .start = 0x20340004,
258 .end = 0x20340004,
259 .flags = IORESOURCE_MEM,
1f83b8f1 260 }, {
1394f032
BW		 261 .start = CONFIG_USB_SL811_BFIN_IRQ,
262 .end = CONFIG_USB_SL811_BFIN_IRQ,
263 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
264 },
265};
266
267#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
268void sl811_port_power(struct device *dev, int is_on)
269{
c6c4d7bb 270 gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS");
acbcd263 271 gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS, is_on);
1394f032
BW		 272}
273#endif
274
275static struct sl811_platform_data sl811_priv = {
276 .potpg = 10,
277 .power = 250, /* == 500mA */
278#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
279 .port_power = &sl811_port_power,
280#endif
281};
282
283static struct platform_device sl811_hcd_device = {
284 .name = "sl811-hcd",
285 .id = 0,
286 .dev = {
287 .platform_data = &sl811_priv,
288 },
289 .num_resources = ARRAY_SIZE(sl811_hcd_resources),
290 .resource = sl811_hcd_resources,
291};
292#endif
293
294#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
295static struct resource isp1362_hcd_resources[] = {
296 {
297 .start = 0x20360000,
298 .end = 0x20360000,
299 .flags = IORESOURCE_MEM,
1f83b8f1 300 }, {
1394f032
BW		 301 .start = 0x20360004,
302 .end = 0x20360004,
303 .flags = IORESOURCE_MEM,
1f83b8f1 304 }, {
1394f032
BW		 305 .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
306 .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
307 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
308 },
309};
310
311static struct isp1362_platform_data isp1362_priv = {
312 .sel15Kres = 1,
313 .clknotstop = 0,
314 .oc_enable = 0,
315 .int_act_high = 0,
316 .int_edge_triggered = 0,
317 .remote_wakeup_connected = 0,
318 .no_power_switching = 1,
319 .power_switching_mode = 0,
320};
321
322static struct platform_device isp1362_hcd_device = {
323 .name = "isp1362-hcd",
324 .id = 0,
325 .dev = {
326 .platform_data = &isp1362_priv,
327 },
328 .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
329 .resource = isp1362_hcd_resources,
330};
331#endif
332
333#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
334static struct platform_device bfin_mac_device = {
335 .name = "bfin_mac",
336};
337#endif
338
339#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
340static struct resource net2272_bfin_resources[] = {
341 {
342 .start = 0x20300000,
343 .end = 0x20300000 + 0x100,
344 .flags = IORESOURCE_MEM,
1f83b8f1 345 }, {
1394f032
BW		 346 .start = IRQ_PF7,
347 .end = IRQ_PF7,
348 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
349 },
350};
351
352static struct platform_device net2272_bfin_device = {
353 .name = "net2272",
354 .id = -1,
355 .num_resources = ARRAY_SIZE(net2272_bfin_resources),
356 .resource = net2272_bfin_resources,
357};
358#endif
359
fc68911e
MF		 360#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
361#ifdef CONFIG_MTD_PARTITIONS
362const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL };
363
364static struct mtd_partition bfin_plat_nand_partitions[] = {
365 {
aa582977 366 .name = "linux kernel(nand)",
fc68911e
MF		 367 .size = 0x400000,
368 .offset = 0,
369 }, {
aa582977 370 .name = "file system(nand)",
fc68911e
MF		 371 .size = MTDPART_SIZ_FULL,
372 .offset = MTDPART_OFS_APPEND,
373 },
374};
375#endif
376
377#define BFIN_NAND_PLAT_CLE 2
378#define BFIN_NAND_PLAT_ALE 1
379static void bfin_plat_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
380{
381 struct nand_chip *this = mtd->priv;
382
383 if (cmd == NAND_CMD_NONE)
384 return;
385
386 if (ctrl & NAND_CLE)
387 writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_CLE));
388 else
389 writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_ALE));
390}
391
392#define BFIN_NAND_PLAT_READY GPIO_PF3
393static int bfin_plat_nand_dev_ready(struct mtd_info *mtd)
394{
395 return gpio_get_value(BFIN_NAND_PLAT_READY);
396}
397
398static struct platform_nand_data bfin_plat_nand_data = {
399 .chip = {
400 .chip_delay = 30,
401#ifdef CONFIG_MTD_PARTITIONS
402 .part_probe_types = part_probes,
403 .partitions = bfin_plat_nand_partitions,
404 .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions),
405#endif
406 },
407 .ctrl = {
408 .cmd_ctrl = bfin_plat_nand_cmd_ctrl,
409 .dev_ready = bfin_plat_nand_dev_ready,
410 },
411};
412
413#define MAX(x, y) (x > y ? x : y)
414static struct resource bfin_plat_nand_resources = {
415 .start = 0x20212000,
416 .end = 0x20212000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)),
417 .flags = IORESOURCE_IO,
418};
419
420static struct platform_device bfin_async_nand_device = {
421 .name = "gen_nand",
422 .id = -1,
423 .num_resources = 1,
424 .resource = &bfin_plat_nand_resources,
425 .dev = {
426 .platform_data = &bfin_plat_nand_data,
427 },
428};
429
430static void bfin_plat_nand_init(void)
431{
432 gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat");
433}
434#else
435static void bfin_plat_nand_init(void) {}
436#endif
437
793dc27b 438#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
de8c43f2
MF		 439static struct mtd_partition stamp_partitions[] = {
440 {
aa582977 441 .name = "bootloader(nor)",
edf05641 442 .size = 0x40000,
de8c43f2
MF		 443 .offset = 0,
444 }, {
aa582977 445 .name = "linux kernel(nor)",
de8c43f2
MF		 446 .size = 0xE0000,
447 .offset = MTDPART_OFS_APPEND,
448 }, {
aa582977 449 .name = "file system(nor)",
edf05641 450 .size = 0x400000 - 0x40000 - 0xE0000 - 0x10000,
de8c43f2
MF		 451 .offset = MTDPART_OFS_APPEND,
452 }, {
aa582977 453 .name = "MAC Address(nor)",
de8c43f2
MF		 454 .size = MTDPART_SIZ_FULL,
455 .offset = 0x3F0000,
456 .mask_flags = MTD_WRITEABLE,
457 }
458};
459
460static struct physmap_flash_data stamp_flash_data = {
461 .width = 2,
462 .parts = stamp_partitions,
463 .nr_parts = ARRAY_SIZE(stamp_partitions),
464};
465
466static struct resource stamp_flash_resource = {
467 .start = 0x20000000,
468 .end = 0x203fffff,
469 .flags = IORESOURCE_MEM,
470};
471
472static struct platform_device stamp_flash_device = {
473 .name = "physmap-flash",
474 .id = 0,
475 .dev = {
476 .platform_data = &stamp_flash_data,
477 },
478 .num_resources = 1,
479 .resource = &stamp_flash_resource,
480};
793dc27b 481#endif
de8c43f2 482
1394f032
BW		 483#if defined(CONFIG_MTD_M25P80) \
484 || defined(CONFIG_MTD_M25P80_MODULE)
485static struct mtd_partition bfin_spi_flash_partitions[] = {
486 {
aa582977 487 .name = "bootloader(spi)",
edf05641 488 .size = 0x00040000,
1394f032
BW		 489 .offset = 0,
490 .mask_flags = MTD_CAP_ROM
1f83b8f1 491 }, {
aa582977 492 .name = "linux kernel(spi)",
1394f032 493 .size = 0xe0000,
edf05641 494 .offset = MTDPART_OFS_APPEND,
1f83b8f1 495 }, {
aa582977 496 .name = "file system(spi)",
edf05641
MF		 497 .size = MTDPART_SIZ_FULL,
498 .offset = MTDPART_OFS_APPEND,
1394f032
BW		 499 }
500};
501
502static struct flash_platform_data bfin_spi_flash_data = {
503 .name = "m25p80",
504 .parts = bfin_spi_flash_partitions,
505 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
506 .type = "m25p64",
507};
508
509/* SPI flash chip (m25p64) */
510static struct bfin5xx_spi_chip spi_flash_chip_info = {
511 .enable_dma = 0, /* use dma transfer with this chip*/
512 .bits_per_word = 8,
513};
514#endif
515
516#if defined(CONFIG_SPI_ADC_BF533) \
517 || defined(CONFIG_SPI_ADC_BF533_MODULE)
518/* SPI ADC chip */
519static struct bfin5xx_spi_chip spi_adc_chip_info = {
520 .enable_dma = 1, /* use dma transfer with this chip*/
521 .bits_per_word = 16,
522};
523#endif
524
525#if defined(CONFIG_SND_BLACKFIN_AD1836) \
526 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
527static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
528 .enable_dma = 0,
529 .bits_per_word = 16,
530};
531#endif
532
533#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
534static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
535 .enable_dma = 0,
536 .bits_per_word = 16,
537};
538#endif
539
540#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
541static struct bfin5xx_spi_chip spi_mmc_chip_info = {
542 .enable_dma = 1,
543 .bits_per_word = 8,
544};
545#endif
546
547#if defined(CONFIG_PBX)
548static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
549 .ctl_reg = 0x4, /* send zero */
550 .enable_dma = 0,
551 .bits_per_word = 8,
552 .cs_change_per_word = 1,
553};
554#endif
555
1394f032 556#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
46aa04f9 557#include <linux/spi/ad7877.h>
1394f032 558static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
1394f032
BW		 559 .enable_dma = 0,
560 .bits_per_word = 16,
561};
562
563static const struct ad7877_platform_data bfin_ad7877_ts_info = {
564 .model = 7877,
565 .vref_delay_usecs = 50, /* internal, no capacitor */
566 .x_plate_ohms = 419,
567 .y_plate_ohms = 486,
568 .pressure_max = 1000,
569 .pressure_min = 0,
570 .stopacq_polarity = 1,
571 .first_conversion_delay = 3,
572 .acquisition_time = 1,
573 .averaging = 1,
574 .pen_down_acc_interval = 1,
575};
576#endif
577
46aa04f9
MH		 578#if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
579#include <linux/spi/ad7879.h>
580static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
581 .enable_dma = 0,
582 .bits_per_word = 16,
583};
584
585static const struct ad7879_platform_data bfin_ad7879_ts_info = {
586 .model = 7879, /* Model = AD7879 */
587 .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
588 .pressure_max = 10000,
589 .pressure_min = 0,
590 .first_conversion_delay = 3, /* wait 512us before do a first conversion */
591 .acquisition_time = 1, /* 4us acquisition time per sample */
592 .median = 2, /* do 8 measurements */
593 .averaging = 1, /* take the average of 4 middle samples */
594 .pen_down_acc_interval = 255, /* 9.4 ms */
595 .gpio_output = 1, /* configure AUX/VBAT/GPIO as GPIO output */
596 .gpio_default = 1, /* During initialization set GPIO = HIGH */
597};
598#endif
599
6e668936
MH		 600#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
601static struct bfin5xx_spi_chip spidev_chip_info = {
602 .enable_dma = 0,
603 .bits_per_word = 8,
604};
605#endif
606
2043f3f7
MH		 607#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
608static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
609 .enable_dma = 0,
610 .bits_per_word = 8,
611};
612#endif
613
8e9d5c7d
MH		 614#if defined(CONFIG_MTD_DATAFLASH) \
615 || defined(CONFIG_MTD_DATAFLASH_MODULE)
ceac2651
MH		 616
617static struct mtd_partition bfin_spi_dataflash_partitions[] = {
618 {
619 .name = "bootloader(spi)",
620 .size = 0x00040000,
621 .offset = 0,
622 .mask_flags = MTD_CAP_ROM
623 }, {
624 .name = "linux kernel(spi)",
625 .size = 0xe0000,
626 .offset = MTDPART_OFS_APPEND,
627 }, {
628 .name = "file system(spi)",
629 .size = MTDPART_SIZ_FULL,
630 .offset = MTDPART_OFS_APPEND,
631 }
632};
633
634static struct flash_platform_data bfin_spi_dataflash_data = {
635 .name = "SPI Dataflash",
636 .parts = bfin_spi_dataflash_partitions,
637 .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
638};
639
8e9d5c7d
MH		 640/* DataFlash chip */
641static struct bfin5xx_spi_chip data_flash_chip_info = {
642 .enable_dma = 0, /* use dma transfer with this chip*/
643 .bits_per_word = 8,
644};
645#endif
646
1394f032
BW		 647static struct spi_board_info bfin_spi_board_info[] __initdata = {
648#if defined(CONFIG_MTD_M25P80) \
649 || defined(CONFIG_MTD_M25P80_MODULE)
650 {
651 /* the modalias must be the same as spi device driver name */
652 .modalias = "m25p80", /* Name of spi_driver for this device */
653 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 654 .bus_num = 0, /* Framework bus number */
1394f032
BW		 655 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
656 .platform_data = &bfin_spi_flash_data,
657 .controller_data = &spi_flash_chip_info,
658 .mode = SPI_MODE_3,
659 },
660#endif
8e9d5c7d
MH		 661#if defined(CONFIG_MTD_DATAFLASH) \
662 || defined(CONFIG_MTD_DATAFLASH_MODULE)
663 { /* DataFlash chip */
664 .modalias = "mtd_dataflash",
ceac2651 665 .max_speed_hz = 33250000, /* max spi clock (SCK) speed in HZ */
8e9d5c7d
MH		 666 .bus_num = 0, /* Framework bus number */
667 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
ceac2651 668 .platform_data = &bfin_spi_dataflash_data,
8e9d5c7d
MH		 669 .controller_data = &data_flash_chip_info,
670 .mode = SPI_MODE_3,
671 },
672#endif
1394f032
BW		 673#if defined(CONFIG_SPI_ADC_BF533) \
674 || defined(CONFIG_SPI_ADC_BF533_MODULE)
675 {
676 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
677 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 678 .bus_num = 0, /* Framework bus number */
1394f032
BW		 679 .chip_select = 1, /* Framework chip select. */
680 .platform_data = NULL, /* No spi_driver specific config */
681 .controller_data = &spi_adc_chip_info,
682 },
683#endif
684
685#if defined(CONFIG_SND_BLACKFIN_AD1836) \
686 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
687 {
688 .modalias = "ad1836-spi",
689 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 690 .bus_num = 0,
1394f032
BW		 691 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
692 .controller_data = &ad1836_spi_chip_info,
693 },
694#endif
695#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
696 {
697 .modalias = "ad9960-spi",
698 .max_speed_hz = 10000000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 699 .bus_num = 0,
1394f032
BW		 700 .chip_select = 1,
701 .controller_data = &ad9960_spi_chip_info,
702 },
703#endif
704#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
705 {
706 .modalias = "spi_mmc_dummy",
111cf97d 707 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 708 .bus_num = 0,
1394f032
BW		 709 .chip_select = 0,
710 .platform_data = NULL,
711 .controller_data = &spi_mmc_chip_info,
712 .mode = SPI_MODE_3,
713 },
714 {
715 .modalias = "spi_mmc",
111cf97d 716 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 717 .bus_num = 0,
1394f032
BW		 718 .chip_select = CONFIG_SPI_MMC_CS_CHAN,
719 .platform_data = NULL,
720 .controller_data = &spi_mmc_chip_info,
721 .mode = SPI_MODE_3,
722 },
723#endif
724#if defined(CONFIG_PBX)
725 {
1f83b8f1
MF		 726 .modalias = "fxs-spi",
727 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb
BW		 728 .bus_num = 0,
729 .chip_select = 8 - CONFIG_J11_JUMPER,
1f83b8f1 730 .controller_data = &spi_si3xxx_chip_info,
1394f032
BW		 731 .mode = SPI_MODE_3,
732 },
733 {
1f83b8f1
MF		 734 .modalias = "fxo-spi",
735 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb
BW		 736 .bus_num = 0,
737 .chip_select = 8 - CONFIG_J19_JUMPER,
1f83b8f1 738 .controller_data = &spi_si3xxx_chip_info,
1394f032
BW		 739 .mode = SPI_MODE_3,
740 },
741#endif
1394f032
BW		 742#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
743 {
744 .modalias = "ad7877",
745 .platform_data = &bfin_ad7877_ts_info,
746 .irq = IRQ_PF6,
747 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
c7d48966 748 .bus_num = 0,
1394f032
BW		 749 .chip_select = 1,
750 .controller_data = &spi_ad7877_chip_info,
751 },
752#endif
46aa04f9
MH		 753#if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
754 {
755 .modalias = "ad7879",
756 .platform_data = &bfin_ad7879_ts_info,
757 .irq = IRQ_PF7,
758 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
759 .bus_num = 0,
760 .chip_select = 1,
761 .controller_data = &spi_ad7879_chip_info,
762 .mode = SPI_CPHA | SPI_CPOL,
763 },
764#endif
6e668936
MH		 765#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
766 {
767 .modalias = "spidev",
768 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
769 .bus_num = 0,
770 .chip_select = 1,
771 .controller_data = &spidev_chip_info,
772 },
773#endif
2043f3f7
MH		 774#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
775 {
776 .modalias = "bfin-lq035q1-spi",
777 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
778 .bus_num = 0,
46aa04f9 779 .chip_select = 2,
2043f3f7
MH		 780 .controller_data = &lq035q1_spi_chip_info,
781 .mode = SPI_CPHA | SPI_CPOL,
782 },
783#endif
1394f032
BW		 784};
785
5bda2723 786#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
1394f032 787/* SPI controller data */
c6c4d7bb 788static struct bfin5xx_spi_master bfin_spi0_info = {
1394f032
BW		 789 .num_chipselect = 8,
790 .enable_dma = 1, /* master has the ability to do dma transfer */
5d448dd5 791 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1394f032
BW		 792};
793
c6c4d7bb
BW		 794/* SPI (0) */
795static struct resource bfin_spi0_resource[] = {
796 [0] = {
797 .start = SPI0_REGBASE,
798 .end = SPI0_REGBASE + 0xFF,
799 .flags = IORESOURCE_MEM,
800 },
801 [1] = {
802 .start = CH_SPI,
803 .end = CH_SPI,
804 .flags = IORESOURCE_IRQ,
805 },
806};
807
808static struct platform_device bfin_spi0_device = {
809 .name = "bfin-spi",
810 .id = 0, /* Bus number */
811 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
812 .resource = bfin_spi0_resource,
1394f032 813 .dev = {
c6c4d7bb 814 .platform_data = &bfin_spi0_info, /* Passed to driver */
1394f032
BW		 815 },
816};
817#endif /* spi master and devices */
818
819#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
820static struct platform_device bfin_fb_device = {
c6c4d7bb
BW		 821 .name = "bf537-lq035",
822};
823#endif
824
825#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
826static struct platform_device bfin_fb_adv7393_device = {
827 .name = "bfin-adv7393",
1394f032
BW		 828};
829#endif
830
2043f3f7
MH		 831#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
832#include <asm/bfin-lq035q1.h>
833
834static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
835 .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
46aa04f9 836 .use_bl = 0, /* let something else control the LCD Blacklight */
2043f3f7
MH		 837 .gpio_bl = GPIO_PF7,
838};
839
840static struct resource bfin_lq035q1_resources[] = {
841 {
842 .start = IRQ_PPI_ERROR,
843 .end = IRQ_PPI_ERROR,
844 .flags = IORESOURCE_IRQ,
845 },
846};
847
848static struct platform_device bfin_lq035q1_device = {
849 .name = "bfin-lq035q1",
850 .id = -1,
851 .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
852 .resource = bfin_lq035q1_resources,
853 .dev = {
854 .platform_data = &bfin_lq035q1_data,
855 },
856};
857#endif
858
1394f032
BW		 859#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
860static struct resource bfin_uart_resources[] = {
233b28a9 861#ifdef CONFIG_SERIAL_BFIN_UART0
1394f032
BW		 862 {
863 .start = 0xFFC00400,
864 .end = 0xFFC004FF,
865 .flags = IORESOURCE_MEM,
233b28a9
SZ		 866 },
867#endif
868#ifdef CONFIG_SERIAL_BFIN_UART1
869 {
1394f032
BW		 870 .start = 0xFFC02000,
871 .end = 0xFFC020FF,
872 .flags = IORESOURCE_MEM,
873 },
233b28a9 874#endif
1394f032
BW		 875};
876
877static struct platform_device bfin_uart_device = {
878 .name = "bfin-uart",
879 .id = 1,
880 .num_resources = ARRAY_SIZE(bfin_uart_resources),
881 .resource = bfin_uart_resources,
882};
883#endif
884
5be36d22
GY		 885#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
886static struct resource bfin_sir_resources[] = {
887#ifdef CONFIG_BFIN_SIR0
888 {
889 .start = 0xFFC00400,
890 .end = 0xFFC004FF,
891 .flags = IORESOURCE_MEM,
892 },
893#endif
894#ifdef CONFIG_BFIN_SIR1
895 {
896 .start = 0xFFC02000,
897 .end = 0xFFC020FF,
898 .flags = IORESOURCE_MEM,
899 },
900#endif
901};
902
903static struct platform_device bfin_sir_device = {
904 .name = "bfin_sir",
905 .id = 0,
906 .num_resources = ARRAY_SIZE(bfin_sir_resources),
907 .resource = bfin_sir_resources,
908};
909#endif
910
1394f032 911#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
c6c4d7bb
BW		 912static struct resource bfin_twi0_resource[] = {
913 [0] = {
914 .start = TWI0_REGBASE,
915 .end = TWI0_REGBASE,
916 .flags = IORESOURCE_MEM,
917 },
918 [1] = {
919 .start = IRQ_TWI,
920 .end = IRQ_TWI,
921 .flags = IORESOURCE_IRQ,
922 },
923};
924
1394f032
BW		 925static struct platform_device i2c_bfin_twi_device = {
926 .name = "i2c-bfin-twi",
927 .id = 0,
c6c4d7bb
BW		 928 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
929 .resource = bfin_twi0_resource,
1394f032
BW		 930};
931#endif
932
81d9c7f2
BW		 933#ifdef CONFIG_I2C_BOARDINFO
934static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
935#if defined(CONFIG_JOYSTICK_AD7142) || defined(CONFIG_JOYSTICK_AD7142_MODULE)
936 {
937 I2C_BOARD_INFO("ad7142_joystick", 0x2C),
81d9c7f2
BW		 938 .irq = 55,
939 },
940#endif
941#if defined(CONFIG_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE)
942 {
943 I2C_BOARD_INFO("pcf8574_lcd", 0x22),
81d9c7f2
BW		 944 },
945#endif
946#if defined(CONFIG_TWI_KEYPAD) || defined(CONFIG_TWI_KEYPAD_MODULE)
947 {
948 I2C_BOARD_INFO("pcf8574_keypad", 0x27),
81d9c7f2
BW		 949 .irq = 72,
950 },
951#endif
952};
953#endif
954
1394f032
BW		 955#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
956static struct platform_device bfin_sport0_uart_device = {
957 .name = "bfin-sport-uart",
958 .id = 0,
959};
960
961static struct platform_device bfin_sport1_uart_device = {
962 .name = "bfin-sport-uart",
963 .id = 1,
964};
965#endif
966
c6c4d7bb 967#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
96b86e94 968#define PATA_INT IRQ_PF5
c6c4d7bb
BW		 969
970static struct pata_platform_info bfin_pata_platform_data = {
971 .ioport_shift = 1,
64e5c512 972 .irq_flags = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
c6c4d7bb
BW		 973};
974
975static struct resource bfin_pata_resources[] = {
976 {
977 .start = 0x20314020,
978 .end = 0x2031403F,
979 .flags = IORESOURCE_MEM,
980 },
981 {
982 .start = 0x2031401C,
983 .end = 0x2031401F,
984 .flags = IORESOURCE_MEM,
985 },
986 {
987 .start = PATA_INT,
988 .end = PATA_INT,
989 .flags = IORESOURCE_IRQ,
990 },
991};
992
993static struct platform_device bfin_pata_device = {
994 .name = "pata_platform",
995 .id = -1,
996 .num_resources = ARRAY_SIZE(bfin_pata_resources),
997 .resource = bfin_pata_resources,
998 .dev = {
999 .platform_data = &bfin_pata_platform_data,
1000 }
1001};
1002#endif
1003
14b03204
MH		 1004static const unsigned int cclk_vlev_datasheet[] =
1005{
1006 VRPAIR(VLEV_085, 250000000),
1007 VRPAIR(VLEV_090, 376000000),
1008 VRPAIR(VLEV_095, 426000000),
1009 VRPAIR(VLEV_100, 426000000),
1010 VRPAIR(VLEV_105, 476000000),
1011 VRPAIR(VLEV_110, 476000000),
1012 VRPAIR(VLEV_115, 476000000),
1013 VRPAIR(VLEV_120, 500000000),
1014 VRPAIR(VLEV_125, 533000000),
1015 VRPAIR(VLEV_130, 600000000),
1016};
1017
1018static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
1019 .tuple_tab = cclk_vlev_datasheet,
1020 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
1021 .vr_settling_time = 25 /* us */,
1022};
1023
1024static struct platform_device bfin_dpmc = {
1025 .name = "bfin dpmc",
1026 .dev = {
1027 .platform_data = &bfin_dmpc_vreg_data,
1028 },
1029};
1030
1394f032 1031static struct platform_device *stamp_devices[] __initdata = {
14b03204
MH		 1032
1033 &bfin_dpmc,
1034
1394f032
BW		 1035#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
1036 &bfin_pcmcia_cf_device,
1037#endif
1038
1039#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
1040 &rtc_device,
1041#endif
1042
1043#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
1044 &sl811_hcd_device,
1045#endif
1046
1047#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
1048 &isp1362_hcd_device,
1049#endif
1050
1051#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
1052 &smc91x_device,
1053#endif
1054
f40d24d9
AL		 1055#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
1056 &dm9000_device,
1057#endif
1058
561cc18b
MH		 1059#if defined(CONFIG_AX88180) || defined(CONFIG_AX88180_MODULE)
1060 &ax88180_device,
1061#endif
1062
1394f032
BW		 1063#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1064 &bfin_mac_device,
1065#endif
1066
1067#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
1068 &net2272_bfin_device,
1069#endif
1070
1071#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
c6c4d7bb 1072 &bfin_spi0_device,
1394f032
BW		 1073#endif
1074
1075#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
1076 &bfin_fb_device,
1077#endif
1078
2043f3f7
MH		 1079#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
1080 &bfin_lq035q1_device,
1081#endif
1082
c6c4d7bb
BW		 1083#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
1084 &bfin_fb_adv7393_device,
1085#endif
1086
1394f032
BW		 1087#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
1088 &bfin_uart_device,
1089#endif
1090
5be36d22
GY		 1091#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
1092 &bfin_sir_device,
1093#endif
1094
1394f032
BW		 1095#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
1096 &i2c_bfin_twi_device,
1097#endif
1098
1099#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
1100 &bfin_sport0_uart_device,
1101 &bfin_sport1_uart_device,
1102#endif
c6c4d7bb
BW		 1103
1104#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
1105 &bfin_pata_device,
1106#endif
2463ef22
MH		 1107
1108#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
1109 &bfin_device_gpiokeys,
1110#endif
cad2ab65
MF		 1111
1112 &bfin_gpios_device,
793dc27b 1113
fc68911e
MF		 1114#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
1115 &bfin_async_nand_device,
1116#endif
1117
793dc27b 1118#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
de8c43f2 1119 &stamp_flash_device,
793dc27b 1120#endif
1394f032
BW		 1121};
1122
1123static int __init stamp_init(void)
1124{
b85d858b 1125 printk(KERN_INFO "%s(): registering device resources\n", __func__);
81d9c7f2
BW		 1126
1127#ifdef CONFIG_I2C_BOARDINFO
1128 i2c_register_board_info(0, bfin_i2c_board_info,
1129 ARRAY_SIZE(bfin_i2c_board_info));
1130#endif
1131
fc68911e 1132 bfin_plat_nand_init();
1394f032 1133 platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
5bda2723 1134 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
c6c4d7bb
BW		 1135
1136#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
1137 irq_desc[PATA_INT].status |= IRQ_NOAUTOEN;
1138#endif
81d9c7f2 1139
1394f032
BW		 1140 return 0;
1141}
1142
1143arch_initcall(stamp_init);
c6c4d7bb
BW		 1144
1145void native_machine_restart(char *cmd)
1146{
1147 /* workaround reboot hang when booting from SPI */
1148 if ((bfin_read_SYSCR() & 0x7) == 0x3)
1149 bfin_gpio_reset_spi0_ssel1();
1150}
137b1529
MF		 1151
1152/*
1153 * Currently the MAC address is saved in Flash by U-Boot
1154 */
1155#define FLASH_MAC 0x203f0000
9862cc52 1156void bfin_get_ether_addr(char *addr)
137b1529
MF		 1157{
1158 *(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC);
1159 *(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4);
1160}
9862cc52 1161EXPORT_SYMBOL(bfin_get_ether_addr);
kernel source for telekom puls (alcatel/mediatek)