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Blackfin arch: clean up sports header file
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / blackfin / mach-bf537 / boards / stamp.c
CommitLineData
1394f032
BW		 1/*
2 * File: arch/blackfin/mach-bf537/boards/stamp.c
3 * Based on: arch/blackfin/mach-bf533/boards/ezkit.c
4 * Author: Aidan Williams <aidan@nicta.com.au>
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2005 National ICT Australia (NICTA)
11 * Copyright 2004-2006 Analog Devices Inc.
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see the file COPYING, or write
27 * to the Free Software Foundation, Inc.,
28 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 */
30
31#include <linux/device.h>
fc68911e 32#include <linux/kernel.h>
1394f032
BW		 33#include <linux/platform_device.h>
34#include <linux/mtd/mtd.h>
fc68911e 35#include <linux/mtd/nand.h>
1394f032 36#include <linux/mtd/partitions.h>
fc68911e 37#include <linux/mtd/plat-ram.h>
de8c43f2 38#include <linux/mtd/physmap.h>
1394f032
BW		 39#include <linux/spi/spi.h>
40#include <linux/spi/flash.h>
41#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
f02bcec5 42#include <linux/usb/isp1362.h>
1394f032 43#endif
0a87e3e9 44#include <linux/ata_platform.h>
1394f032
BW		 45#include <linux/irq.h>
46#include <linux/interrupt.h>
81d9c7f2 47#include <linux/i2c.h>
27f5d75a 48#include <linux/usb/sl811.h>
f79ea4cb 49#include <linux/spi/mmc_spi.h>
c6c4d7bb 50#include <asm/dma.h>
1f83b8f1 51#include <asm/bfin5xx_spi.h>
c6c4d7bb 52#include <asm/reboot.h>
5d448dd5 53#include <asm/portmux.h>
14b03204 54#include <asm/dpmc.h>
1394f032
BW		 55
56/*
57 * Name the Board for the /proc/cpuinfo
58 */
fe85cad2 59const char bfin_board_name[] = "ADI BF537-STAMP";
1394f032
BW		 60
61/*
62 * Driver needs to know address, irq and flag pin.
63 */
64
1394f032 65#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
3f375690
MH		 66#include <linux/usb/isp1760.h>
67static struct resource bfin_isp1760_resources[] = {
1394f032 68 [0] = {
3f375690
MH		 69 .start = 0x203C0000,
70 .end = 0x203C0000 + 0x000fffff,
1394f032
BW		 71 .flags = IORESOURCE_MEM,
72 },
73 [1] = {
3f375690
MH		 74 .start = IRQ_PF7,
75 .end = IRQ_PF7,
6a6be3d1 76 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
1394f032
BW		 77 },
78};
79
3f375690
MH		 80static struct isp1760_platform_data isp1760_priv = {
81 .is_isp1761 = 0,
82 .port1_disable = 0,
83 .bus_width_16 = 1,
84 .port1_otg = 0,
85 .analog_oc = 0,
86 .dack_polarity_high = 0,
87 .dreq_polarity_high = 0,
1394f032
BW		 88};
89
3f375690
MH		 90static struct platform_device bfin_isp1760_device = {
91 .name = "isp1760-hcd",
92 .id = 0,
93 .dev = {
94 .platform_data = &isp1760_priv,
95 },
96 .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
97 .resource = bfin_isp1760_resources,
1394f032 98};
1394f032
BW		 99#endif
100
2463ef22
MH		 101#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
102#include <linux/input.h>
103#include <linux/gpio_keys.h>
104
105static struct gpio_keys_button bfin_gpio_keys_table[] = {
106 {BTN_0, GPIO_PF2, 1, "gpio-keys: BTN0"},
107 {BTN_1, GPIO_PF3, 1, "gpio-keys: BTN1"},
108 {BTN_2, GPIO_PF4, 1, "gpio-keys: BTN2"},
109 {BTN_3, GPIO_PF5, 1, "gpio-keys: BTN3"},
110};
111
112static struct gpio_keys_platform_data bfin_gpio_keys_data = {
113 .buttons = bfin_gpio_keys_table,
114 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
115};
116
117static struct platform_device bfin_device_gpiokeys = {
118 .name = "gpio-keys",
119 .dev = {
120 .platform_data = &bfin_gpio_keys_data,
121 },
122};
123#endif
124
cad2ab65
MF		 125static struct resource bfin_gpios_resources = {
126 .start = 0,
127 .end = MAX_BLACKFIN_GPIOS - 1,
128 .flags = IORESOURCE_IRQ,
129};
130
131static struct platform_device bfin_gpios_device = {
132 .name = "simple-gpio",
133 .id = -1,
134 .num_resources = 1,
135 .resource = &bfin_gpios_resources,
136};
137
1394f032
BW		 138#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
139static struct resource bfin_pcmcia_cf_resources[] = {
140 {
141 .start = 0x20310000, /* IO PORT */
142 .end = 0x20312000,
143 .flags = IORESOURCE_MEM,
1f83b8f1 144 }, {
d2d50aa9 145 .start = 0x20311000, /* Attribute Memory */
1394f032
BW		 146 .end = 0x20311FFF,
147 .flags = IORESOURCE_MEM,
1f83b8f1 148 }, {
1394f032
BW		 149 .start = IRQ_PF4,
150 .end = IRQ_PF4,
151 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
1f83b8f1 152 }, {
1394f032
BW		 153 .start = 6, /* Card Detect PF6 */
154 .end = 6,
155 .flags = IORESOURCE_IRQ,
156 },
157};
158
159static struct platform_device bfin_pcmcia_cf_device = {
160 .name = "bfin_cf_pcmcia",
161 .id = -1,
162 .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
163 .resource = bfin_pcmcia_cf_resources,
164};
165#endif
166
167#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
168static struct platform_device rtc_device = {
169 .name = "rtc-bfin",
170 .id = -1,
171};
172#endif
173
174#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
175static struct resource smc91x_resources[] = {
176 {
177 .name = "smc91x-regs",
178 .start = 0x20300300,
179 .end = 0x20300300 + 16,
180 .flags = IORESOURCE_MEM,
1f83b8f1 181 }, {
1394f032
BW		 182
183 .start = IRQ_PF7,
184 .end = IRQ_PF7,
185 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
186 },
187};
188static struct platform_device smc91x_device = {
189 .name = "smc91x",
190 .id = 0,
191 .num_resources = ARRAY_SIZE(smc91x_resources),
192 .resource = smc91x_resources,
193};
194#endif
195
f40d24d9
AL		 196#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
197static struct resource dm9000_resources[] = {
198 [0] = {
199 .start = 0x203FB800,
200 .end = 0x203FB800 + 8,
201 .flags = IORESOURCE_MEM,
202 },
203 [1] = {
204 .start = IRQ_PF9,
205 .end = IRQ_PF9,
206 .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
207 },
208};
209
210static struct platform_device dm9000_device = {
211 .name = "dm9000",
212 .id = -1,
213 .num_resources = ARRAY_SIZE(dm9000_resources),
214 .resource = dm9000_resources,
215};
216#endif
217
561cc18b
MH		 218#if defined(CONFIG_AX88180) || defined(CONFIG_AX88180_MODULE)
219static struct resource ax88180_resources[] = {
220 [0] = {
221 .start = 0x20300000,
222 .end = 0x20300000 + 0x8000,
223 .flags = IORESOURCE_MEM,
224 },
225 [1] = {
226 .start = IRQ_PF7,
227 .end = IRQ_PF7,
228 .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL),
229 },
230};
231
232static struct platform_device ax88180_device = {
233 .name = "ax88180",
234 .id = -1,
235 .num_resources = ARRAY_SIZE(ax88180_resources),
236 .resource = ax88180_resources,
237};
238#endif
239
1394f032
BW		 240#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
241static struct resource sl811_hcd_resources[] = {
242 {
243 .start = 0x20340000,
244 .end = 0x20340000,
245 .flags = IORESOURCE_MEM,
1f83b8f1 246 }, {
1394f032
BW		 247 .start = 0x20340004,
248 .end = 0x20340004,
249 .flags = IORESOURCE_MEM,
1f83b8f1 250 }, {
1394f032
BW		 251 .start = CONFIG_USB_SL811_BFIN_IRQ,
252 .end = CONFIG_USB_SL811_BFIN_IRQ,
253 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
254 },
255};
256
257#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
258void sl811_port_power(struct device *dev, int is_on)
259{
c6c4d7bb 260 gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS");
acbcd263 261 gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS, is_on);
1394f032
BW		 262}
263#endif
264
265static struct sl811_platform_data sl811_priv = {
266 .potpg = 10,
267 .power = 250, /* == 500mA */
268#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
269 .port_power = &sl811_port_power,
270#endif
271};
272
273static struct platform_device sl811_hcd_device = {
274 .name = "sl811-hcd",
275 .id = 0,
276 .dev = {
277 .platform_data = &sl811_priv,
278 },
279 .num_resources = ARRAY_SIZE(sl811_hcd_resources),
280 .resource = sl811_hcd_resources,
281};
282#endif
283
284#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
285static struct resource isp1362_hcd_resources[] = {
286 {
287 .start = 0x20360000,
288 .end = 0x20360000,
289 .flags = IORESOURCE_MEM,
1f83b8f1 290 }, {
1394f032
BW		 291 .start = 0x20360004,
292 .end = 0x20360004,
293 .flags = IORESOURCE_MEM,
1f83b8f1 294 }, {
1394f032
BW		 295 .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
296 .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
297 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
298 },
299};
300
301static struct isp1362_platform_data isp1362_priv = {
302 .sel15Kres = 1,
303 .clknotstop = 0,
304 .oc_enable = 0,
305 .int_act_high = 0,
306 .int_edge_triggered = 0,
307 .remote_wakeup_connected = 0,
308 .no_power_switching = 1,
309 .power_switching_mode = 0,
310};
311
312static struct platform_device isp1362_hcd_device = {
313 .name = "isp1362-hcd",
314 .id = 0,
315 .dev = {
316 .platform_data = &isp1362_priv,
317 },
318 .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
319 .resource = isp1362_hcd_resources,
320};
321#endif
322
323#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
65319628
GY		 324static struct platform_device bfin_mii_bus = {
325 .name = "bfin_mii_bus",
326};
327
1394f032
BW		 328static struct platform_device bfin_mac_device = {
329 .name = "bfin_mac",
65319628 330 .dev.platform_data = &bfin_mii_bus,
1394f032
BW		 331};
332#endif
333
334#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
335static struct resource net2272_bfin_resources[] = {
336 {
337 .start = 0x20300000,
338 .end = 0x20300000 + 0x100,
339 .flags = IORESOURCE_MEM,
1f83b8f1 340 }, {
1394f032
BW		 341 .start = IRQ_PF7,
342 .end = IRQ_PF7,
343 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
344 },
345};
346
347static struct platform_device net2272_bfin_device = {
348 .name = "net2272",
349 .id = -1,
350 .num_resources = ARRAY_SIZE(net2272_bfin_resources),
351 .resource = net2272_bfin_resources,
352};
353#endif
354
fc68911e
MF		 355#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
356#ifdef CONFIG_MTD_PARTITIONS
357const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL };
358
359static struct mtd_partition bfin_plat_nand_partitions[] = {
360 {
aa582977 361 .name = "linux kernel(nand)",
fc68911e
MF		 362 .size = 0x400000,
363 .offset = 0,
364 }, {
aa582977 365 .name = "file system(nand)",
fc68911e
MF		 366 .size = MTDPART_SIZ_FULL,
367 .offset = MTDPART_OFS_APPEND,
368 },
369};
370#endif
371
372#define BFIN_NAND_PLAT_CLE 2
373#define BFIN_NAND_PLAT_ALE 1
374static void bfin_plat_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
375{
376 struct nand_chip *this = mtd->priv;
377
378 if (cmd == NAND_CMD_NONE)
379 return;
380
381 if (ctrl & NAND_CLE)
382 writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_CLE));
383 else
384 writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_ALE));
385}
386
387#define BFIN_NAND_PLAT_READY GPIO_PF3
388static int bfin_plat_nand_dev_ready(struct mtd_info *mtd)
389{
390 return gpio_get_value(BFIN_NAND_PLAT_READY);
391}
392
393static struct platform_nand_data bfin_plat_nand_data = {
394 .chip = {
395 .chip_delay = 30,
396#ifdef CONFIG_MTD_PARTITIONS
397 .part_probe_types = part_probes,
398 .partitions = bfin_plat_nand_partitions,
399 .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions),
400#endif
401 },
402 .ctrl = {
403 .cmd_ctrl = bfin_plat_nand_cmd_ctrl,
404 .dev_ready = bfin_plat_nand_dev_ready,
405 },
406};
407
408#define MAX(x, y) (x > y ? x : y)
409static struct resource bfin_plat_nand_resources = {
410 .start = 0x20212000,
411 .end = 0x20212000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)),
412 .flags = IORESOURCE_IO,
413};
414
415static struct platform_device bfin_async_nand_device = {
416 .name = "gen_nand",
417 .id = -1,
418 .num_resources = 1,
419 .resource = &bfin_plat_nand_resources,
420 .dev = {
421 .platform_data = &bfin_plat_nand_data,
422 },
423};
424
425static void bfin_plat_nand_init(void)
426{
427 gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat");
428}
429#else
430static void bfin_plat_nand_init(void) {}
431#endif
432
793dc27b 433#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
de8c43f2
MF		 434static struct mtd_partition stamp_partitions[] = {
435 {
aa582977 436 .name = "bootloader(nor)",
edf05641 437 .size = 0x40000,
de8c43f2
MF		 438 .offset = 0,
439 }, {
aa582977 440 .name = "linux kernel(nor)",
6ecb5b6d 441 .size = 0x180000,
de8c43f2
MF		 442 .offset = MTDPART_OFS_APPEND,
443 }, {
aa582977 444 .name = "file system(nor)",
6ecb5b6d 445 .size = 0x400000 - 0x40000 - 0x180000 - 0x10000,
de8c43f2
MF		 446 .offset = MTDPART_OFS_APPEND,
447 }, {
aa582977 448 .name = "MAC Address(nor)",
de8c43f2
MF		 449 .size = MTDPART_SIZ_FULL,
450 .offset = 0x3F0000,
451 .mask_flags = MTD_WRITEABLE,
452 }
453};
454
455static struct physmap_flash_data stamp_flash_data = {
456 .width = 2,
457 .parts = stamp_partitions,
458 .nr_parts = ARRAY_SIZE(stamp_partitions),
459};
460
461static struct resource stamp_flash_resource = {
462 .start = 0x20000000,
463 .end = 0x203fffff,
464 .flags = IORESOURCE_MEM,
465};
466
467static struct platform_device stamp_flash_device = {
468 .name = "physmap-flash",
469 .id = 0,
470 .dev = {
471 .platform_data = &stamp_flash_data,
472 },
473 .num_resources = 1,
474 .resource = &stamp_flash_resource,
475};
793dc27b 476#endif
de8c43f2 477
1394f032
BW		 478#if defined(CONFIG_MTD_M25P80) \
479 || defined(CONFIG_MTD_M25P80_MODULE)
480static struct mtd_partition bfin_spi_flash_partitions[] = {
481 {
aa582977 482 .name = "bootloader(spi)",
edf05641 483 .size = 0x00040000,
1394f032
BW		 484 .offset = 0,
485 .mask_flags = MTD_CAP_ROM
1f83b8f1 486 }, {
aa582977 487 .name = "linux kernel(spi)",
6ecb5b6d 488 .size = 0x180000,
edf05641 489 .offset = MTDPART_OFS_APPEND,
1f83b8f1 490 }, {
aa582977 491 .name = "file system(spi)",
edf05641
MF		 492 .size = MTDPART_SIZ_FULL,
493 .offset = MTDPART_OFS_APPEND,
1394f032
BW		 494 }
495};
496
497static struct flash_platform_data bfin_spi_flash_data = {
498 .name = "m25p80",
499 .parts = bfin_spi_flash_partitions,
500 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
88a8078b 501 /* .type = "m25p64", */
1394f032
BW		 502};
503
504/* SPI flash chip (m25p64) */
505static struct bfin5xx_spi_chip spi_flash_chip_info = {
506 .enable_dma = 0, /* use dma transfer with this chip*/
507 .bits_per_word = 8,
508};
509#endif
510
511#if defined(CONFIG_SPI_ADC_BF533) \
512 || defined(CONFIG_SPI_ADC_BF533_MODULE)
513/* SPI ADC chip */
514static struct bfin5xx_spi_chip spi_adc_chip_info = {
515 .enable_dma = 1, /* use dma transfer with this chip*/
516 .bits_per_word = 16,
517};
518#endif
519
520#if defined(CONFIG_SND_BLACKFIN_AD1836) \
521 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
522static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
523 .enable_dma = 0,
524 .bits_per_word = 16,
525};
526#endif
527
528#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
529static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
530 .enable_dma = 0,
531 .bits_per_word = 16,
532};
533#endif
534
f79ea4cb
YL		 535#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
536#define MMC_SPI_CARD_DETECT_INT IRQ_PF5
537
538static int bfin_mmc_spi_init(struct device *dev,
539 irqreturn_t (*detect_int)(int, void *), void *data)
540{
541 return request_irq(MMC_SPI_CARD_DETECT_INT, detect_int,
542 IRQF_TRIGGER_FALLING, "mmc-spi-detect", data);
543}
544
545static void bfin_mmc_spi_exit(struct device *dev, void *data)
546{
547 free_irq(MMC_SPI_CARD_DETECT_INT, data);
548}
549
550static struct mmc_spi_platform_data bfin_mmc_spi_pdata = {
551 .init = bfin_mmc_spi_init,
552 .exit = bfin_mmc_spi_exit,
553 .detect_delay = 100, /* msecs */
554};
555
556static struct bfin5xx_spi_chip mmc_spi_chip_info = {
557 .enable_dma = 0,
558 .bits_per_word = 8,
559};
560#endif
561
1394f032
BW		 562#if defined(CONFIG_PBX)
563static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
564 .ctl_reg = 0x4, /* send zero */
565 .enable_dma = 0,
566 .bits_per_word = 8,
567 .cs_change_per_word = 1,
568};
569#endif
570
1394f032 571#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
46aa04f9 572#include <linux/spi/ad7877.h>
1394f032 573static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
1394f032
BW		 574 .enable_dma = 0,
575 .bits_per_word = 16,
576};
577
578static const struct ad7877_platform_data bfin_ad7877_ts_info = {
579 .model = 7877,
580 .vref_delay_usecs = 50, /* internal, no capacitor */
581 .x_plate_ohms = 419,
582 .y_plate_ohms = 486,
583 .pressure_max = 1000,
584 .pressure_min = 0,
585 .stopacq_polarity = 1,
586 .first_conversion_delay = 3,
587 .acquisition_time = 1,
588 .averaging = 1,
589 .pen_down_acc_interval = 1,
590};
591#endif
592
46aa04f9
MH		 593#if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
594#include <linux/spi/ad7879.h>
46aa04f9
MH		 595static const struct ad7879_platform_data bfin_ad7879_ts_info = {
596 .model = 7879, /* Model = AD7879 */
597 .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
598 .pressure_max = 10000,
599 .pressure_min = 0,
600 .first_conversion_delay = 3, /* wait 512us before do a first conversion */
601 .acquisition_time = 1, /* 4us acquisition time per sample */
602 .median = 2, /* do 8 measurements */
603 .averaging = 1, /* take the average of 4 middle samples */
604 .pen_down_acc_interval = 255, /* 9.4 ms */
605 .gpio_output = 1, /* configure AUX/VBAT/GPIO as GPIO output */
606 .gpio_default = 1, /* During initialization set GPIO = HIGH */
607};
608#endif
609
f5150155
MH		 610#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
611static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
612 .enable_dma = 0,
613 .bits_per_word = 16,
614};
615#endif
616
6e668936
MH		 617#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
618static struct bfin5xx_spi_chip spidev_chip_info = {
619 .enable_dma = 0,
620 .bits_per_word = 8,
621};
622#endif
623
2043f3f7
MH		 624#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
625static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
626 .enable_dma = 0,
627 .bits_per_word = 8,
628};
629#endif
630
85a192e9
MH		 631#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE)
632static struct bfin5xx_spi_chip enc28j60_spi_chip_info = {
633 .enable_dma = 1,
634 .bits_per_word = 8,
635 .cs_gpio = GPIO_PF10,
636};
637#endif
638
8e9d5c7d
MH		 639#if defined(CONFIG_MTD_DATAFLASH) \
640 || defined(CONFIG_MTD_DATAFLASH_MODULE)
ceac2651
MH		 641
642static struct mtd_partition bfin_spi_dataflash_partitions[] = {
643 {
644 .name = "bootloader(spi)",
645 .size = 0x00040000,
646 .offset = 0,
647 .mask_flags = MTD_CAP_ROM
648 }, {
649 .name = "linux kernel(spi)",
6ecb5b6d 650 .size = 0x180000,
ceac2651
MH		 651 .offset = MTDPART_OFS_APPEND,
652 }, {
653 .name = "file system(spi)",
654 .size = MTDPART_SIZ_FULL,
655 .offset = MTDPART_OFS_APPEND,
656 }
657};
658
659static struct flash_platform_data bfin_spi_dataflash_data = {
660 .name = "SPI Dataflash",
661 .parts = bfin_spi_dataflash_partitions,
662 .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
663};
664
8e9d5c7d
MH		 665/* DataFlash chip */
666static struct bfin5xx_spi_chip data_flash_chip_info = {
667 .enable_dma = 0, /* use dma transfer with this chip*/
668 .bits_per_word = 8,
669};
670#endif
671
1394f032
BW		 672static struct spi_board_info bfin_spi_board_info[] __initdata = {
673#if defined(CONFIG_MTD_M25P80) \
674 || defined(CONFIG_MTD_M25P80_MODULE)
675 {
676 /* the modalias must be the same as spi device driver name */
677 .modalias = "m25p80", /* Name of spi_driver for this device */
678 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 679 .bus_num = 0, /* Framework bus number */
1394f032
BW		 680 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
681 .platform_data = &bfin_spi_flash_data,
682 .controller_data = &spi_flash_chip_info,
683 .mode = SPI_MODE_3,
684 },
685#endif
8e9d5c7d
MH		 686#if defined(CONFIG_MTD_DATAFLASH) \
687 || defined(CONFIG_MTD_DATAFLASH_MODULE)
688 { /* DataFlash chip */
689 .modalias = "mtd_dataflash",
ceac2651 690 .max_speed_hz = 33250000, /* max spi clock (SCK) speed in HZ */
8e9d5c7d
MH		 691 .bus_num = 0, /* Framework bus number */
692 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
ceac2651 693 .platform_data = &bfin_spi_dataflash_data,
8e9d5c7d
MH		 694 .controller_data = &data_flash_chip_info,
695 .mode = SPI_MODE_3,
696 },
697#endif
1394f032
BW		 698#if defined(CONFIG_SPI_ADC_BF533) \
699 || defined(CONFIG_SPI_ADC_BF533_MODULE)
700 {
701 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
702 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 703 .bus_num = 0, /* Framework bus number */
1394f032
BW		 704 .chip_select = 1, /* Framework chip select. */
705 .platform_data = NULL, /* No spi_driver specific config */
706 .controller_data = &spi_adc_chip_info,
707 },
708#endif
709
710#if defined(CONFIG_SND_BLACKFIN_AD1836) \
711 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
712 {
713 .modalias = "ad1836-spi",
714 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 715 .bus_num = 0,
1394f032
BW		 716 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
717 .controller_data = &ad1836_spi_chip_info,
718 },
719#endif
720#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
721 {
722 .modalias = "ad9960-spi",
723 .max_speed_hz = 10000000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 724 .bus_num = 0,
1394f032
BW		 725 .chip_select = 1,
726 .controller_data = &ad9960_spi_chip_info,
727 },
728#endif
f79ea4cb
YL		 729#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
730 {
731 .modalias = "mmc_spi",
732 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
733 .bus_num = 0,
734 .chip_select = 4,
735 .platform_data = &bfin_mmc_spi_pdata,
736 .controller_data = &mmc_spi_chip_info,
737 .mode = SPI_MODE_3,
738 },
739#endif
1394f032
BW		 740#if defined(CONFIG_PBX)
741 {
1f83b8f1
MF		 742 .modalias = "fxs-spi",
743 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb
BW		 744 .bus_num = 0,
745 .chip_select = 8 - CONFIG_J11_JUMPER,
1f83b8f1 746 .controller_data = &spi_si3xxx_chip_info,
1394f032
BW		 747 .mode = SPI_MODE_3,
748 },
749 {
1f83b8f1
MF		 750 .modalias = "fxo-spi",
751 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb
BW		 752 .bus_num = 0,
753 .chip_select = 8 - CONFIG_J19_JUMPER,
1f83b8f1 754 .controller_data = &spi_si3xxx_chip_info,
1394f032
BW		 755 .mode = SPI_MODE_3,
756 },
757#endif
1394f032
BW		 758#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
759 {
760 .modalias = "ad7877",
761 .platform_data = &bfin_ad7877_ts_info,
762 .irq = IRQ_PF6,
763 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
c7d48966 764 .bus_num = 0,
1394f032
BW		 765 .chip_select = 1,
766 .controller_data = &spi_ad7877_chip_info,
767 },
768#endif
f5150155 769#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
46aa04f9
MH		 770 {
771 .modalias = "ad7879",
772 .platform_data = &bfin_ad7879_ts_info,
773 .irq = IRQ_PF7,
774 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
775 .bus_num = 0,
776 .chip_select = 1,
777 .controller_data = &spi_ad7879_chip_info,
778 .mode = SPI_CPHA | SPI_CPOL,
779 },
780#endif
6e668936
MH		 781#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
782 {
783 .modalias = "spidev",
784 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
785 .bus_num = 0,
786 .chip_select = 1,
787 .controller_data = &spidev_chip_info,
788 },
789#endif
2043f3f7
MH		 790#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
791 {
792 .modalias = "bfin-lq035q1-spi",
793 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
794 .bus_num = 0,
46aa04f9 795 .chip_select = 2,
2043f3f7
MH		 796 .controller_data = &lq035q1_spi_chip_info,
797 .mode = SPI_CPHA | SPI_CPOL,
798 },
799#endif
85a192e9
MH		 800#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE)
801 {
802 .modalias = "enc28j60",
803 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
804 .irq = IRQ_PF6,
805 .bus_num = 0,
806 .chip_select = 0, /* GPIO controlled SSEL */
807 .controller_data = &enc28j60_spi_chip_info,
808 .mode = SPI_MODE_0,
809 },
810#endif
1394f032
BW		 811};
812
5bda2723 813#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
1394f032 814/* SPI controller data */
c6c4d7bb 815static struct bfin5xx_spi_master bfin_spi0_info = {
1394f032
BW		 816 .num_chipselect = 8,
817 .enable_dma = 1, /* master has the ability to do dma transfer */
5d448dd5 818 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1394f032
BW		 819};
820
c6c4d7bb
BW		 821/* SPI (0) */
822static struct resource bfin_spi0_resource[] = {
823 [0] = {
824 .start = SPI0_REGBASE,
825 .end = SPI0_REGBASE + 0xFF,
826 .flags = IORESOURCE_MEM,
827 },
828 [1] = {
829 .start = CH_SPI,
830 .end = CH_SPI,
831 .flags = IORESOURCE_IRQ,
832 },
833};
834
835static struct platform_device bfin_spi0_device = {
836 .name = "bfin-spi",
837 .id = 0, /* Bus number */
838 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
839 .resource = bfin_spi0_resource,
1394f032 840 .dev = {
c6c4d7bb 841 .platform_data = &bfin_spi0_info, /* Passed to driver */
1394f032
BW		 842 },
843};
844#endif /* spi master and devices */
845
846#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
847static struct platform_device bfin_fb_device = {
c6c4d7bb
BW		 848 .name = "bf537-lq035",
849};
850#endif
851
852#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
853static struct platform_device bfin_fb_adv7393_device = {
854 .name = "bfin-adv7393",
1394f032
BW		 855};
856#endif
857
2043f3f7
MH		 858#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
859#include <asm/bfin-lq035q1.h>
860
861static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
862 .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
46aa04f9 863 .use_bl = 0, /* let something else control the LCD Blacklight */
2043f3f7
MH		 864 .gpio_bl = GPIO_PF7,
865};
866
867static struct resource bfin_lq035q1_resources[] = {
868 {
869 .start = IRQ_PPI_ERROR,
870 .end = IRQ_PPI_ERROR,
871 .flags = IORESOURCE_IRQ,
872 },
873};
874
875static struct platform_device bfin_lq035q1_device = {
876 .name = "bfin-lq035q1",
877 .id = -1,
878 .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
879 .resource = bfin_lq035q1_resources,
880 .dev = {
881 .platform_data = &bfin_lq035q1_data,
882 },
883};
884#endif
885
1394f032
BW		 886#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
887static struct resource bfin_uart_resources[] = {
233b28a9 888#ifdef CONFIG_SERIAL_BFIN_UART0
1394f032
BW		 889 {
890 .start = 0xFFC00400,
891 .end = 0xFFC004FF,
892 .flags = IORESOURCE_MEM,
233b28a9
SZ		 893 },
894#endif
895#ifdef CONFIG_SERIAL_BFIN_UART1
896 {
1394f032
BW		 897 .start = 0xFFC02000,
898 .end = 0xFFC020FF,
899 .flags = IORESOURCE_MEM,
900 },
233b28a9 901#endif
1394f032
BW		 902};
903
904static struct platform_device bfin_uart_device = {
905 .name = "bfin-uart",
906 .id = 1,
907 .num_resources = ARRAY_SIZE(bfin_uart_resources),
908 .resource = bfin_uart_resources,
909};
910#endif
911
5be36d22 912#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
5be36d22 913#ifdef CONFIG_BFIN_SIR0
42bd8bcb 914static struct resource bfin_sir0_resources[] = {
5be36d22
GY		 915 {
916 .start = 0xFFC00400,
917 .end = 0xFFC004FF,
918 .flags = IORESOURCE_MEM,
919 },
42bd8bcb
GY		 920 {
921 .start = IRQ_UART0_RX,
922 .end = IRQ_UART0_RX+1,
923 .flags = IORESOURCE_IRQ,
924 },
925 {
926 .start = CH_UART0_RX,
927 .end = CH_UART0_RX+1,
928 .flags = IORESOURCE_DMA,
929 },
930};
931
932static struct platform_device bfin_sir0_device = {
933 .name = "bfin_sir",
934 .id = 0,
935 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
936 .resource = bfin_sir0_resources,
937};
5be36d22
GY		 938#endif
939#ifdef CONFIG_BFIN_SIR1
42bd8bcb 940static struct resource bfin_sir1_resources[] = {
5be36d22
GY		 941 {
942 .start = 0xFFC02000,
943 .end = 0xFFC020FF,
944 .flags = IORESOURCE_MEM,
945 },
42bd8bcb
GY		 946 {
947 .start = IRQ_UART1_RX,
948 .end = IRQ_UART1_RX+1,
949 .flags = IORESOURCE_IRQ,
950 },
951 {
952 .start = CH_UART1_RX,
953 .end = CH_UART1_RX+1,
954 .flags = IORESOURCE_DMA,
955 },
5be36d22
GY		 956};
957
42bd8bcb 958static struct platform_device bfin_sir1_device = {
5be36d22 959 .name = "bfin_sir",
42bd8bcb
GY		 960 .id = 1,
961 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
962 .resource = bfin_sir1_resources,
5be36d22
GY		 963};
964#endif
42bd8bcb 965#endif
5be36d22 966
1394f032 967#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
c6c4d7bb
BW		 968static struct resource bfin_twi0_resource[] = {
969 [0] = {
970 .start = TWI0_REGBASE,
971 .end = TWI0_REGBASE,
972 .flags = IORESOURCE_MEM,
973 },
974 [1] = {
975 .start = IRQ_TWI,
976 .end = IRQ_TWI,
977 .flags = IORESOURCE_IRQ,
978 },
979};
980
1394f032
BW		 981static struct platform_device i2c_bfin_twi_device = {
982 .name = "i2c-bfin-twi",
983 .id = 0,
c6c4d7bb
BW		 984 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
985 .resource = bfin_twi0_resource,
1394f032
BW		 986};
987#endif
988
51ed9ad7
MH		 989#if defined(CONFIG_KEYBOARD_ADP5588) || defined(CONFIG_KEYBOARD_ADP5588_MODULE)
990#include <linux/input.h>
991#include <linux/i2c/adp5588_keys.h>
992static const unsigned short adp5588_keymap[ADP5588_KEYMAPSIZE] = {
993 [0] = KEY_GRAVE,
994 [1] = KEY_1,
995 [2] = KEY_2,
996 [3] = KEY_3,
997 [4] = KEY_4,
998 [5] = KEY_5,
999 [6] = KEY_6,
1000 [7] = KEY_7,
1001 [8] = KEY_8,
1002 [9] = KEY_9,
1003 [10] = KEY_0,
1004 [11] = KEY_MINUS,
1005 [12] = KEY_EQUAL,
1006 [13] = KEY_BACKSLASH,
1007 [15] = KEY_KP0,
1008 [16] = KEY_Q,
1009 [17] = KEY_W,
1010 [18] = KEY_E,
1011 [19] = KEY_R,
1012 [20] = KEY_T,
1013 [21] = KEY_Y,
1014 [22] = KEY_U,
1015 [23] = KEY_I,
1016 [24] = KEY_O,
1017 [25] = KEY_P,
1018 [26] = KEY_LEFTBRACE,
1019 [27] = KEY_RIGHTBRACE,
1020 [29] = KEY_KP1,
1021 [30] = KEY_KP2,
1022 [31] = KEY_KP3,
1023 [32] = KEY_A,
1024 [33] = KEY_S,
1025 [34] = KEY_D,
1026 [35] = KEY_F,
1027 [36] = KEY_G,
1028 [37] = KEY_H,
1029 [38] = KEY_J,
1030 [39] = KEY_K,
1031 [40] = KEY_L,
1032 [41] = KEY_SEMICOLON,
1033 [42] = KEY_APOSTROPHE,
1034 [43] = KEY_BACKSLASH,
1035 [45] = KEY_KP4,
1036 [46] = KEY_KP5,
1037 [47] = KEY_KP6,
1038 [48] = KEY_102ND,
1039 [49] = KEY_Z,
1040 [50] = KEY_X,
1041 [51] = KEY_C,
1042 [52] = KEY_V,
1043 [53] = KEY_B,
1044 [54] = KEY_N,
1045 [55] = KEY_M,
1046 [56] = KEY_COMMA,
1047 [57] = KEY_DOT,
1048 [58] = KEY_SLASH,
1049 [60] = KEY_KPDOT,
1050 [61] = KEY_KP7,
1051 [62] = KEY_KP8,
1052 [63] = KEY_KP9,
1053 [64] = KEY_SPACE,
1054 [65] = KEY_BACKSPACE,
1055 [66] = KEY_TAB,
1056 [67] = KEY_KPENTER,
1057 [68] = KEY_ENTER,
1058 [69] = KEY_ESC,
1059 [70] = KEY_DELETE,
1060 [74] = KEY_KPMINUS,
1061 [76] = KEY_UP,
1062 [77] = KEY_DOWN,
1063 [78] = KEY_RIGHT,
1064 [79] = KEY_LEFT,
1065};
1066
1067static struct adp5588_kpad_platform_data adp5588_kpad_data = {
1068 .rows = 8,
1069 .cols = 10,
1070 .keymap = adp5588_keymap,
1071 .keymapsize = ARRAY_SIZE(adp5588_keymap),
1072 .repeat = 0,
1073};
1074#endif
1075
81d9c7f2
BW		 1076static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
1077#if defined(CONFIG_JOYSTICK_AD7142) || defined(CONFIG_JOYSTICK_AD7142_MODULE)
1078 {
1079 I2C_BOARD_INFO("ad7142_joystick", 0x2C),
f5150155 1080 .irq = IRQ_PF5,
81d9c7f2
BW		 1081 },
1082#endif
1083#if defined(CONFIG_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE)
1084 {
1085 I2C_BOARD_INFO("pcf8574_lcd", 0x22),
81d9c7f2
BW		 1086 },
1087#endif
1088#if defined(CONFIG_TWI_KEYPAD) || defined(CONFIG_TWI_KEYPAD_MODULE)
1089 {
1090 I2C_BOARD_INFO("pcf8574_keypad", 0x27),
f5150155
MH		 1091 .irq = IRQ_PG6,
1092 },
1093#endif
1094#if defined(CONFIG_TOUCHSCREEN_AD7879_I2C) || defined(CONFIG_TOUCHSCREEN_AD7879_I2C_MODULE)
1095 {
1096 I2C_BOARD_INFO("ad7879", 0x2F),
1097 .irq = IRQ_PG5,
1098 .platform_data = (void *)&bfin_ad7879_ts_info,
81d9c7f2
BW		 1099 },
1100#endif
51ed9ad7
MH		 1101#if defined(CONFIG_KEYBOARD_ADP5588) || defined(CONFIG_KEYBOARD_ADP5588_MODULE)
1102 {
1103 I2C_BOARD_INFO("adp5588-keys", 0x34),
1104 .irq = IRQ_PG0,
1105 .platform_data = (void *)&adp5588_kpad_data,
1106 },
1107#endif
81d9c7f2 1108};
81d9c7f2 1109
1394f032
BW		 1110#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
1111static struct platform_device bfin_sport0_uart_device = {
1112 .name = "bfin-sport-uart",
1113 .id = 0,
1114};
1115
1116static struct platform_device bfin_sport1_uart_device = {
1117 .name = "bfin-sport-uart",
1118 .id = 1,
1119};
1120#endif
1121
c6c4d7bb 1122#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
96b86e94 1123#define PATA_INT IRQ_PF5
c6c4d7bb
BW		 1124
1125static struct pata_platform_info bfin_pata_platform_data = {
1126 .ioport_shift = 1,
64e5c512 1127 .irq_flags = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
c6c4d7bb
BW		 1128};
1129
1130static struct resource bfin_pata_resources[] = {
1131 {
1132 .start = 0x20314020,
1133 .end = 0x2031403F,
1134 .flags = IORESOURCE_MEM,
1135 },
1136 {
1137 .start = 0x2031401C,
1138 .end = 0x2031401F,
1139 .flags = IORESOURCE_MEM,
1140 },
1141 {
1142 .start = PATA_INT,
1143 .end = PATA_INT,
1144 .flags = IORESOURCE_IRQ,
1145 },
1146};
1147
1148static struct platform_device bfin_pata_device = {
1149 .name = "pata_platform",
1150 .id = -1,
1151 .num_resources = ARRAY_SIZE(bfin_pata_resources),
1152 .resource = bfin_pata_resources,
1153 .dev = {
1154 .platform_data = &bfin_pata_platform_data,
1155 }
1156};
1157#endif
1158
14b03204
MH		 1159static const unsigned int cclk_vlev_datasheet[] =
1160{
1161 VRPAIR(VLEV_085, 250000000),
1162 VRPAIR(VLEV_090, 376000000),
1163 VRPAIR(VLEV_095, 426000000),
1164 VRPAIR(VLEV_100, 426000000),
1165 VRPAIR(VLEV_105, 476000000),
1166 VRPAIR(VLEV_110, 476000000),
1167 VRPAIR(VLEV_115, 476000000),
1168 VRPAIR(VLEV_120, 500000000),
1169 VRPAIR(VLEV_125, 533000000),
1170 VRPAIR(VLEV_130, 600000000),
1171};
1172
1173static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
1174 .tuple_tab = cclk_vlev_datasheet,
1175 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
1176 .vr_settling_time = 25 /* us */,
1177};
1178
1179static struct platform_device bfin_dpmc = {
1180 .name = "bfin dpmc",
1181 .dev = {
1182 .platform_data = &bfin_dmpc_vreg_data,
1183 },
1184};
1185
1394f032 1186static struct platform_device *stamp_devices[] __initdata = {
14b03204
MH		 1187
1188 &bfin_dpmc,
1189
1394f032
BW		 1190#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
1191 &bfin_pcmcia_cf_device,
1192#endif
1193
1194#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
1195 &rtc_device,
1196#endif
1197
1198#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
1199 &sl811_hcd_device,
1200#endif
1201
1202#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
1203 &isp1362_hcd_device,
1204#endif
1205
3f375690
MH		 1206#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
1207 &bfin_isp1760_device,
1208#endif
1209
1394f032
BW		 1210#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
1211 &smc91x_device,
1212#endif
1213
f40d24d9
AL		 1214#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
1215 &dm9000_device,
1216#endif
1217
561cc18b
MH		 1218#if defined(CONFIG_AX88180) || defined(CONFIG_AX88180_MODULE)
1219 &ax88180_device,
1220#endif
1221
1394f032 1222#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
65319628 1223 &bfin_mii_bus,
1394f032
BW		 1224 &bfin_mac_device,
1225#endif
1226
1227#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
1228 &net2272_bfin_device,
1229#endif
1230
1231#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
c6c4d7bb 1232 &bfin_spi0_device,
1394f032
BW		 1233#endif
1234
1235#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
1236 &bfin_fb_device,
1237#endif
1238
2043f3f7
MH		 1239#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
1240 &bfin_lq035q1_device,
1241#endif
1242
c6c4d7bb
BW		 1243#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
1244 &bfin_fb_adv7393_device,
1245#endif
1246
1394f032
BW		 1247#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
1248 &bfin_uart_device,
1249#endif
1250
5be36d22 1251#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
42bd8bcb
GY		 1252#ifdef CONFIG_BFIN_SIR0
1253 &bfin_sir0_device,
1254#endif
1255#ifdef CONFIG_BFIN_SIR1
1256 &bfin_sir1_device,
1257#endif
5be36d22
GY		 1258#endif
1259
1394f032
BW		 1260#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
1261 &i2c_bfin_twi_device,
1262#endif
1263
1264#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
1265 &bfin_sport0_uart_device,
1266 &bfin_sport1_uart_device,
1267#endif
c6c4d7bb
BW		 1268
1269#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
1270 &bfin_pata_device,
1271#endif
2463ef22
MH		 1272
1273#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
1274 &bfin_device_gpiokeys,
1275#endif
cad2ab65
MF		 1276
1277 &bfin_gpios_device,
793dc27b 1278
fc68911e
MF		 1279#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
1280 &bfin_async_nand_device,
1281#endif
1282
793dc27b 1283#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
de8c43f2 1284 &stamp_flash_device,
793dc27b 1285#endif
1394f032
BW		 1286};
1287
1288static int __init stamp_init(void)
1289{
b85d858b 1290 printk(KERN_INFO "%s(): registering device resources\n", __func__);
81d9c7f2
BW		 1291 i2c_register_board_info(0, bfin_i2c_board_info,
1292 ARRAY_SIZE(bfin_i2c_board_info));
fc68911e 1293 bfin_plat_nand_init();
1394f032 1294 platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
5bda2723 1295 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
c6c4d7bb
BW		 1296
1297#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
1298 irq_desc[PATA_INT].status |= IRQ_NOAUTOEN;
1299#endif
81d9c7f2 1300
1394f032
BW		 1301 return 0;
1302}
1303
1304arch_initcall(stamp_init);
c6c4d7bb
BW		 1305
1306void native_machine_restart(char *cmd)
1307{
1308 /* workaround reboot hang when booting from SPI */
1309 if ((bfin_read_SYSCR() & 0x7) == 0x3)
b52dae31 1310 bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
c6c4d7bb 1311}
137b1529
MF		 1312
1313/*
1314 * Currently the MAC address is saved in Flash by U-Boot
1315 */
1316#define FLASH_MAC 0x203f0000
9862cc52 1317void bfin_get_ether_addr(char *addr)
137b1529
MF		 1318{
1319 *(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC);
1320 *(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4);
1321}
9862cc52 1322EXPORT_SYMBOL(bfin_get_ether_addr);
kernel source for telekom puls (alcatel/mediatek)