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1394f032 BW |
1 | /* |
2 | * File: arch/blackfin/mach-bf537/boards/stamp.c | |
3 | * Based on: arch/blackfin/mach-bf533/boards/ezkit.c | |
4 | * Author: Aidan Williams <aidan@nicta.com.au> | |
5 | * | |
6 | * Created: | |
7 | * Description: | |
8 | * | |
9 | * Modified: | |
10 | * Copyright 2005 National ICT Australia (NICTA) | |
11 | * Copyright 2004-2006 Analog Devices Inc. | |
12 | * | |
13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License as published by | |
17 | * the Free Software Foundation; either version 2 of the License, or | |
18 | * (at your option) any later version. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License | |
26 | * along with this program; if not, see the file COPYING, or write | |
27 | * to the Free Software Foundation, Inc., | |
28 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
29 | */ | |
30 | ||
31 | #include <linux/device.h> | |
fc68911e | 32 | #include <linux/kernel.h> |
1394f032 BW |
33 | #include <linux/platform_device.h> |
34 | #include <linux/mtd/mtd.h> | |
fc68911e | 35 | #include <linux/mtd/nand.h> |
1394f032 | 36 | #include <linux/mtd/partitions.h> |
fc68911e | 37 | #include <linux/mtd/plat-ram.h> |
de8c43f2 | 38 | #include <linux/mtd/physmap.h> |
1394f032 BW |
39 | #include <linux/spi/spi.h> |
40 | #include <linux/spi/flash.h> | |
41 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) | |
f02bcec5 | 42 | #include <linux/usb/isp1362.h> |
1394f032 | 43 | #endif |
0a87e3e9 | 44 | #include <linux/ata_platform.h> |
1394f032 BW |
45 | #include <linux/irq.h> |
46 | #include <linux/interrupt.h> | |
81d9c7f2 | 47 | #include <linux/i2c.h> |
27f5d75a | 48 | #include <linux/usb/sl811.h> |
f79ea4cb | 49 | #include <linux/spi/mmc_spi.h> |
c6c4d7bb | 50 | #include <asm/dma.h> |
1f83b8f1 | 51 | #include <asm/bfin5xx_spi.h> |
c6c4d7bb | 52 | #include <asm/reboot.h> |
5d448dd5 | 53 | #include <asm/portmux.h> |
14b03204 | 54 | #include <asm/dpmc.h> |
1394f032 BW |
55 | |
56 | /* | |
57 | * Name the Board for the /proc/cpuinfo | |
58 | */ | |
fe85cad2 | 59 | const char bfin_board_name[] = "ADI BF537-STAMP"; |
1394f032 BW |
60 | |
61 | /* | |
62 | * Driver needs to know address, irq and flag pin. | |
63 | */ | |
64 | ||
1394f032 | 65 | #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) |
3f375690 MH |
66 | #include <linux/usb/isp1760.h> |
67 | static struct resource bfin_isp1760_resources[] = { | |
1394f032 | 68 | [0] = { |
3f375690 MH |
69 | .start = 0x203C0000, |
70 | .end = 0x203C0000 + 0x000fffff, | |
1394f032 BW |
71 | .flags = IORESOURCE_MEM, |
72 | }, | |
73 | [1] = { | |
3f375690 MH |
74 | .start = IRQ_PF7, |
75 | .end = IRQ_PF7, | |
6a6be3d1 | 76 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, |
1394f032 BW |
77 | }, |
78 | }; | |
79 | ||
3f375690 MH |
80 | static struct isp1760_platform_data isp1760_priv = { |
81 | .is_isp1761 = 0, | |
3f375690 MH |
82 | .bus_width_16 = 1, |
83 | .port1_otg = 0, | |
84 | .analog_oc = 0, | |
85 | .dack_polarity_high = 0, | |
86 | .dreq_polarity_high = 0, | |
1394f032 BW |
87 | }; |
88 | ||
3f375690 MH |
89 | static struct platform_device bfin_isp1760_device = { |
90 | .name = "isp1760-hcd", | |
91 | .id = 0, | |
92 | .dev = { | |
93 | .platform_data = &isp1760_priv, | |
94 | }, | |
95 | .num_resources = ARRAY_SIZE(bfin_isp1760_resources), | |
96 | .resource = bfin_isp1760_resources, | |
1394f032 | 97 | }; |
1394f032 BW |
98 | #endif |
99 | ||
2463ef22 MH |
100 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) |
101 | #include <linux/input.h> | |
102 | #include <linux/gpio_keys.h> | |
103 | ||
104 | static struct gpio_keys_button bfin_gpio_keys_table[] = { | |
105 | {BTN_0, GPIO_PF2, 1, "gpio-keys: BTN0"}, | |
106 | {BTN_1, GPIO_PF3, 1, "gpio-keys: BTN1"}, | |
107 | {BTN_2, GPIO_PF4, 1, "gpio-keys: BTN2"}, | |
108 | {BTN_3, GPIO_PF5, 1, "gpio-keys: BTN3"}, | |
109 | }; | |
110 | ||
111 | static struct gpio_keys_platform_data bfin_gpio_keys_data = { | |
112 | .buttons = bfin_gpio_keys_table, | |
113 | .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table), | |
114 | }; | |
115 | ||
116 | static struct platform_device bfin_device_gpiokeys = { | |
117 | .name = "gpio-keys", | |
118 | .dev = { | |
119 | .platform_data = &bfin_gpio_keys_data, | |
120 | }, | |
121 | }; | |
122 | #endif | |
123 | ||
cad2ab65 MF |
124 | static struct resource bfin_gpios_resources = { |
125 | .start = 0, | |
126 | .end = MAX_BLACKFIN_GPIOS - 1, | |
127 | .flags = IORESOURCE_IRQ, | |
128 | }; | |
129 | ||
130 | static struct platform_device bfin_gpios_device = { | |
131 | .name = "simple-gpio", | |
132 | .id = -1, | |
133 | .num_resources = 1, | |
134 | .resource = &bfin_gpios_resources, | |
135 | }; | |
136 | ||
1394f032 BW |
137 | #if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE) |
138 | static struct resource bfin_pcmcia_cf_resources[] = { | |
139 | { | |
140 | .start = 0x20310000, /* IO PORT */ | |
141 | .end = 0x20312000, | |
142 | .flags = IORESOURCE_MEM, | |
1f83b8f1 | 143 | }, { |
d2d50aa9 | 144 | .start = 0x20311000, /* Attribute Memory */ |
1394f032 BW |
145 | .end = 0x20311FFF, |
146 | .flags = IORESOURCE_MEM, | |
1f83b8f1 | 147 | }, { |
1394f032 BW |
148 | .start = IRQ_PF4, |
149 | .end = IRQ_PF4, | |
150 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, | |
1f83b8f1 | 151 | }, { |
1394f032 BW |
152 | .start = 6, /* Card Detect PF6 */ |
153 | .end = 6, | |
154 | .flags = IORESOURCE_IRQ, | |
155 | }, | |
156 | }; | |
157 | ||
158 | static struct platform_device bfin_pcmcia_cf_device = { | |
159 | .name = "bfin_cf_pcmcia", | |
160 | .id = -1, | |
161 | .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources), | |
162 | .resource = bfin_pcmcia_cf_resources, | |
163 | }; | |
164 | #endif | |
165 | ||
166 | #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) | |
167 | static struct platform_device rtc_device = { | |
168 | .name = "rtc-bfin", | |
169 | .id = -1, | |
170 | }; | |
171 | #endif | |
172 | ||
173 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | |
174 | static struct resource smc91x_resources[] = { | |
175 | { | |
176 | .name = "smc91x-regs", | |
177 | .start = 0x20300300, | |
178 | .end = 0x20300300 + 16, | |
179 | .flags = IORESOURCE_MEM, | |
1f83b8f1 | 180 | }, { |
1394f032 BW |
181 | |
182 | .start = IRQ_PF7, | |
183 | .end = IRQ_PF7, | |
184 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | |
185 | }, | |
186 | }; | |
187 | static struct platform_device smc91x_device = { | |
188 | .name = "smc91x", | |
189 | .id = 0, | |
190 | .num_resources = ARRAY_SIZE(smc91x_resources), | |
191 | .resource = smc91x_resources, | |
192 | }; | |
193 | #endif | |
194 | ||
f40d24d9 AL |
195 | #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE) |
196 | static struct resource dm9000_resources[] = { | |
197 | [0] = { | |
198 | .start = 0x203FB800, | |
199 | .end = 0x203FB800 + 8, | |
200 | .flags = IORESOURCE_MEM, | |
201 | }, | |
202 | [1] = { | |
203 | .start = IRQ_PF9, | |
204 | .end = IRQ_PF9, | |
205 | .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE), | |
206 | }, | |
207 | }; | |
208 | ||
209 | static struct platform_device dm9000_device = { | |
210 | .name = "dm9000", | |
211 | .id = -1, | |
212 | .num_resources = ARRAY_SIZE(dm9000_resources), | |
213 | .resource = dm9000_resources, | |
214 | }; | |
215 | #endif | |
216 | ||
561cc18b MH |
217 | #if defined(CONFIG_AX88180) || defined(CONFIG_AX88180_MODULE) |
218 | static struct resource ax88180_resources[] = { | |
219 | [0] = { | |
220 | .start = 0x20300000, | |
221 | .end = 0x20300000 + 0x8000, | |
222 | .flags = IORESOURCE_MEM, | |
223 | }, | |
224 | [1] = { | |
225 | .start = IRQ_PF7, | |
226 | .end = IRQ_PF7, | |
227 | .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL), | |
228 | }, | |
229 | }; | |
230 | ||
231 | static struct platform_device ax88180_device = { | |
232 | .name = "ax88180", | |
233 | .id = -1, | |
234 | .num_resources = ARRAY_SIZE(ax88180_resources), | |
235 | .resource = ax88180_resources, | |
236 | }; | |
237 | #endif | |
238 | ||
1394f032 BW |
239 | #if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE) |
240 | static struct resource sl811_hcd_resources[] = { | |
241 | { | |
242 | .start = 0x20340000, | |
243 | .end = 0x20340000, | |
244 | .flags = IORESOURCE_MEM, | |
1f83b8f1 | 245 | }, { |
1394f032 BW |
246 | .start = 0x20340004, |
247 | .end = 0x20340004, | |
248 | .flags = IORESOURCE_MEM, | |
1f83b8f1 | 249 | }, { |
1394f032 BW |
250 | .start = CONFIG_USB_SL811_BFIN_IRQ, |
251 | .end = CONFIG_USB_SL811_BFIN_IRQ, | |
252 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | |
253 | }, | |
254 | }; | |
255 | ||
256 | #if defined(CONFIG_USB_SL811_BFIN_USE_VBUS) | |
257 | void sl811_port_power(struct device *dev, int is_on) | |
258 | { | |
c6c4d7bb | 259 | gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS"); |
acbcd263 | 260 | gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS, is_on); |
1394f032 BW |
261 | } |
262 | #endif | |
263 | ||
264 | static struct sl811_platform_data sl811_priv = { | |
265 | .potpg = 10, | |
266 | .power = 250, /* == 500mA */ | |
267 | #if defined(CONFIG_USB_SL811_BFIN_USE_VBUS) | |
268 | .port_power = &sl811_port_power, | |
269 | #endif | |
270 | }; | |
271 | ||
272 | static struct platform_device sl811_hcd_device = { | |
273 | .name = "sl811-hcd", | |
274 | .id = 0, | |
275 | .dev = { | |
276 | .platform_data = &sl811_priv, | |
277 | }, | |
278 | .num_resources = ARRAY_SIZE(sl811_hcd_resources), | |
279 | .resource = sl811_hcd_resources, | |
280 | }; | |
281 | #endif | |
282 | ||
283 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) | |
284 | static struct resource isp1362_hcd_resources[] = { | |
285 | { | |
286 | .start = 0x20360000, | |
287 | .end = 0x20360000, | |
288 | .flags = IORESOURCE_MEM, | |
1f83b8f1 | 289 | }, { |
1394f032 BW |
290 | .start = 0x20360004, |
291 | .end = 0x20360004, | |
292 | .flags = IORESOURCE_MEM, | |
1f83b8f1 | 293 | }, { |
1394f032 BW |
294 | .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, |
295 | .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, | |
296 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | |
297 | }, | |
298 | }; | |
299 | ||
300 | static struct isp1362_platform_data isp1362_priv = { | |
301 | .sel15Kres = 1, | |
302 | .clknotstop = 0, | |
303 | .oc_enable = 0, | |
304 | .int_act_high = 0, | |
305 | .int_edge_triggered = 0, | |
306 | .remote_wakeup_connected = 0, | |
307 | .no_power_switching = 1, | |
308 | .power_switching_mode = 0, | |
309 | }; | |
310 | ||
311 | static struct platform_device isp1362_hcd_device = { | |
312 | .name = "isp1362-hcd", | |
313 | .id = 0, | |
314 | .dev = { | |
315 | .platform_data = &isp1362_priv, | |
316 | }, | |
317 | .num_resources = ARRAY_SIZE(isp1362_hcd_resources), | |
318 | .resource = isp1362_hcd_resources, | |
319 | }; | |
320 | #endif | |
321 | ||
322 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) | |
65319628 GY |
323 | static struct platform_device bfin_mii_bus = { |
324 | .name = "bfin_mii_bus", | |
325 | }; | |
326 | ||
1394f032 BW |
327 | static struct platform_device bfin_mac_device = { |
328 | .name = "bfin_mac", | |
65319628 | 329 | .dev.platform_data = &bfin_mii_bus, |
1394f032 BW |
330 | }; |
331 | #endif | |
332 | ||
333 | #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) | |
334 | static struct resource net2272_bfin_resources[] = { | |
335 | { | |
336 | .start = 0x20300000, | |
337 | .end = 0x20300000 + 0x100, | |
338 | .flags = IORESOURCE_MEM, | |
1f83b8f1 | 339 | }, { |
1394f032 BW |
340 | .start = IRQ_PF7, |
341 | .end = IRQ_PF7, | |
342 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | |
343 | }, | |
344 | }; | |
345 | ||
346 | static struct platform_device net2272_bfin_device = { | |
347 | .name = "net2272", | |
348 | .id = -1, | |
349 | .num_resources = ARRAY_SIZE(net2272_bfin_resources), | |
350 | .resource = net2272_bfin_resources, | |
351 | }; | |
352 | #endif | |
353 | ||
fc68911e MF |
354 | #if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE) |
355 | #ifdef CONFIG_MTD_PARTITIONS | |
356 | const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL }; | |
357 | ||
358 | static struct mtd_partition bfin_plat_nand_partitions[] = { | |
359 | { | |
aa582977 | 360 | .name = "linux kernel(nand)", |
fc68911e MF |
361 | .size = 0x400000, |
362 | .offset = 0, | |
363 | }, { | |
aa582977 | 364 | .name = "file system(nand)", |
fc68911e MF |
365 | .size = MTDPART_SIZ_FULL, |
366 | .offset = MTDPART_OFS_APPEND, | |
367 | }, | |
368 | }; | |
369 | #endif | |
370 | ||
371 | #define BFIN_NAND_PLAT_CLE 2 | |
372 | #define BFIN_NAND_PLAT_ALE 1 | |
373 | static void bfin_plat_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) | |
374 | { | |
375 | struct nand_chip *this = mtd->priv; | |
376 | ||
377 | if (cmd == NAND_CMD_NONE) | |
378 | return; | |
379 | ||
380 | if (ctrl & NAND_CLE) | |
381 | writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_CLE)); | |
382 | else | |
383 | writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_ALE)); | |
384 | } | |
385 | ||
386 | #define BFIN_NAND_PLAT_READY GPIO_PF3 | |
387 | static int bfin_plat_nand_dev_ready(struct mtd_info *mtd) | |
388 | { | |
389 | return gpio_get_value(BFIN_NAND_PLAT_READY); | |
390 | } | |
391 | ||
392 | static struct platform_nand_data bfin_plat_nand_data = { | |
393 | .chip = { | |
394 | .chip_delay = 30, | |
395 | #ifdef CONFIG_MTD_PARTITIONS | |
396 | .part_probe_types = part_probes, | |
397 | .partitions = bfin_plat_nand_partitions, | |
398 | .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions), | |
399 | #endif | |
400 | }, | |
401 | .ctrl = { | |
402 | .cmd_ctrl = bfin_plat_nand_cmd_ctrl, | |
403 | .dev_ready = bfin_plat_nand_dev_ready, | |
404 | }, | |
405 | }; | |
406 | ||
407 | #define MAX(x, y) (x > y ? x : y) | |
408 | static struct resource bfin_plat_nand_resources = { | |
409 | .start = 0x20212000, | |
410 | .end = 0x20212000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)), | |
411 | .flags = IORESOURCE_IO, | |
412 | }; | |
413 | ||
414 | static struct platform_device bfin_async_nand_device = { | |
415 | .name = "gen_nand", | |
416 | .id = -1, | |
417 | .num_resources = 1, | |
418 | .resource = &bfin_plat_nand_resources, | |
419 | .dev = { | |
420 | .platform_data = &bfin_plat_nand_data, | |
421 | }, | |
422 | }; | |
423 | ||
424 | static void bfin_plat_nand_init(void) | |
425 | { | |
426 | gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat"); | |
427 | } | |
428 | #else | |
429 | static void bfin_plat_nand_init(void) {} | |
430 | #endif | |
431 | ||
793dc27b | 432 | #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) |
de8c43f2 MF |
433 | static struct mtd_partition stamp_partitions[] = { |
434 | { | |
aa582977 | 435 | .name = "bootloader(nor)", |
edf05641 | 436 | .size = 0x40000, |
de8c43f2 MF |
437 | .offset = 0, |
438 | }, { | |
aa582977 | 439 | .name = "linux kernel(nor)", |
6ecb5b6d | 440 | .size = 0x180000, |
de8c43f2 MF |
441 | .offset = MTDPART_OFS_APPEND, |
442 | }, { | |
aa582977 | 443 | .name = "file system(nor)", |
6ecb5b6d | 444 | .size = 0x400000 - 0x40000 - 0x180000 - 0x10000, |
de8c43f2 MF |
445 | .offset = MTDPART_OFS_APPEND, |
446 | }, { | |
aa582977 | 447 | .name = "MAC Address(nor)", |
de8c43f2 MF |
448 | .size = MTDPART_SIZ_FULL, |
449 | .offset = 0x3F0000, | |
450 | .mask_flags = MTD_WRITEABLE, | |
451 | } | |
452 | }; | |
453 | ||
454 | static struct physmap_flash_data stamp_flash_data = { | |
455 | .width = 2, | |
456 | .parts = stamp_partitions, | |
457 | .nr_parts = ARRAY_SIZE(stamp_partitions), | |
458 | }; | |
459 | ||
460 | static struct resource stamp_flash_resource = { | |
461 | .start = 0x20000000, | |
462 | .end = 0x203fffff, | |
463 | .flags = IORESOURCE_MEM, | |
464 | }; | |
465 | ||
466 | static struct platform_device stamp_flash_device = { | |
467 | .name = "physmap-flash", | |
468 | .id = 0, | |
469 | .dev = { | |
470 | .platform_data = &stamp_flash_data, | |
471 | }, | |
472 | .num_resources = 1, | |
473 | .resource = &stamp_flash_resource, | |
474 | }; | |
793dc27b | 475 | #endif |
de8c43f2 | 476 | |
1394f032 BW |
477 | #if defined(CONFIG_MTD_M25P80) \ |
478 | || defined(CONFIG_MTD_M25P80_MODULE) | |
479 | static struct mtd_partition bfin_spi_flash_partitions[] = { | |
480 | { | |
aa582977 | 481 | .name = "bootloader(spi)", |
edf05641 | 482 | .size = 0x00040000, |
1394f032 BW |
483 | .offset = 0, |
484 | .mask_flags = MTD_CAP_ROM | |
1f83b8f1 | 485 | }, { |
aa582977 | 486 | .name = "linux kernel(spi)", |
6ecb5b6d | 487 | .size = 0x180000, |
edf05641 | 488 | .offset = MTDPART_OFS_APPEND, |
1f83b8f1 | 489 | }, { |
aa582977 | 490 | .name = "file system(spi)", |
edf05641 MF |
491 | .size = MTDPART_SIZ_FULL, |
492 | .offset = MTDPART_OFS_APPEND, | |
1394f032 BW |
493 | } |
494 | }; | |
495 | ||
496 | static struct flash_platform_data bfin_spi_flash_data = { | |
497 | .name = "m25p80", | |
498 | .parts = bfin_spi_flash_partitions, | |
499 | .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), | |
88a8078b | 500 | /* .type = "m25p64", */ |
1394f032 BW |
501 | }; |
502 | ||
503 | /* SPI flash chip (m25p64) */ | |
504 | static struct bfin5xx_spi_chip spi_flash_chip_info = { | |
505 | .enable_dma = 0, /* use dma transfer with this chip*/ | |
506 | .bits_per_word = 8, | |
507 | }; | |
508 | #endif | |
509 | ||
a261eec0 MF |
510 | #if defined(CONFIG_BFIN_SPI_ADC) \ |
511 | || defined(CONFIG_BFIN_SPI_ADC_MODULE) | |
1394f032 BW |
512 | /* SPI ADC chip */ |
513 | static struct bfin5xx_spi_chip spi_adc_chip_info = { | |
514 | .enable_dma = 1, /* use dma transfer with this chip*/ | |
515 | .bits_per_word = 16, | |
516 | }; | |
517 | #endif | |
518 | ||
519 | #if defined(CONFIG_SND_BLACKFIN_AD1836) \ | |
520 | || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) | |
521 | static struct bfin5xx_spi_chip ad1836_spi_chip_info = { | |
522 | .enable_dma = 0, | |
523 | .bits_per_word = 16, | |
524 | }; | |
525 | #endif | |
526 | ||
d4b834c1 BS |
527 | #if defined(CONFIG_SND_BF5XX_SOC_AD1938) \ |
528 | || defined(CONFIG_SND_BF5XX_SOC_AD1938_MODULE) | |
529 | static struct bfin5xx_spi_chip ad1938_spi_chip_info = { | |
530 | .enable_dma = 0, | |
531 | .bits_per_word = 8, | |
532 | .cs_gpio = GPIO_PF5, | |
533 | }; | |
534 | #endif | |
535 | ||
1394f032 BW |
536 | #if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE) |
537 | static struct bfin5xx_spi_chip ad9960_spi_chip_info = { | |
538 | .enable_dma = 0, | |
539 | .bits_per_word = 16, | |
540 | }; | |
541 | #endif | |
542 | ||
f79ea4cb YL |
543 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
544 | #define MMC_SPI_CARD_DETECT_INT IRQ_PF5 | |
545 | ||
546 | static int bfin_mmc_spi_init(struct device *dev, | |
547 | irqreturn_t (*detect_int)(int, void *), void *data) | |
548 | { | |
549 | return request_irq(MMC_SPI_CARD_DETECT_INT, detect_int, | |
550 | IRQF_TRIGGER_FALLING, "mmc-spi-detect", data); | |
551 | } | |
552 | ||
553 | static void bfin_mmc_spi_exit(struct device *dev, void *data) | |
554 | { | |
555 | free_irq(MMC_SPI_CARD_DETECT_INT, data); | |
556 | } | |
557 | ||
558 | static struct mmc_spi_platform_data bfin_mmc_spi_pdata = { | |
559 | .init = bfin_mmc_spi_init, | |
560 | .exit = bfin_mmc_spi_exit, | |
561 | .detect_delay = 100, /* msecs */ | |
562 | }; | |
563 | ||
564 | static struct bfin5xx_spi_chip mmc_spi_chip_info = { | |
565 | .enable_dma = 0, | |
566 | .bits_per_word = 8, | |
e68d1ebc | 567 | .pio_interrupt = 0, |
f79ea4cb YL |
568 | }; |
569 | #endif | |
570 | ||
1394f032 BW |
571 | #if defined(CONFIG_PBX) |
572 | static struct bfin5xx_spi_chip spi_si3xxx_chip_info = { | |
573 | .ctl_reg = 0x4, /* send zero */ | |
574 | .enable_dma = 0, | |
575 | .bits_per_word = 8, | |
576 | .cs_change_per_word = 1, | |
577 | }; | |
578 | #endif | |
579 | ||
1394f032 | 580 | #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) |
46aa04f9 | 581 | #include <linux/spi/ad7877.h> |
1394f032 | 582 | static struct bfin5xx_spi_chip spi_ad7877_chip_info = { |
1394f032 BW |
583 | .enable_dma = 0, |
584 | .bits_per_word = 16, | |
585 | }; | |
586 | ||
587 | static const struct ad7877_platform_data bfin_ad7877_ts_info = { | |
588 | .model = 7877, | |
589 | .vref_delay_usecs = 50, /* internal, no capacitor */ | |
590 | .x_plate_ohms = 419, | |
591 | .y_plate_ohms = 486, | |
592 | .pressure_max = 1000, | |
593 | .pressure_min = 0, | |
594 | .stopacq_polarity = 1, | |
595 | .first_conversion_delay = 3, | |
596 | .acquisition_time = 1, | |
597 | .averaging = 1, | |
598 | .pen_down_acc_interval = 1, | |
599 | }; | |
600 | #endif | |
601 | ||
46aa04f9 MH |
602 | #if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE) |
603 | #include <linux/spi/ad7879.h> | |
46aa04f9 MH |
604 | static const struct ad7879_platform_data bfin_ad7879_ts_info = { |
605 | .model = 7879, /* Model = AD7879 */ | |
606 | .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */ | |
607 | .pressure_max = 10000, | |
608 | .pressure_min = 0, | |
609 | .first_conversion_delay = 3, /* wait 512us before do a first conversion */ | |
610 | .acquisition_time = 1, /* 4us acquisition time per sample */ | |
611 | .median = 2, /* do 8 measurements */ | |
612 | .averaging = 1, /* take the average of 4 middle samples */ | |
613 | .pen_down_acc_interval = 255, /* 9.4 ms */ | |
614 | .gpio_output = 1, /* configure AUX/VBAT/GPIO as GPIO output */ | |
615 | .gpio_default = 1, /* During initialization set GPIO = HIGH */ | |
616 | }; | |
617 | #endif | |
618 | ||
ffc4d8bc MH |
619 | #if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE) |
620 | #include <linux/input.h> | |
621 | #include <linux/spi/adxl34x.h> | |
622 | static const struct adxl34x_platform_data adxl34x_info = { | |
623 | .x_axis_offset = 0, | |
624 | .y_axis_offset = 0, | |
625 | .z_axis_offset = 0, | |
626 | .tap_threshold = 0x31, | |
627 | .tap_duration = 0x10, | |
628 | .tap_latency = 0x60, | |
629 | .tap_window = 0xF0, | |
630 | .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN, | |
631 | .act_axis_control = 0xFF, | |
632 | .activity_threshold = 5, | |
633 | .inactivity_threshold = 3, | |
634 | .inactivity_time = 4, | |
635 | .free_fall_threshold = 0x7, | |
636 | .free_fall_time = 0x20, | |
637 | .data_rate = 0x8, | |
638 | .data_range = ADXL_FULL_RES, | |
639 | ||
640 | .ev_type = EV_ABS, | |
641 | .ev_code_x = ABS_X, /* EV_REL */ | |
642 | .ev_code_y = ABS_Y, /* EV_REL */ | |
643 | .ev_code_z = ABS_Z, /* EV_REL */ | |
644 | ||
645 | .ev_code_tap_x = BTN_TOUCH, /* EV_KEY */ | |
646 | .ev_code_tap_y = BTN_TOUCH, /* EV_KEY */ | |
647 | .ev_code_tap_z = BTN_TOUCH, /* EV_KEY */ | |
648 | ||
649 | /* .ev_code_ff = KEY_F,*/ /* EV_KEY */ | |
650 | /* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */ | |
651 | .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK, | |
652 | .fifo_mode = ADXL_FIFO_STREAM, | |
653 | }; | |
654 | #endif | |
655 | ||
f5150155 MH |
656 | #if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE) |
657 | static struct bfin5xx_spi_chip spi_ad7879_chip_info = { | |
658 | .enable_dma = 0, | |
659 | .bits_per_word = 16, | |
660 | }; | |
661 | #endif | |
662 | ||
6e668936 MH |
663 | #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) |
664 | static struct bfin5xx_spi_chip spidev_chip_info = { | |
665 | .enable_dma = 0, | |
666 | .bits_per_word = 8, | |
667 | }; | |
668 | #endif | |
669 | ||
2043f3f7 MH |
670 | #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) |
671 | static struct bfin5xx_spi_chip lq035q1_spi_chip_info = { | |
672 | .enable_dma = 0, | |
673 | .bits_per_word = 8, | |
674 | }; | |
675 | #endif | |
676 | ||
85a192e9 MH |
677 | #if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE) |
678 | static struct bfin5xx_spi_chip enc28j60_spi_chip_info = { | |
679 | .enable_dma = 1, | |
680 | .bits_per_word = 8, | |
681 | .cs_gpio = GPIO_PF10, | |
682 | }; | |
683 | #endif | |
684 | ||
8e9d5c7d MH |
685 | #if defined(CONFIG_MTD_DATAFLASH) \ |
686 | || defined(CONFIG_MTD_DATAFLASH_MODULE) | |
ceac2651 MH |
687 | |
688 | static struct mtd_partition bfin_spi_dataflash_partitions[] = { | |
689 | { | |
690 | .name = "bootloader(spi)", | |
691 | .size = 0x00040000, | |
692 | .offset = 0, | |
693 | .mask_flags = MTD_CAP_ROM | |
694 | }, { | |
695 | .name = "linux kernel(spi)", | |
6ecb5b6d | 696 | .size = 0x180000, |
ceac2651 MH |
697 | .offset = MTDPART_OFS_APPEND, |
698 | }, { | |
699 | .name = "file system(spi)", | |
700 | .size = MTDPART_SIZ_FULL, | |
701 | .offset = MTDPART_OFS_APPEND, | |
702 | } | |
703 | }; | |
704 | ||
705 | static struct flash_platform_data bfin_spi_dataflash_data = { | |
706 | .name = "SPI Dataflash", | |
707 | .parts = bfin_spi_dataflash_partitions, | |
708 | .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions), | |
709 | }; | |
710 | ||
8e9d5c7d MH |
711 | /* DataFlash chip */ |
712 | static struct bfin5xx_spi_chip data_flash_chip_info = { | |
713 | .enable_dma = 0, /* use dma transfer with this chip*/ | |
714 | .bits_per_word = 8, | |
715 | }; | |
716 | #endif | |
717 | ||
1394f032 BW |
718 | static struct spi_board_info bfin_spi_board_info[] __initdata = { |
719 | #if defined(CONFIG_MTD_M25P80) \ | |
720 | || defined(CONFIG_MTD_M25P80_MODULE) | |
721 | { | |
722 | /* the modalias must be the same as spi device driver name */ | |
723 | .modalias = "m25p80", /* Name of spi_driver for this device */ | |
724 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | |
c6c4d7bb | 725 | .bus_num = 0, /* Framework bus number */ |
1394f032 BW |
726 | .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/ |
727 | .platform_data = &bfin_spi_flash_data, | |
728 | .controller_data = &spi_flash_chip_info, | |
729 | .mode = SPI_MODE_3, | |
730 | }, | |
731 | #endif | |
8e9d5c7d MH |
732 | #if defined(CONFIG_MTD_DATAFLASH) \ |
733 | || defined(CONFIG_MTD_DATAFLASH_MODULE) | |
734 | { /* DataFlash chip */ | |
735 | .modalias = "mtd_dataflash", | |
ceac2651 | 736 | .max_speed_hz = 33250000, /* max spi clock (SCK) speed in HZ */ |
8e9d5c7d MH |
737 | .bus_num = 0, /* Framework bus number */ |
738 | .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/ | |
ceac2651 | 739 | .platform_data = &bfin_spi_dataflash_data, |
8e9d5c7d MH |
740 | .controller_data = &data_flash_chip_info, |
741 | .mode = SPI_MODE_3, | |
742 | }, | |
743 | #endif | |
a261eec0 MF |
744 | #if defined(CONFIG_BFIN_SPI_ADC) \ |
745 | || defined(CONFIG_BFIN_SPI_ADC_MODULE) | |
1394f032 BW |
746 | { |
747 | .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ | |
748 | .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ | |
c6c4d7bb | 749 | .bus_num = 0, /* Framework bus number */ |
1394f032 BW |
750 | .chip_select = 1, /* Framework chip select. */ |
751 | .platform_data = NULL, /* No spi_driver specific config */ | |
752 | .controller_data = &spi_adc_chip_info, | |
753 | }, | |
754 | #endif | |
755 | ||
756 | #if defined(CONFIG_SND_BLACKFIN_AD1836) \ | |
757 | || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) | |
758 | { | |
759 | .modalias = "ad1836-spi", | |
760 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ | |
c6c4d7bb | 761 | .bus_num = 0, |
1394f032 BW |
762 | .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, |
763 | .controller_data = &ad1836_spi_chip_info, | |
764 | }, | |
765 | #endif | |
d4b834c1 BS |
766 | |
767 | #if defined(CONFIG_SND_BF5XX_SOC_AD1938) || defined(CONFIG_SND_BF5XX_SOC_AD1938_MODULE) | |
768 | { | |
769 | .modalias = "ad1938-spi", | |
770 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ | |
771 | .bus_num = 0, | |
772 | .chip_select = 0,/* CONFIG_SND_BLACKFIN_SPI_PFBIT */ | |
773 | .controller_data = &ad1938_spi_chip_info, | |
774 | .mode = SPI_MODE_3, | |
775 | }, | |
776 | #endif | |
777 | ||
1394f032 BW |
778 | #if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE) |
779 | { | |
780 | .modalias = "ad9960-spi", | |
781 | .max_speed_hz = 10000000, /* max spi clock (SCK) speed in HZ */ | |
c6c4d7bb | 782 | .bus_num = 0, |
1394f032 BW |
783 | .chip_select = 1, |
784 | .controller_data = &ad9960_spi_chip_info, | |
785 | }, | |
786 | #endif | |
f79ea4cb YL |
787 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
788 | { | |
789 | .modalias = "mmc_spi", | |
790 | .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ | |
791 | .bus_num = 0, | |
792 | .chip_select = 4, | |
793 | .platform_data = &bfin_mmc_spi_pdata, | |
794 | .controller_data = &mmc_spi_chip_info, | |
795 | .mode = SPI_MODE_3, | |
796 | }, | |
797 | #endif | |
1394f032 BW |
798 | #if defined(CONFIG_PBX) |
799 | { | |
1f83b8f1 MF |
800 | .modalias = "fxs-spi", |
801 | .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ | |
c6c4d7bb BW |
802 | .bus_num = 0, |
803 | .chip_select = 8 - CONFIG_J11_JUMPER, | |
1f83b8f1 | 804 | .controller_data = &spi_si3xxx_chip_info, |
1394f032 BW |
805 | .mode = SPI_MODE_3, |
806 | }, | |
807 | { | |
1f83b8f1 MF |
808 | .modalias = "fxo-spi", |
809 | .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ | |
c6c4d7bb BW |
810 | .bus_num = 0, |
811 | .chip_select = 8 - CONFIG_J19_JUMPER, | |
1f83b8f1 | 812 | .controller_data = &spi_si3xxx_chip_info, |
1394f032 BW |
813 | .mode = SPI_MODE_3, |
814 | }, | |
815 | #endif | |
1394f032 BW |
816 | #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) |
817 | { | |
818 | .modalias = "ad7877", | |
819 | .platform_data = &bfin_ad7877_ts_info, | |
820 | .irq = IRQ_PF6, | |
821 | .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ | |
c7d48966 | 822 | .bus_num = 0, |
1394f032 BW |
823 | .chip_select = 1, |
824 | .controller_data = &spi_ad7877_chip_info, | |
825 | }, | |
826 | #endif | |
f5150155 | 827 | #if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE) |
46aa04f9 MH |
828 | { |
829 | .modalias = "ad7879", | |
830 | .platform_data = &bfin_ad7879_ts_info, | |
831 | .irq = IRQ_PF7, | |
832 | .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ | |
833 | .bus_num = 0, | |
834 | .chip_select = 1, | |
835 | .controller_data = &spi_ad7879_chip_info, | |
836 | .mode = SPI_CPHA | SPI_CPOL, | |
837 | }, | |
838 | #endif | |
6e668936 MH |
839 | #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) |
840 | { | |
841 | .modalias = "spidev", | |
842 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ | |
843 | .bus_num = 0, | |
844 | .chip_select = 1, | |
845 | .controller_data = &spidev_chip_info, | |
846 | }, | |
847 | #endif | |
2043f3f7 MH |
848 | #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) |
849 | { | |
850 | .modalias = "bfin-lq035q1-spi", | |
851 | .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ | |
852 | .bus_num = 0, | |
46aa04f9 | 853 | .chip_select = 2, |
2043f3f7 MH |
854 | .controller_data = &lq035q1_spi_chip_info, |
855 | .mode = SPI_CPHA | SPI_CPOL, | |
856 | }, | |
857 | #endif | |
85a192e9 MH |
858 | #if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE) |
859 | { | |
860 | .modalias = "enc28j60", | |
861 | .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ | |
862 | .irq = IRQ_PF6, | |
863 | .bus_num = 0, | |
864 | .chip_select = 0, /* GPIO controlled SSEL */ | |
865 | .controller_data = &enc28j60_spi_chip_info, | |
866 | .mode = SPI_MODE_0, | |
867 | }, | |
868 | #endif | |
1394f032 BW |
869 | }; |
870 | ||
5bda2723 | 871 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) |
1394f032 | 872 | /* SPI controller data */ |
c6c4d7bb | 873 | static struct bfin5xx_spi_master bfin_spi0_info = { |
1394f032 BW |
874 | .num_chipselect = 8, |
875 | .enable_dma = 1, /* master has the ability to do dma transfer */ | |
5d448dd5 | 876 | .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, |
1394f032 BW |
877 | }; |
878 | ||
c6c4d7bb BW |
879 | /* SPI (0) */ |
880 | static struct resource bfin_spi0_resource[] = { | |
881 | [0] = { | |
882 | .start = SPI0_REGBASE, | |
883 | .end = SPI0_REGBASE + 0xFF, | |
884 | .flags = IORESOURCE_MEM, | |
885 | }, | |
886 | [1] = { | |
887 | .start = CH_SPI, | |
888 | .end = CH_SPI, | |
e68d1ebc YL |
889 | .flags = IORESOURCE_DMA, |
890 | }, | |
891 | [2] = { | |
892 | .start = IRQ_SPI, | |
893 | .end = IRQ_SPI, | |
c6c4d7bb BW |
894 | .flags = IORESOURCE_IRQ, |
895 | }, | |
896 | }; | |
897 | ||
898 | static struct platform_device bfin_spi0_device = { | |
899 | .name = "bfin-spi", | |
900 | .id = 0, /* Bus number */ | |
901 | .num_resources = ARRAY_SIZE(bfin_spi0_resource), | |
902 | .resource = bfin_spi0_resource, | |
1394f032 | 903 | .dev = { |
c6c4d7bb | 904 | .platform_data = &bfin_spi0_info, /* Passed to driver */ |
1394f032 BW |
905 | }, |
906 | }; | |
907 | #endif /* spi master and devices */ | |
908 | ||
1e9aa955 CC |
909 | #if defined(CONFIG_SPI_BFIN_SPORT) || defined(CONFIG_SPI_BFIN_SPORT_MODULE) |
910 | ||
911 | /* SPORT SPI controller data */ | |
912 | static struct bfin5xx_spi_master bfin_sport_spi0_info = { | |
913 | .num_chipselect = 1, /* master only supports one device */ | |
914 | .enable_dma = 0, /* master don't support DMA */ | |
915 | .pin_req = {P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_DRPRI, | |
916 | P_SPORT0_RSCLK, P_SPORT0_TFS, P_SPORT0_RFS, 0}, | |
917 | }; | |
918 | ||
919 | static struct resource bfin_sport_spi0_resource[] = { | |
920 | [0] = { | |
921 | .start = SPORT0_TCR1, | |
922 | .end = SPORT0_TCR1 + 0xFF, | |
923 | .flags = IORESOURCE_MEM, | |
924 | }, | |
925 | [1] = { | |
926 | .start = IRQ_SPORT0_ERROR, | |
927 | .end = IRQ_SPORT0_ERROR, | |
928 | .flags = IORESOURCE_IRQ, | |
929 | }, | |
930 | }; | |
931 | ||
932 | static struct platform_device bfin_sport_spi0_device = { | |
933 | .name = "bfin-sport-spi", | |
934 | .id = 1, /* Bus number */ | |
935 | .num_resources = ARRAY_SIZE(bfin_sport_spi0_resource), | |
936 | .resource = bfin_sport_spi0_resource, | |
937 | .dev = { | |
938 | .platform_data = &bfin_sport_spi0_info, /* Passed to driver */ | |
939 | }, | |
940 | }; | |
941 | ||
942 | static struct bfin5xx_spi_master bfin_sport_spi1_info = { | |
943 | .num_chipselect = 1, /* master only supports one device */ | |
944 | .enable_dma = 0, /* master don't support DMA */ | |
945 | .pin_req = {P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_DRPRI, | |
946 | P_SPORT1_RSCLK, P_SPORT1_TFS, P_SPORT1_RFS, 0}, | |
947 | }; | |
948 | ||
949 | static struct resource bfin_sport_spi1_resource[] = { | |
950 | [0] = { | |
951 | .start = SPORT1_TCR1, | |
952 | .end = SPORT1_TCR1 + 0xFF, | |
953 | .flags = IORESOURCE_MEM, | |
954 | }, | |
955 | [1] = { | |
956 | .start = IRQ_SPORT1_ERROR, | |
957 | .end = IRQ_SPORT1_ERROR, | |
958 | .flags = IORESOURCE_IRQ, | |
959 | }, | |
960 | }; | |
961 | ||
962 | static struct platform_device bfin_sport_spi1_device = { | |
963 | .name = "bfin-sport-spi", | |
964 | .id = 2, /* Bus number */ | |
965 | .num_resources = ARRAY_SIZE(bfin_sport_spi1_resource), | |
966 | .resource = bfin_sport_spi1_resource, | |
967 | .dev = { | |
968 | .platform_data = &bfin_sport_spi1_info, /* Passed to driver */ | |
969 | }, | |
970 | }; | |
971 | ||
972 | #endif /* sport spi master and devices */ | |
973 | ||
1394f032 BW |
974 | #if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE) |
975 | static struct platform_device bfin_fb_device = { | |
c6c4d7bb BW |
976 | .name = "bf537-lq035", |
977 | }; | |
978 | #endif | |
979 | ||
980 | #if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE) | |
981 | static struct platform_device bfin_fb_adv7393_device = { | |
982 | .name = "bfin-adv7393", | |
1394f032 BW |
983 | }; |
984 | #endif | |
985 | ||
2043f3f7 MH |
986 | #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) |
987 | #include <asm/bfin-lq035q1.h> | |
988 | ||
989 | static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = { | |
990 | .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB, | |
46aa04f9 | 991 | .use_bl = 0, /* let something else control the LCD Blacklight */ |
2043f3f7 MH |
992 | .gpio_bl = GPIO_PF7, |
993 | }; | |
994 | ||
995 | static struct resource bfin_lq035q1_resources[] = { | |
996 | { | |
997 | .start = IRQ_PPI_ERROR, | |
998 | .end = IRQ_PPI_ERROR, | |
999 | .flags = IORESOURCE_IRQ, | |
1000 | }, | |
1001 | }; | |
1002 | ||
1003 | static struct platform_device bfin_lq035q1_device = { | |
1004 | .name = "bfin-lq035q1", | |
1005 | .id = -1, | |
1006 | .num_resources = ARRAY_SIZE(bfin_lq035q1_resources), | |
1007 | .resource = bfin_lq035q1_resources, | |
1008 | .dev = { | |
1009 | .platform_data = &bfin_lq035q1_data, | |
1010 | }, | |
1011 | }; | |
1012 | #endif | |
1013 | ||
1394f032 BW |
1014 | #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) |
1015 | static struct resource bfin_uart_resources[] = { | |
233b28a9 | 1016 | #ifdef CONFIG_SERIAL_BFIN_UART0 |
1394f032 BW |
1017 | { |
1018 | .start = 0xFFC00400, | |
1019 | .end = 0xFFC004FF, | |
1020 | .flags = IORESOURCE_MEM, | |
233b28a9 SZ |
1021 | }, |
1022 | #endif | |
1023 | #ifdef CONFIG_SERIAL_BFIN_UART1 | |
1024 | { | |
1394f032 BW |
1025 | .start = 0xFFC02000, |
1026 | .end = 0xFFC020FF, | |
1027 | .flags = IORESOURCE_MEM, | |
1028 | }, | |
233b28a9 | 1029 | #endif |
1394f032 BW |
1030 | }; |
1031 | ||
1032 | static struct platform_device bfin_uart_device = { | |
1033 | .name = "bfin-uart", | |
1034 | .id = 1, | |
1035 | .num_resources = ARRAY_SIZE(bfin_uart_resources), | |
1036 | .resource = bfin_uart_resources, | |
1037 | }; | |
1038 | #endif | |
1039 | ||
5be36d22 | 1040 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
5be36d22 | 1041 | #ifdef CONFIG_BFIN_SIR0 |
42bd8bcb | 1042 | static struct resource bfin_sir0_resources[] = { |
5be36d22 GY |
1043 | { |
1044 | .start = 0xFFC00400, | |
1045 | .end = 0xFFC004FF, | |
1046 | .flags = IORESOURCE_MEM, | |
1047 | }, | |
42bd8bcb GY |
1048 | { |
1049 | .start = IRQ_UART0_RX, | |
1050 | .end = IRQ_UART0_RX+1, | |
1051 | .flags = IORESOURCE_IRQ, | |
1052 | }, | |
1053 | { | |
1054 | .start = CH_UART0_RX, | |
1055 | .end = CH_UART0_RX+1, | |
1056 | .flags = IORESOURCE_DMA, | |
1057 | }, | |
1058 | }; | |
1059 | ||
1060 | static struct platform_device bfin_sir0_device = { | |
1061 | .name = "bfin_sir", | |
1062 | .id = 0, | |
1063 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), | |
1064 | .resource = bfin_sir0_resources, | |
1065 | }; | |
5be36d22 GY |
1066 | #endif |
1067 | #ifdef CONFIG_BFIN_SIR1 | |
42bd8bcb | 1068 | static struct resource bfin_sir1_resources[] = { |
5be36d22 GY |
1069 | { |
1070 | .start = 0xFFC02000, | |
1071 | .end = 0xFFC020FF, | |
1072 | .flags = IORESOURCE_MEM, | |
1073 | }, | |
42bd8bcb GY |
1074 | { |
1075 | .start = IRQ_UART1_RX, | |
1076 | .end = IRQ_UART1_RX+1, | |
1077 | .flags = IORESOURCE_IRQ, | |
1078 | }, | |
1079 | { | |
1080 | .start = CH_UART1_RX, | |
1081 | .end = CH_UART1_RX+1, | |
1082 | .flags = IORESOURCE_DMA, | |
1083 | }, | |
5be36d22 GY |
1084 | }; |
1085 | ||
42bd8bcb | 1086 | static struct platform_device bfin_sir1_device = { |
5be36d22 | 1087 | .name = "bfin_sir", |
42bd8bcb GY |
1088 | .id = 1, |
1089 | .num_resources = ARRAY_SIZE(bfin_sir1_resources), | |
1090 | .resource = bfin_sir1_resources, | |
5be36d22 GY |
1091 | }; |
1092 | #endif | |
42bd8bcb | 1093 | #endif |
5be36d22 | 1094 | |
1394f032 | 1095 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) |
c6c4d7bb BW |
1096 | static struct resource bfin_twi0_resource[] = { |
1097 | [0] = { | |
1098 | .start = TWI0_REGBASE, | |
1099 | .end = TWI0_REGBASE, | |
1100 | .flags = IORESOURCE_MEM, | |
1101 | }, | |
1102 | [1] = { | |
1103 | .start = IRQ_TWI, | |
1104 | .end = IRQ_TWI, | |
1105 | .flags = IORESOURCE_IRQ, | |
1106 | }, | |
1107 | }; | |
1108 | ||
1394f032 BW |
1109 | static struct platform_device i2c_bfin_twi_device = { |
1110 | .name = "i2c-bfin-twi", | |
1111 | .id = 0, | |
c6c4d7bb BW |
1112 | .num_resources = ARRAY_SIZE(bfin_twi0_resource), |
1113 | .resource = bfin_twi0_resource, | |
1394f032 BW |
1114 | }; |
1115 | #endif | |
1116 | ||
51ed9ad7 MH |
1117 | #if defined(CONFIG_KEYBOARD_ADP5588) || defined(CONFIG_KEYBOARD_ADP5588_MODULE) |
1118 | #include <linux/input.h> | |
f39d56ec | 1119 | #include <linux/i2c/adp5588.h> |
51ed9ad7 MH |
1120 | static const unsigned short adp5588_keymap[ADP5588_KEYMAPSIZE] = { |
1121 | [0] = KEY_GRAVE, | |
1122 | [1] = KEY_1, | |
1123 | [2] = KEY_2, | |
1124 | [3] = KEY_3, | |
1125 | [4] = KEY_4, | |
1126 | [5] = KEY_5, | |
1127 | [6] = KEY_6, | |
1128 | [7] = KEY_7, | |
1129 | [8] = KEY_8, | |
1130 | [9] = KEY_9, | |
1131 | [10] = KEY_0, | |
1132 | [11] = KEY_MINUS, | |
1133 | [12] = KEY_EQUAL, | |
1134 | [13] = KEY_BACKSLASH, | |
1135 | [15] = KEY_KP0, | |
1136 | [16] = KEY_Q, | |
1137 | [17] = KEY_W, | |
1138 | [18] = KEY_E, | |
1139 | [19] = KEY_R, | |
1140 | [20] = KEY_T, | |
1141 | [21] = KEY_Y, | |
1142 | [22] = KEY_U, | |
1143 | [23] = KEY_I, | |
1144 | [24] = KEY_O, | |
1145 | [25] = KEY_P, | |
1146 | [26] = KEY_LEFTBRACE, | |
1147 | [27] = KEY_RIGHTBRACE, | |
1148 | [29] = KEY_KP1, | |
1149 | [30] = KEY_KP2, | |
1150 | [31] = KEY_KP3, | |
1151 | [32] = KEY_A, | |
1152 | [33] = KEY_S, | |
1153 | [34] = KEY_D, | |
1154 | [35] = KEY_F, | |
1155 | [36] = KEY_G, | |
1156 | [37] = KEY_H, | |
1157 | [38] = KEY_J, | |
1158 | [39] = KEY_K, | |
1159 | [40] = KEY_L, | |
1160 | [41] = KEY_SEMICOLON, | |
1161 | [42] = KEY_APOSTROPHE, | |
1162 | [43] = KEY_BACKSLASH, | |
1163 | [45] = KEY_KP4, | |
1164 | [46] = KEY_KP5, | |
1165 | [47] = KEY_KP6, | |
1166 | [48] = KEY_102ND, | |
1167 | [49] = KEY_Z, | |
1168 | [50] = KEY_X, | |
1169 | [51] = KEY_C, | |
1170 | [52] = KEY_V, | |
1171 | [53] = KEY_B, | |
1172 | [54] = KEY_N, | |
1173 | [55] = KEY_M, | |
1174 | [56] = KEY_COMMA, | |
1175 | [57] = KEY_DOT, | |
1176 | [58] = KEY_SLASH, | |
1177 | [60] = KEY_KPDOT, | |
1178 | [61] = KEY_KP7, | |
1179 | [62] = KEY_KP8, | |
1180 | [63] = KEY_KP9, | |
1181 | [64] = KEY_SPACE, | |
1182 | [65] = KEY_BACKSPACE, | |
1183 | [66] = KEY_TAB, | |
1184 | [67] = KEY_KPENTER, | |
1185 | [68] = KEY_ENTER, | |
1186 | [69] = KEY_ESC, | |
1187 | [70] = KEY_DELETE, | |
1188 | [74] = KEY_KPMINUS, | |
1189 | [76] = KEY_UP, | |
1190 | [77] = KEY_DOWN, | |
1191 | [78] = KEY_RIGHT, | |
1192 | [79] = KEY_LEFT, | |
1193 | }; | |
1194 | ||
1195 | static struct adp5588_kpad_platform_data adp5588_kpad_data = { | |
1196 | .rows = 8, | |
1197 | .cols = 10, | |
1198 | .keymap = adp5588_keymap, | |
1199 | .keymapsize = ARRAY_SIZE(adp5588_keymap), | |
1200 | .repeat = 0, | |
1201 | }; | |
1202 | #endif | |
1203 | ||
3ea57218 MH |
1204 | #if defined(CONFIG_PMIC_ADP5520) || defined(CONFIG_PMIC_ADP5520_MODULE) |
1205 | #include <linux/mfd/adp5520.h> | |
1206 | ||
1207 | /* | |
1208 | * ADP5520/5501 Backlight Data | |
1209 | */ | |
1210 | ||
1211 | static struct adp5520_backlight_platfrom_data adp5520_backlight_data = { | |
1212 | .fade_in = FADE_T_1200ms, | |
1213 | .fade_out = FADE_T_1200ms, | |
1214 | .fade_led_law = BL_LAW_LINEAR, | |
1215 | .en_ambl_sens = 1, | |
1216 | .abml_filt = BL_AMBL_FILT_640ms, | |
1217 | .l1_daylight_max = BL_CUR_mA(15), | |
1218 | .l1_daylight_dim = BL_CUR_mA(0), | |
1219 | .l2_office_max = BL_CUR_mA(7), | |
1220 | .l2_office_dim = BL_CUR_mA(0), | |
1221 | .l3_dark_max = BL_CUR_mA(3), | |
1222 | .l3_dark_dim = BL_CUR_mA(0), | |
1223 | .l2_trip = L2_COMP_CURR_uA(700), | |
1224 | .l2_hyst = L2_COMP_CURR_uA(50), | |
1225 | .l3_trip = L3_COMP_CURR_uA(80), | |
1226 | .l3_hyst = L3_COMP_CURR_uA(20), | |
1227 | }; | |
1228 | ||
1229 | /* | |
1230 | * ADP5520/5501 LEDs Data | |
1231 | */ | |
1232 | ||
1233 | #include <linux/leds.h> | |
1234 | ||
1235 | static struct led_info adp5520_leds[] = { | |
1236 | { | |
1237 | .name = "adp5520-led1", | |
1238 | .default_trigger = "none", | |
1239 | .flags = FLAG_ID_ADP5520_LED1_ADP5501_LED0 | LED_OFFT_600ms, | |
1240 | }, | |
1241 | #ifdef ADP5520_EN_ALL_LEDS | |
1242 | { | |
1243 | .name = "adp5520-led2", | |
1244 | .default_trigger = "none", | |
1245 | .flags = FLAG_ID_ADP5520_LED2_ADP5501_LED1, | |
1246 | }, | |
1247 | { | |
1248 | .name = "adp5520-led3", | |
1249 | .default_trigger = "none", | |
1250 | .flags = FLAG_ID_ADP5520_LED3_ADP5501_LED2, | |
1251 | }, | |
1252 | #endif | |
1253 | }; | |
1254 | ||
1255 | static struct adp5520_leds_platfrom_data adp5520_leds_data = { | |
1256 | .num_leds = ARRAY_SIZE(adp5520_leds), | |
1257 | .leds = adp5520_leds, | |
1258 | .fade_in = FADE_T_600ms, | |
1259 | .fade_out = FADE_T_600ms, | |
1260 | .led_on_time = LED_ONT_600ms, | |
1261 | }; | |
1262 | ||
1263 | /* | |
1264 | * ADP5520 GPIO Data | |
1265 | */ | |
1266 | ||
1267 | static struct adp5520_gpio_platfrom_data adp5520_gpio_data = { | |
1268 | .gpio_start = 50, | |
1269 | .gpio_en_mask = GPIO_C1 | GPIO_C2 | GPIO_R2, | |
1270 | .gpio_pullup_mask = GPIO_C1 | GPIO_C2 | GPIO_R2, | |
1271 | }; | |
1272 | ||
1273 | /* | |
1274 | * ADP5520 Keypad Data | |
1275 | */ | |
1276 | ||
1277 | #include <linux/input.h> | |
1278 | static const unsigned short adp5520_keymap[ADP5520_KEYMAPSIZE] = { | |
1279 | [KEY(0, 0)] = KEY_GRAVE, | |
1280 | [KEY(0, 1)] = KEY_1, | |
1281 | [KEY(0, 2)] = KEY_2, | |
1282 | [KEY(0, 3)] = KEY_3, | |
1283 | [KEY(1, 0)] = KEY_4, | |
1284 | [KEY(1, 1)] = KEY_5, | |
1285 | [KEY(1, 2)] = KEY_6, | |
1286 | [KEY(1, 3)] = KEY_7, | |
1287 | [KEY(2, 0)] = KEY_8, | |
1288 | [KEY(2, 1)] = KEY_9, | |
1289 | [KEY(2, 2)] = KEY_0, | |
1290 | [KEY(2, 3)] = KEY_MINUS, | |
1291 | [KEY(3, 0)] = KEY_EQUAL, | |
1292 | [KEY(3, 1)] = KEY_BACKSLASH, | |
1293 | [KEY(3, 2)] = KEY_BACKSPACE, | |
1294 | [KEY(3, 3)] = KEY_ENTER, | |
1295 | }; | |
1296 | ||
1297 | static struct adp5520_keys_platfrom_data adp5520_keys_data = { | |
1298 | .rows_en_mask = ROW_R3 | ROW_R2 | ROW_R1 | ROW_R0, | |
1299 | .cols_en_mask = COL_C3 | COL_C2 | COL_C1 | COL_C0, | |
1300 | .keymap = adp5520_keymap, | |
1301 | .keymapsize = ARRAY_SIZE(adp5520_keymap), | |
1302 | .repeat = 0, | |
1303 | }; | |
1304 | ||
1305 | /* | |
1306 | * ADP5520/5501 Multifuction Device Init Data | |
1307 | */ | |
1308 | ||
1309 | static struct adp5520_subdev_info adp5520_subdevs[] = { | |
1310 | { | |
1311 | .name = "adp5520-backlight", | |
1312 | .id = ID_ADP5520, | |
1313 | .platform_data = &adp5520_backlight_data, | |
1314 | }, | |
1315 | { | |
1316 | .name = "adp5520-led", | |
1317 | .id = ID_ADP5520, | |
1318 | .platform_data = &adp5520_leds_data, | |
1319 | }, | |
1320 | { | |
1321 | .name = "adp5520-gpio", | |
1322 | .id = ID_ADP5520, | |
1323 | .platform_data = &adp5520_gpio_data, | |
1324 | }, | |
1325 | { | |
1326 | .name = "adp5520-keys", | |
1327 | .id = ID_ADP5520, | |
1328 | .platform_data = &adp5520_keys_data, | |
1329 | }, | |
1330 | }; | |
1331 | ||
1332 | static struct adp5520_platform_data adp5520_pdev_data = { | |
1333 | .num_subdevs = ARRAY_SIZE(adp5520_subdevs), | |
1334 | .subdevs = adp5520_subdevs, | |
1335 | }; | |
1336 | ||
1337 | #endif | |
1338 | ||
81d9c7f2 BW |
1339 | static struct i2c_board_info __initdata bfin_i2c_board_info[] = { |
1340 | #if defined(CONFIG_JOYSTICK_AD7142) || defined(CONFIG_JOYSTICK_AD7142_MODULE) | |
1341 | { | |
1342 | I2C_BOARD_INFO("ad7142_joystick", 0x2C), | |
4c94c3e0 | 1343 | .irq = IRQ_PG5, |
81d9c7f2 BW |
1344 | }, |
1345 | #endif | |
ebd58333 | 1346 | #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE) |
81d9c7f2 BW |
1347 | { |
1348 | I2C_BOARD_INFO("pcf8574_lcd", 0x22), | |
81d9c7f2 BW |
1349 | }, |
1350 | #endif | |
204844eb | 1351 | #if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE) |
81d9c7f2 BW |
1352 | { |
1353 | I2C_BOARD_INFO("pcf8574_keypad", 0x27), | |
f5150155 MH |
1354 | .irq = IRQ_PG6, |
1355 | }, | |
1356 | #endif | |
1357 | #if defined(CONFIG_TOUCHSCREEN_AD7879_I2C) || defined(CONFIG_TOUCHSCREEN_AD7879_I2C_MODULE) | |
1358 | { | |
1359 | I2C_BOARD_INFO("ad7879", 0x2F), | |
1360 | .irq = IRQ_PG5, | |
1361 | .platform_data = (void *)&bfin_ad7879_ts_info, | |
81d9c7f2 BW |
1362 | }, |
1363 | #endif | |
51ed9ad7 MH |
1364 | #if defined(CONFIG_KEYBOARD_ADP5588) || defined(CONFIG_KEYBOARD_ADP5588_MODULE) |
1365 | { | |
1366 | I2C_BOARD_INFO("adp5588-keys", 0x34), | |
1367 | .irq = IRQ_PG0, | |
1368 | .platform_data = (void *)&adp5588_kpad_data, | |
1369 | }, | |
1370 | #endif | |
3ea57218 MH |
1371 | #if defined(CONFIG_PMIC_ADP5520) || defined(CONFIG_PMIC_ADP5520_MODULE) |
1372 | { | |
1373 | I2C_BOARD_INFO("pmic-adp5520", 0x32), | |
4f84b6e0 | 1374 | .irq = IRQ_PG0, |
3ea57218 MH |
1375 | .platform_data = (void *)&adp5520_pdev_data, |
1376 | }, | |
1377 | #endif | |
ffc4d8bc MH |
1378 | #if defined(CONFIG_INPUT_ADXL34X_I2C) || defined(CONFIG_INPUT_ADXL34X_I2C_MODULE) |
1379 | { | |
1380 | I2C_BOARD_INFO("adxl34x", 0x53), | |
1381 | .irq = IRQ_PG3, | |
1382 | .platform_data = (void *)&adxl34x_info, | |
1383 | }, | |
1384 | #endif | |
81d9c7f2 | 1385 | }; |
81d9c7f2 | 1386 | |
1394f032 BW |
1387 | #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) |
1388 | static struct platform_device bfin_sport0_uart_device = { | |
1389 | .name = "bfin-sport-uart", | |
1390 | .id = 0, | |
1391 | }; | |
1392 | ||
1393 | static struct platform_device bfin_sport1_uart_device = { | |
1394 | .name = "bfin-sport-uart", | |
1395 | .id = 1, | |
1396 | }; | |
1397 | #endif | |
1398 | ||
c6c4d7bb | 1399 | #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) |
2c8beb2c MH |
1400 | #define CF_IDE_NAND_CARD_USE_HDD_INTERFACE |
1401 | /* #define CF_IDE_NAND_CARD_USE_CF_IN_COMMON_MEMORY_MODE */ | |
c6c4d7bb | 1402 | |
2c8beb2c MH |
1403 | #ifdef CF_IDE_NAND_CARD_USE_HDD_INTERFACE |
1404 | #define PATA_INT IRQ_PF5 | |
c6c4d7bb BW |
1405 | static struct pata_platform_info bfin_pata_platform_data = { |
1406 | .ioport_shift = 1, | |
64e5c512 | 1407 | .irq_flags = IRQF_TRIGGER_HIGH | IRQF_DISABLED, |
c6c4d7bb BW |
1408 | }; |
1409 | ||
1410 | static struct resource bfin_pata_resources[] = { | |
1411 | { | |
1412 | .start = 0x20314020, | |
1413 | .end = 0x2031403F, | |
1414 | .flags = IORESOURCE_MEM, | |
1415 | }, | |
1416 | { | |
1417 | .start = 0x2031401C, | |
1418 | .end = 0x2031401F, | |
1419 | .flags = IORESOURCE_MEM, | |
1420 | }, | |
1421 | { | |
1422 | .start = PATA_INT, | |
1423 | .end = PATA_INT, | |
1424 | .flags = IORESOURCE_IRQ, | |
1425 | }, | |
1426 | }; | |
2c8beb2c MH |
1427 | #elif defined(CF_IDE_NAND_CARD_USE_CF_IN_COMMON_MEMORY_MODE) |
1428 | static struct pata_platform_info bfin_pata_platform_data = { | |
1429 | .ioport_shift = 0, | |
1430 | }; | |
648882d9 MH |
1431 | /* CompactFlash Storage Card Memory Mapped Adressing |
1432 | * /REG = A11 = 1 | |
1433 | */ | |
2c8beb2c MH |
1434 | static struct resource bfin_pata_resources[] = { |
1435 | { | |
648882d9 MH |
1436 | .start = 0x20211800, |
1437 | .end = 0x20211807, | |
2c8beb2c MH |
1438 | .flags = IORESOURCE_MEM, |
1439 | }, | |
1440 | { | |
648882d9 MH |
1441 | .start = 0x2021180E, /* Device Ctl */ |
1442 | .end = 0x2021180E, | |
2c8beb2c MH |
1443 | .flags = IORESOURCE_MEM, |
1444 | }, | |
1445 | }; | |
1446 | #endif | |
c6c4d7bb BW |
1447 | |
1448 | static struct platform_device bfin_pata_device = { | |
1449 | .name = "pata_platform", | |
1450 | .id = -1, | |
1451 | .num_resources = ARRAY_SIZE(bfin_pata_resources), | |
1452 | .resource = bfin_pata_resources, | |
1453 | .dev = { | |
1454 | .platform_data = &bfin_pata_platform_data, | |
1455 | } | |
1456 | }; | |
1457 | #endif | |
1458 | ||
14b03204 MH |
1459 | static const unsigned int cclk_vlev_datasheet[] = |
1460 | { | |
1461 | VRPAIR(VLEV_085, 250000000), | |
1462 | VRPAIR(VLEV_090, 376000000), | |
1463 | VRPAIR(VLEV_095, 426000000), | |
1464 | VRPAIR(VLEV_100, 426000000), | |
1465 | VRPAIR(VLEV_105, 476000000), | |
1466 | VRPAIR(VLEV_110, 476000000), | |
1467 | VRPAIR(VLEV_115, 476000000), | |
1468 | VRPAIR(VLEV_120, 500000000), | |
1469 | VRPAIR(VLEV_125, 533000000), | |
1470 | VRPAIR(VLEV_130, 600000000), | |
1471 | }; | |
1472 | ||
1473 | static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { | |
1474 | .tuple_tab = cclk_vlev_datasheet, | |
1475 | .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), | |
1476 | .vr_settling_time = 25 /* us */, | |
1477 | }; | |
1478 | ||
1479 | static struct platform_device bfin_dpmc = { | |
1480 | .name = "bfin dpmc", | |
1481 | .dev = { | |
1482 | .platform_data = &bfin_dmpc_vreg_data, | |
1483 | }, | |
1484 | }; | |
1485 | ||
1394f032 | 1486 | static struct platform_device *stamp_devices[] __initdata = { |
14b03204 MH |
1487 | |
1488 | &bfin_dpmc, | |
1489 | ||
1394f032 BW |
1490 | #if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE) |
1491 | &bfin_pcmcia_cf_device, | |
1492 | #endif | |
1493 | ||
1494 | #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) | |
1495 | &rtc_device, | |
1496 | #endif | |
1497 | ||
1498 | #if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE) | |
1499 | &sl811_hcd_device, | |
1500 | #endif | |
1501 | ||
1502 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) | |
1503 | &isp1362_hcd_device, | |
1504 | #endif | |
1505 | ||
3f375690 MH |
1506 | #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) |
1507 | &bfin_isp1760_device, | |
1508 | #endif | |
1509 | ||
1394f032 BW |
1510 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) |
1511 | &smc91x_device, | |
1512 | #endif | |
1513 | ||
f40d24d9 AL |
1514 | #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE) |
1515 | &dm9000_device, | |
1516 | #endif | |
1517 | ||
561cc18b MH |
1518 | #if defined(CONFIG_AX88180) || defined(CONFIG_AX88180_MODULE) |
1519 | &ax88180_device, | |
1520 | #endif | |
1521 | ||
1394f032 | 1522 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) |
65319628 | 1523 | &bfin_mii_bus, |
1394f032 BW |
1524 | &bfin_mac_device, |
1525 | #endif | |
1526 | ||
1527 | #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) | |
1528 | &net2272_bfin_device, | |
1529 | #endif | |
1530 | ||
1531 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | |
c6c4d7bb | 1532 | &bfin_spi0_device, |
1394f032 BW |
1533 | #endif |
1534 | ||
1e9aa955 CC |
1535 | #if defined(CONFIG_SPI_BFIN_SPORT) || defined(CONFIG_SPI_BFIN_SPORT_MODULE) |
1536 | &bfin_sport_spi0_device, | |
1537 | &bfin_sport_spi1_device, | |
1538 | #endif | |
1539 | ||
1394f032 BW |
1540 | #if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE) |
1541 | &bfin_fb_device, | |
1542 | #endif | |
1543 | ||
2043f3f7 MH |
1544 | #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) |
1545 | &bfin_lq035q1_device, | |
1546 | #endif | |
1547 | ||
c6c4d7bb BW |
1548 | #if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE) |
1549 | &bfin_fb_adv7393_device, | |
1550 | #endif | |
1551 | ||
1394f032 BW |
1552 | #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) |
1553 | &bfin_uart_device, | |
1554 | #endif | |
1555 | ||
5be36d22 | 1556 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
42bd8bcb GY |
1557 | #ifdef CONFIG_BFIN_SIR0 |
1558 | &bfin_sir0_device, | |
1559 | #endif | |
1560 | #ifdef CONFIG_BFIN_SIR1 | |
1561 | &bfin_sir1_device, | |
1562 | #endif | |
5be36d22 GY |
1563 | #endif |
1564 | ||
1394f032 BW |
1565 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) |
1566 | &i2c_bfin_twi_device, | |
1567 | #endif | |
1568 | ||
1569 | #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) | |
1570 | &bfin_sport0_uart_device, | |
1571 | &bfin_sport1_uart_device, | |
1572 | #endif | |
c6c4d7bb BW |
1573 | |
1574 | #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) | |
1575 | &bfin_pata_device, | |
1576 | #endif | |
2463ef22 MH |
1577 | |
1578 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) | |
1579 | &bfin_device_gpiokeys, | |
1580 | #endif | |
cad2ab65 MF |
1581 | |
1582 | &bfin_gpios_device, | |
793dc27b | 1583 | |
fc68911e MF |
1584 | #if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE) |
1585 | &bfin_async_nand_device, | |
1586 | #endif | |
1587 | ||
793dc27b | 1588 | #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) |
de8c43f2 | 1589 | &stamp_flash_device, |
793dc27b | 1590 | #endif |
1394f032 BW |
1591 | }; |
1592 | ||
1593 | static int __init stamp_init(void) | |
1594 | { | |
b85d858b | 1595 | printk(KERN_INFO "%s(): registering device resources\n", __func__); |
81d9c7f2 BW |
1596 | i2c_register_board_info(0, bfin_i2c_board_info, |
1597 | ARRAY_SIZE(bfin_i2c_board_info)); | |
fc68911e | 1598 | bfin_plat_nand_init(); |
1394f032 | 1599 | platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices)); |
5bda2723 | 1600 | spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); |
c6c4d7bb | 1601 | |
648882d9 MH |
1602 | #if (defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)) \ |
1603 | && defined(PATA_INT) | |
c6c4d7bb BW |
1604 | irq_desc[PATA_INT].status |= IRQ_NOAUTOEN; |
1605 | #endif | |
81d9c7f2 | 1606 | |
1394f032 BW |
1607 | return 0; |
1608 | } | |
1609 | ||
1610 | arch_initcall(stamp_init); | |
c6c4d7bb BW |
1611 | |
1612 | void native_machine_restart(char *cmd) | |
1613 | { | |
1614 | /* workaround reboot hang when booting from SPI */ | |
1615 | if ((bfin_read_SYSCR() & 0x7) == 0x3) | |
b52dae31 | 1616 | bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS); |
c6c4d7bb | 1617 | } |
137b1529 MF |
1618 | |
1619 | /* | |
1620 | * Currently the MAC address is saved in Flash by U-Boot | |
1621 | */ | |
1622 | #define FLASH_MAC 0x203f0000 | |
9862cc52 | 1623 | void bfin_get_ether_addr(char *addr) |
137b1529 MF |
1624 | { |
1625 | *(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC); | |
1626 | *(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4); | |
1627 | } | |
9862cc52 | 1628 | EXPORT_SYMBOL(bfin_get_ether_addr); |