Blackfin arch: rename MAX_BLACKFIN_DMA_CHANNEL to MAX_DMA_CHANNELS to match everyone...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / blackfin / mach-bf537 / boards / stamp.c
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1/*
2 * File: arch/blackfin/mach-bf537/boards/stamp.c
3 * Based on: arch/blackfin/mach-bf533/boards/ezkit.c
4 * Author: Aidan Williams <aidan@nicta.com.au>
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2005 National ICT Australia (NICTA)
11 * Copyright 2004-2006 Analog Devices Inc.
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see the file COPYING, or write
27 * to the Free Software Foundation, Inc.,
28 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 */
30
31#include <linux/device.h>
fc68911e 32#include <linux/kernel.h>
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33#include <linux/platform_device.h>
34#include <linux/mtd/mtd.h>
fc68911e 35#include <linux/mtd/nand.h>
1394f032 36#include <linux/mtd/partitions.h>
fc68911e 37#include <linux/mtd/plat-ram.h>
de8c43f2 38#include <linux/mtd/physmap.h>
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39#include <linux/spi/spi.h>
40#include <linux/spi/flash.h>
41#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
f02bcec5 42#include <linux/usb/isp1362.h>
1394f032 43#endif
0a87e3e9 44#include <linux/ata_platform.h>
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45#include <linux/irq.h>
46#include <linux/interrupt.h>
81d9c7f2 47#include <linux/i2c.h>
27f5d75a 48#include <linux/usb/sl811.h>
c6c4d7bb 49#include <asm/dma.h>
1f83b8f1 50#include <asm/bfin5xx_spi.h>
c6c4d7bb 51#include <asm/reboot.h>
5d448dd5 52#include <asm/portmux.h>
14b03204 53#include <asm/dpmc.h>
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54
55/*
56 * Name the Board for the /proc/cpuinfo
57 */
fe85cad2 58const char bfin_board_name[] = "ADI BF537-STAMP";
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59
60/*
61 * Driver needs to know address, irq and flag pin.
62 */
63
1394f032 64#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
3f375690
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65#include <linux/usb/isp1760.h>
66static struct resource bfin_isp1760_resources[] = {
1394f032 67 [0] = {
3f375690
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68 .start = 0x203C0000,
69 .end = 0x203C0000 + 0x000fffff,
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70 .flags = IORESOURCE_MEM,
71 },
72 [1] = {
3f375690
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73 .start = IRQ_PF7,
74 .end = IRQ_PF7,
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75 .flags = IORESOURCE_IRQ,
76 },
77};
78
3f375690
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79static struct isp1760_platform_data isp1760_priv = {
80 .is_isp1761 = 0,
81 .port1_disable = 0,
82 .bus_width_16 = 1,
83 .port1_otg = 0,
84 .analog_oc = 0,
85 .dack_polarity_high = 0,
86 .dreq_polarity_high = 0,
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87};
88
3f375690
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89static struct platform_device bfin_isp1760_device = {
90 .name = "isp1760-hcd",
91 .id = 0,
92 .dev = {
93 .platform_data = &isp1760_priv,
94 },
95 .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
96 .resource = bfin_isp1760_resources,
1394f032 97};
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98#endif
99
2463ef22
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100#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
101#include <linux/input.h>
102#include <linux/gpio_keys.h>
103
104static struct gpio_keys_button bfin_gpio_keys_table[] = {
105 {BTN_0, GPIO_PF2, 1, "gpio-keys: BTN0"},
106 {BTN_1, GPIO_PF3, 1, "gpio-keys: BTN1"},
107 {BTN_2, GPIO_PF4, 1, "gpio-keys: BTN2"},
108 {BTN_3, GPIO_PF5, 1, "gpio-keys: BTN3"},
109};
110
111static struct gpio_keys_platform_data bfin_gpio_keys_data = {
112 .buttons = bfin_gpio_keys_table,
113 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
114};
115
116static struct platform_device bfin_device_gpiokeys = {
117 .name = "gpio-keys",
118 .dev = {
119 .platform_data = &bfin_gpio_keys_data,
120 },
121};
122#endif
123
cad2ab65
MF
124static struct resource bfin_gpios_resources = {
125 .start = 0,
126 .end = MAX_BLACKFIN_GPIOS - 1,
127 .flags = IORESOURCE_IRQ,
128};
129
130static struct platform_device bfin_gpios_device = {
131 .name = "simple-gpio",
132 .id = -1,
133 .num_resources = 1,
134 .resource = &bfin_gpios_resources,
135};
136
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137#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
138static struct resource bfin_pcmcia_cf_resources[] = {
139 {
140 .start = 0x20310000, /* IO PORT */
141 .end = 0x20312000,
142 .flags = IORESOURCE_MEM,
1f83b8f1 143 }, {
d2d50aa9 144 .start = 0x20311000, /* Attribute Memory */
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145 .end = 0x20311FFF,
146 .flags = IORESOURCE_MEM,
1f83b8f1 147 }, {
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148 .start = IRQ_PF4,
149 .end = IRQ_PF4,
150 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
1f83b8f1 151 }, {
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152 .start = 6, /* Card Detect PF6 */
153 .end = 6,
154 .flags = IORESOURCE_IRQ,
155 },
156};
157
158static struct platform_device bfin_pcmcia_cf_device = {
159 .name = "bfin_cf_pcmcia",
160 .id = -1,
161 .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
162 .resource = bfin_pcmcia_cf_resources,
163};
164#endif
165
166#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
167static struct platform_device rtc_device = {
168 .name = "rtc-bfin",
169 .id = -1,
170};
171#endif
172
173#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
174static struct resource smc91x_resources[] = {
175 {
176 .name = "smc91x-regs",
177 .start = 0x20300300,
178 .end = 0x20300300 + 16,
179 .flags = IORESOURCE_MEM,
1f83b8f1 180 }, {
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181
182 .start = IRQ_PF7,
183 .end = IRQ_PF7,
184 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
185 },
186};
187static struct platform_device smc91x_device = {
188 .name = "smc91x",
189 .id = 0,
190 .num_resources = ARRAY_SIZE(smc91x_resources),
191 .resource = smc91x_resources,
192};
193#endif
194
f40d24d9
AL
195#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
196static struct resource dm9000_resources[] = {
197 [0] = {
198 .start = 0x203FB800,
199 .end = 0x203FB800 + 8,
200 .flags = IORESOURCE_MEM,
201 },
202 [1] = {
203 .start = IRQ_PF9,
204 .end = IRQ_PF9,
205 .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
206 },
207};
208
209static struct platform_device dm9000_device = {
210 .name = "dm9000",
211 .id = -1,
212 .num_resources = ARRAY_SIZE(dm9000_resources),
213 .resource = dm9000_resources,
214};
215#endif
216
561cc18b
MH
217#if defined(CONFIG_AX88180) || defined(CONFIG_AX88180_MODULE)
218static struct resource ax88180_resources[] = {
219 [0] = {
220 .start = 0x20300000,
221 .end = 0x20300000 + 0x8000,
222 .flags = IORESOURCE_MEM,
223 },
224 [1] = {
225 .start = IRQ_PF7,
226 .end = IRQ_PF7,
227 .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL),
228 },
229};
230
231static struct platform_device ax88180_device = {
232 .name = "ax88180",
233 .id = -1,
234 .num_resources = ARRAY_SIZE(ax88180_resources),
235 .resource = ax88180_resources,
236};
237#endif
238
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239#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
240static struct resource sl811_hcd_resources[] = {
241 {
242 .start = 0x20340000,
243 .end = 0x20340000,
244 .flags = IORESOURCE_MEM,
1f83b8f1 245 }, {
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246 .start = 0x20340004,
247 .end = 0x20340004,
248 .flags = IORESOURCE_MEM,
1f83b8f1 249 }, {
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250 .start = CONFIG_USB_SL811_BFIN_IRQ,
251 .end = CONFIG_USB_SL811_BFIN_IRQ,
252 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
253 },
254};
255
256#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
257void sl811_port_power(struct device *dev, int is_on)
258{
c6c4d7bb 259 gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS");
acbcd263 260 gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS, is_on);
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261}
262#endif
263
264static struct sl811_platform_data sl811_priv = {
265 .potpg = 10,
266 .power = 250, /* == 500mA */
267#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
268 .port_power = &sl811_port_power,
269#endif
270};
271
272static struct platform_device sl811_hcd_device = {
273 .name = "sl811-hcd",
274 .id = 0,
275 .dev = {
276 .platform_data = &sl811_priv,
277 },
278 .num_resources = ARRAY_SIZE(sl811_hcd_resources),
279 .resource = sl811_hcd_resources,
280};
281#endif
282
283#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
284static struct resource isp1362_hcd_resources[] = {
285 {
286 .start = 0x20360000,
287 .end = 0x20360000,
288 .flags = IORESOURCE_MEM,
1f83b8f1 289 }, {
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290 .start = 0x20360004,
291 .end = 0x20360004,
292 .flags = IORESOURCE_MEM,
1f83b8f1 293 }, {
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294 .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
295 .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
296 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
297 },
298};
299
300static struct isp1362_platform_data isp1362_priv = {
301 .sel15Kres = 1,
302 .clknotstop = 0,
303 .oc_enable = 0,
304 .int_act_high = 0,
305 .int_edge_triggered = 0,
306 .remote_wakeup_connected = 0,
307 .no_power_switching = 1,
308 .power_switching_mode = 0,
309};
310
311static struct platform_device isp1362_hcd_device = {
312 .name = "isp1362-hcd",
313 .id = 0,
314 .dev = {
315 .platform_data = &isp1362_priv,
316 },
317 .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
318 .resource = isp1362_hcd_resources,
319};
320#endif
321
322#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
323static struct platform_device bfin_mac_device = {
324 .name = "bfin_mac",
325};
326#endif
327
328#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
329static struct resource net2272_bfin_resources[] = {
330 {
331 .start = 0x20300000,
332 .end = 0x20300000 + 0x100,
333 .flags = IORESOURCE_MEM,
1f83b8f1 334 }, {
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335 .start = IRQ_PF7,
336 .end = IRQ_PF7,
337 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
338 },
339};
340
341static struct platform_device net2272_bfin_device = {
342 .name = "net2272",
343 .id = -1,
344 .num_resources = ARRAY_SIZE(net2272_bfin_resources),
345 .resource = net2272_bfin_resources,
346};
347#endif
348
fc68911e
MF
349#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
350#ifdef CONFIG_MTD_PARTITIONS
351const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL };
352
353static struct mtd_partition bfin_plat_nand_partitions[] = {
354 {
aa582977 355 .name = "linux kernel(nand)",
fc68911e
MF
356 .size = 0x400000,
357 .offset = 0,
358 }, {
aa582977 359 .name = "file system(nand)",
fc68911e
MF
360 .size = MTDPART_SIZ_FULL,
361 .offset = MTDPART_OFS_APPEND,
362 },
363};
364#endif
365
366#define BFIN_NAND_PLAT_CLE 2
367#define BFIN_NAND_PLAT_ALE 1
368static void bfin_plat_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
369{
370 struct nand_chip *this = mtd->priv;
371
372 if (cmd == NAND_CMD_NONE)
373 return;
374
375 if (ctrl & NAND_CLE)
376 writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_CLE));
377 else
378 writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_ALE));
379}
380
381#define BFIN_NAND_PLAT_READY GPIO_PF3
382static int bfin_plat_nand_dev_ready(struct mtd_info *mtd)
383{
384 return gpio_get_value(BFIN_NAND_PLAT_READY);
385}
386
387static struct platform_nand_data bfin_plat_nand_data = {
388 .chip = {
389 .chip_delay = 30,
390#ifdef CONFIG_MTD_PARTITIONS
391 .part_probe_types = part_probes,
392 .partitions = bfin_plat_nand_partitions,
393 .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions),
394#endif
395 },
396 .ctrl = {
397 .cmd_ctrl = bfin_plat_nand_cmd_ctrl,
398 .dev_ready = bfin_plat_nand_dev_ready,
399 },
400};
401
402#define MAX(x, y) (x > y ? x : y)
403static struct resource bfin_plat_nand_resources = {
404 .start = 0x20212000,
405 .end = 0x20212000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)),
406 .flags = IORESOURCE_IO,
407};
408
409static struct platform_device bfin_async_nand_device = {
410 .name = "gen_nand",
411 .id = -1,
412 .num_resources = 1,
413 .resource = &bfin_plat_nand_resources,
414 .dev = {
415 .platform_data = &bfin_plat_nand_data,
416 },
417};
418
419static void bfin_plat_nand_init(void)
420{
421 gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat");
422}
423#else
424static void bfin_plat_nand_init(void) {}
425#endif
426
793dc27b 427#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
de8c43f2
MF
428static struct mtd_partition stamp_partitions[] = {
429 {
aa582977 430 .name = "bootloader(nor)",
edf05641 431 .size = 0x40000,
de8c43f2
MF
432 .offset = 0,
433 }, {
aa582977 434 .name = "linux kernel(nor)",
de8c43f2
MF
435 .size = 0xE0000,
436 .offset = MTDPART_OFS_APPEND,
437 }, {
aa582977 438 .name = "file system(nor)",
edf05641 439 .size = 0x400000 - 0x40000 - 0xE0000 - 0x10000,
de8c43f2
MF
440 .offset = MTDPART_OFS_APPEND,
441 }, {
aa582977 442 .name = "MAC Address(nor)",
de8c43f2
MF
443 .size = MTDPART_SIZ_FULL,
444 .offset = 0x3F0000,
445 .mask_flags = MTD_WRITEABLE,
446 }
447};
448
449static struct physmap_flash_data stamp_flash_data = {
450 .width = 2,
451 .parts = stamp_partitions,
452 .nr_parts = ARRAY_SIZE(stamp_partitions),
453};
454
455static struct resource stamp_flash_resource = {
456 .start = 0x20000000,
457 .end = 0x203fffff,
458 .flags = IORESOURCE_MEM,
459};
460
461static struct platform_device stamp_flash_device = {
462 .name = "physmap-flash",
463 .id = 0,
464 .dev = {
465 .platform_data = &stamp_flash_data,
466 },
467 .num_resources = 1,
468 .resource = &stamp_flash_resource,
469};
793dc27b 470#endif
de8c43f2 471
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472#if defined(CONFIG_MTD_M25P80) \
473 || defined(CONFIG_MTD_M25P80_MODULE)
474static struct mtd_partition bfin_spi_flash_partitions[] = {
475 {
aa582977 476 .name = "bootloader(spi)",
edf05641 477 .size = 0x00040000,
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478 .offset = 0,
479 .mask_flags = MTD_CAP_ROM
1f83b8f1 480 }, {
aa582977 481 .name = "linux kernel(spi)",
1394f032 482 .size = 0xe0000,
edf05641 483 .offset = MTDPART_OFS_APPEND,
1f83b8f1 484 }, {
aa582977 485 .name = "file system(spi)",
edf05641
MF
486 .size = MTDPART_SIZ_FULL,
487 .offset = MTDPART_OFS_APPEND,
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488 }
489};
490
491static struct flash_platform_data bfin_spi_flash_data = {
492 .name = "m25p80",
493 .parts = bfin_spi_flash_partitions,
494 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
88a8078b 495 /* .type = "m25p64", */
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496};
497
498/* SPI flash chip (m25p64) */
499static struct bfin5xx_spi_chip spi_flash_chip_info = {
500 .enable_dma = 0, /* use dma transfer with this chip*/
501 .bits_per_word = 8,
502};
503#endif
504
505#if defined(CONFIG_SPI_ADC_BF533) \
506 || defined(CONFIG_SPI_ADC_BF533_MODULE)
507/* SPI ADC chip */
508static struct bfin5xx_spi_chip spi_adc_chip_info = {
509 .enable_dma = 1, /* use dma transfer with this chip*/
510 .bits_per_word = 16,
511};
512#endif
513
514#if defined(CONFIG_SND_BLACKFIN_AD1836) \
515 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
516static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
517 .enable_dma = 0,
518 .bits_per_word = 16,
519};
520#endif
521
522#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
523static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
524 .enable_dma = 0,
525 .bits_per_word = 16,
526};
527#endif
528
529#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
530static struct bfin5xx_spi_chip spi_mmc_chip_info = {
4989dbc1 531 .enable_dma = 0,
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532 .bits_per_word = 8,
533};
534#endif
535
536#if defined(CONFIG_PBX)
537static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
538 .ctl_reg = 0x4, /* send zero */
539 .enable_dma = 0,
540 .bits_per_word = 8,
541 .cs_change_per_word = 1,
542};
543#endif
544
1394f032 545#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
46aa04f9 546#include <linux/spi/ad7877.h>
1394f032 547static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
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548 .enable_dma = 0,
549 .bits_per_word = 16,
550};
551
552static const struct ad7877_platform_data bfin_ad7877_ts_info = {
553 .model = 7877,
554 .vref_delay_usecs = 50, /* internal, no capacitor */
555 .x_plate_ohms = 419,
556 .y_plate_ohms = 486,
557 .pressure_max = 1000,
558 .pressure_min = 0,
559 .stopacq_polarity = 1,
560 .first_conversion_delay = 3,
561 .acquisition_time = 1,
562 .averaging = 1,
563 .pen_down_acc_interval = 1,
564};
565#endif
566
46aa04f9
MH
567#if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
568#include <linux/spi/ad7879.h>
46aa04f9
MH
569static const struct ad7879_platform_data bfin_ad7879_ts_info = {
570 .model = 7879, /* Model = AD7879 */
571 .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
572 .pressure_max = 10000,
573 .pressure_min = 0,
574 .first_conversion_delay = 3, /* wait 512us before do a first conversion */
575 .acquisition_time = 1, /* 4us acquisition time per sample */
576 .median = 2, /* do 8 measurements */
577 .averaging = 1, /* take the average of 4 middle samples */
578 .pen_down_acc_interval = 255, /* 9.4 ms */
579 .gpio_output = 1, /* configure AUX/VBAT/GPIO as GPIO output */
580 .gpio_default = 1, /* During initialization set GPIO = HIGH */
581};
582#endif
583
f5150155
MH
584#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
585static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
586 .enable_dma = 0,
587 .bits_per_word = 16,
588};
589#endif
590
6e668936
MH
591#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
592static struct bfin5xx_spi_chip spidev_chip_info = {
593 .enable_dma = 0,
594 .bits_per_word = 8,
595};
596#endif
597
2043f3f7
MH
598#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
599static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
600 .enable_dma = 0,
601 .bits_per_word = 8,
602};
603#endif
604
8e9d5c7d
MH
605#if defined(CONFIG_MTD_DATAFLASH) \
606 || defined(CONFIG_MTD_DATAFLASH_MODULE)
ceac2651
MH
607
608static struct mtd_partition bfin_spi_dataflash_partitions[] = {
609 {
610 .name = "bootloader(spi)",
611 .size = 0x00040000,
612 .offset = 0,
613 .mask_flags = MTD_CAP_ROM
614 }, {
615 .name = "linux kernel(spi)",
616 .size = 0xe0000,
617 .offset = MTDPART_OFS_APPEND,
618 }, {
619 .name = "file system(spi)",
620 .size = MTDPART_SIZ_FULL,
621 .offset = MTDPART_OFS_APPEND,
622 }
623};
624
625static struct flash_platform_data bfin_spi_dataflash_data = {
626 .name = "SPI Dataflash",
627 .parts = bfin_spi_dataflash_partitions,
628 .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
629};
630
8e9d5c7d
MH
631/* DataFlash chip */
632static struct bfin5xx_spi_chip data_flash_chip_info = {
633 .enable_dma = 0, /* use dma transfer with this chip*/
634 .bits_per_word = 8,
635};
636#endif
637
1394f032
BW
638static struct spi_board_info bfin_spi_board_info[] __initdata = {
639#if defined(CONFIG_MTD_M25P80) \
640 || defined(CONFIG_MTD_M25P80_MODULE)
641 {
642 /* the modalias must be the same as spi device driver name */
643 .modalias = "m25p80", /* Name of spi_driver for this device */
644 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 645 .bus_num = 0, /* Framework bus number */
1394f032
BW
646 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
647 .platform_data = &bfin_spi_flash_data,
648 .controller_data = &spi_flash_chip_info,
649 .mode = SPI_MODE_3,
650 },
651#endif
8e9d5c7d
MH
652#if defined(CONFIG_MTD_DATAFLASH) \
653 || defined(CONFIG_MTD_DATAFLASH_MODULE)
654 { /* DataFlash chip */
655 .modalias = "mtd_dataflash",
ceac2651 656 .max_speed_hz = 33250000, /* max spi clock (SCK) speed in HZ */
8e9d5c7d
MH
657 .bus_num = 0, /* Framework bus number */
658 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
ceac2651 659 .platform_data = &bfin_spi_dataflash_data,
8e9d5c7d
MH
660 .controller_data = &data_flash_chip_info,
661 .mode = SPI_MODE_3,
662 },
663#endif
1394f032
BW
664#if defined(CONFIG_SPI_ADC_BF533) \
665 || defined(CONFIG_SPI_ADC_BF533_MODULE)
666 {
667 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
668 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 669 .bus_num = 0, /* Framework bus number */
1394f032
BW
670 .chip_select = 1, /* Framework chip select. */
671 .platform_data = NULL, /* No spi_driver specific config */
672 .controller_data = &spi_adc_chip_info,
673 },
674#endif
675
676#if defined(CONFIG_SND_BLACKFIN_AD1836) \
677 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
678 {
679 .modalias = "ad1836-spi",
680 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 681 .bus_num = 0,
1394f032
BW
682 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
683 .controller_data = &ad1836_spi_chip_info,
684 },
685#endif
686#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
687 {
688 .modalias = "ad9960-spi",
689 .max_speed_hz = 10000000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 690 .bus_num = 0,
1394f032
BW
691 .chip_select = 1,
692 .controller_data = &ad9960_spi_chip_info,
693 },
694#endif
695#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
696 {
697 .modalias = "spi_mmc_dummy",
111cf97d 698 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 699 .bus_num = 0,
1394f032
BW
700 .chip_select = 0,
701 .platform_data = NULL,
702 .controller_data = &spi_mmc_chip_info,
703 .mode = SPI_MODE_3,
704 },
705 {
706 .modalias = "spi_mmc",
111cf97d 707 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 708 .bus_num = 0,
1394f032
BW
709 .chip_select = CONFIG_SPI_MMC_CS_CHAN,
710 .platform_data = NULL,
711 .controller_data = &spi_mmc_chip_info,
712 .mode = SPI_MODE_3,
713 },
714#endif
715#if defined(CONFIG_PBX)
716 {
1f83b8f1
MF
717 .modalias = "fxs-spi",
718 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb
BW
719 .bus_num = 0,
720 .chip_select = 8 - CONFIG_J11_JUMPER,
1f83b8f1 721 .controller_data = &spi_si3xxx_chip_info,
1394f032
BW
722 .mode = SPI_MODE_3,
723 },
724 {
1f83b8f1
MF
725 .modalias = "fxo-spi",
726 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb
BW
727 .bus_num = 0,
728 .chip_select = 8 - CONFIG_J19_JUMPER,
1f83b8f1 729 .controller_data = &spi_si3xxx_chip_info,
1394f032
BW
730 .mode = SPI_MODE_3,
731 },
732#endif
1394f032
BW
733#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
734 {
735 .modalias = "ad7877",
736 .platform_data = &bfin_ad7877_ts_info,
737 .irq = IRQ_PF6,
738 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
c7d48966 739 .bus_num = 0,
1394f032
BW
740 .chip_select = 1,
741 .controller_data = &spi_ad7877_chip_info,
742 },
743#endif
f5150155 744#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
46aa04f9
MH
745 {
746 .modalias = "ad7879",
747 .platform_data = &bfin_ad7879_ts_info,
748 .irq = IRQ_PF7,
749 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
750 .bus_num = 0,
751 .chip_select = 1,
752 .controller_data = &spi_ad7879_chip_info,
753 .mode = SPI_CPHA | SPI_CPOL,
754 },
755#endif
6e668936
MH
756#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
757 {
758 .modalias = "spidev",
759 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
760 .bus_num = 0,
761 .chip_select = 1,
762 .controller_data = &spidev_chip_info,
763 },
764#endif
2043f3f7
MH
765#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
766 {
767 .modalias = "bfin-lq035q1-spi",
768 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
769 .bus_num = 0,
46aa04f9 770 .chip_select = 2,
2043f3f7
MH
771 .controller_data = &lq035q1_spi_chip_info,
772 .mode = SPI_CPHA | SPI_CPOL,
773 },
774#endif
1394f032
BW
775};
776
5bda2723 777#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
1394f032 778/* SPI controller data */
c6c4d7bb 779static struct bfin5xx_spi_master bfin_spi0_info = {
1394f032
BW
780 .num_chipselect = 8,
781 .enable_dma = 1, /* master has the ability to do dma transfer */
5d448dd5 782 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1394f032
BW
783};
784
c6c4d7bb
BW
785/* SPI (0) */
786static struct resource bfin_spi0_resource[] = {
787 [0] = {
788 .start = SPI0_REGBASE,
789 .end = SPI0_REGBASE + 0xFF,
790 .flags = IORESOURCE_MEM,
791 },
792 [1] = {
793 .start = CH_SPI,
794 .end = CH_SPI,
795 .flags = IORESOURCE_IRQ,
796 },
797};
798
799static struct platform_device bfin_spi0_device = {
800 .name = "bfin-spi",
801 .id = 0, /* Bus number */
802 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
803 .resource = bfin_spi0_resource,
1394f032 804 .dev = {
c6c4d7bb 805 .platform_data = &bfin_spi0_info, /* Passed to driver */
1394f032
BW
806 },
807};
808#endif /* spi master and devices */
809
810#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
811static struct platform_device bfin_fb_device = {
c6c4d7bb
BW
812 .name = "bf537-lq035",
813};
814#endif
815
816#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
817static struct platform_device bfin_fb_adv7393_device = {
818 .name = "bfin-adv7393",
1394f032
BW
819};
820#endif
821
2043f3f7
MH
822#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
823#include <asm/bfin-lq035q1.h>
824
825static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
826 .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
46aa04f9 827 .use_bl = 0, /* let something else control the LCD Blacklight */
2043f3f7
MH
828 .gpio_bl = GPIO_PF7,
829};
830
831static struct resource bfin_lq035q1_resources[] = {
832 {
833 .start = IRQ_PPI_ERROR,
834 .end = IRQ_PPI_ERROR,
835 .flags = IORESOURCE_IRQ,
836 },
837};
838
839static struct platform_device bfin_lq035q1_device = {
840 .name = "bfin-lq035q1",
841 .id = -1,
842 .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
843 .resource = bfin_lq035q1_resources,
844 .dev = {
845 .platform_data = &bfin_lq035q1_data,
846 },
847};
848#endif
849
1394f032
BW
850#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
851static struct resource bfin_uart_resources[] = {
233b28a9 852#ifdef CONFIG_SERIAL_BFIN_UART0
1394f032
BW
853 {
854 .start = 0xFFC00400,
855 .end = 0xFFC004FF,
856 .flags = IORESOURCE_MEM,
233b28a9
SZ
857 },
858#endif
859#ifdef CONFIG_SERIAL_BFIN_UART1
860 {
1394f032
BW
861 .start = 0xFFC02000,
862 .end = 0xFFC020FF,
863 .flags = IORESOURCE_MEM,
864 },
233b28a9 865#endif
1394f032
BW
866};
867
868static struct platform_device bfin_uart_device = {
869 .name = "bfin-uart",
870 .id = 1,
871 .num_resources = ARRAY_SIZE(bfin_uart_resources),
872 .resource = bfin_uart_resources,
873};
874#endif
875
5be36d22
GY
876#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
877static struct resource bfin_sir_resources[] = {
878#ifdef CONFIG_BFIN_SIR0
879 {
880 .start = 0xFFC00400,
881 .end = 0xFFC004FF,
882 .flags = IORESOURCE_MEM,
883 },
884#endif
885#ifdef CONFIG_BFIN_SIR1
886 {
887 .start = 0xFFC02000,
888 .end = 0xFFC020FF,
889 .flags = IORESOURCE_MEM,
890 },
891#endif
892};
893
894static struct platform_device bfin_sir_device = {
895 .name = "bfin_sir",
896 .id = 0,
897 .num_resources = ARRAY_SIZE(bfin_sir_resources),
898 .resource = bfin_sir_resources,
899};
900#endif
901
1394f032 902#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
c6c4d7bb
BW
903static struct resource bfin_twi0_resource[] = {
904 [0] = {
905 .start = TWI0_REGBASE,
906 .end = TWI0_REGBASE,
907 .flags = IORESOURCE_MEM,
908 },
909 [1] = {
910 .start = IRQ_TWI,
911 .end = IRQ_TWI,
912 .flags = IORESOURCE_IRQ,
913 },
914};
915
1394f032
BW
916static struct platform_device i2c_bfin_twi_device = {
917 .name = "i2c-bfin-twi",
918 .id = 0,
c6c4d7bb
BW
919 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
920 .resource = bfin_twi0_resource,
1394f032
BW
921};
922#endif
923
81d9c7f2
BW
924#ifdef CONFIG_I2C_BOARDINFO
925static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
926#if defined(CONFIG_JOYSTICK_AD7142) || defined(CONFIG_JOYSTICK_AD7142_MODULE)
927 {
928 I2C_BOARD_INFO("ad7142_joystick", 0x2C),
f5150155 929 .irq = IRQ_PF5,
81d9c7f2
BW
930 },
931#endif
932#if defined(CONFIG_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE)
933 {
934 I2C_BOARD_INFO("pcf8574_lcd", 0x22),
81d9c7f2
BW
935 },
936#endif
937#if defined(CONFIG_TWI_KEYPAD) || defined(CONFIG_TWI_KEYPAD_MODULE)
938 {
939 I2C_BOARD_INFO("pcf8574_keypad", 0x27),
f5150155
MH
940 .irq = IRQ_PG6,
941 },
942#endif
943#if defined(CONFIG_TOUCHSCREEN_AD7879_I2C) || defined(CONFIG_TOUCHSCREEN_AD7879_I2C_MODULE)
944 {
945 I2C_BOARD_INFO("ad7879", 0x2F),
946 .irq = IRQ_PG5,
947 .platform_data = (void *)&bfin_ad7879_ts_info,
81d9c7f2
BW
948 },
949#endif
950};
951#endif
952
1394f032
BW
953#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
954static struct platform_device bfin_sport0_uart_device = {
955 .name = "bfin-sport-uart",
956 .id = 0,
957};
958
959static struct platform_device bfin_sport1_uart_device = {
960 .name = "bfin-sport-uart",
961 .id = 1,
962};
963#endif
964
c6c4d7bb 965#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
96b86e94 966#define PATA_INT IRQ_PF5
c6c4d7bb
BW
967
968static struct pata_platform_info bfin_pata_platform_data = {
969 .ioport_shift = 1,
64e5c512 970 .irq_flags = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
c6c4d7bb
BW
971};
972
973static struct resource bfin_pata_resources[] = {
974 {
975 .start = 0x20314020,
976 .end = 0x2031403F,
977 .flags = IORESOURCE_MEM,
978 },
979 {
980 .start = 0x2031401C,
981 .end = 0x2031401F,
982 .flags = IORESOURCE_MEM,
983 },
984 {
985 .start = PATA_INT,
986 .end = PATA_INT,
987 .flags = IORESOURCE_IRQ,
988 },
989};
990
991static struct platform_device bfin_pata_device = {
992 .name = "pata_platform",
993 .id = -1,
994 .num_resources = ARRAY_SIZE(bfin_pata_resources),
995 .resource = bfin_pata_resources,
996 .dev = {
997 .platform_data = &bfin_pata_platform_data,
998 }
999};
1000#endif
1001
14b03204
MH
1002static const unsigned int cclk_vlev_datasheet[] =
1003{
1004 VRPAIR(VLEV_085, 250000000),
1005 VRPAIR(VLEV_090, 376000000),
1006 VRPAIR(VLEV_095, 426000000),
1007 VRPAIR(VLEV_100, 426000000),
1008 VRPAIR(VLEV_105, 476000000),
1009 VRPAIR(VLEV_110, 476000000),
1010 VRPAIR(VLEV_115, 476000000),
1011 VRPAIR(VLEV_120, 500000000),
1012 VRPAIR(VLEV_125, 533000000),
1013 VRPAIR(VLEV_130, 600000000),
1014};
1015
1016static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
1017 .tuple_tab = cclk_vlev_datasheet,
1018 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
1019 .vr_settling_time = 25 /* us */,
1020};
1021
1022static struct platform_device bfin_dpmc = {
1023 .name = "bfin dpmc",
1024 .dev = {
1025 .platform_data = &bfin_dmpc_vreg_data,
1026 },
1027};
1028
1394f032 1029static struct platform_device *stamp_devices[] __initdata = {
14b03204
MH
1030
1031 &bfin_dpmc,
1032
1394f032
BW
1033#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
1034 &bfin_pcmcia_cf_device,
1035#endif
1036
1037#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
1038 &rtc_device,
1039#endif
1040
1041#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
1042 &sl811_hcd_device,
1043#endif
1044
1045#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
1046 &isp1362_hcd_device,
1047#endif
1048
3f375690
MH
1049#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
1050 &bfin_isp1760_device,
1051#endif
1052
1394f032
BW
1053#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
1054 &smc91x_device,
1055#endif
1056
f40d24d9
AL
1057#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
1058 &dm9000_device,
1059#endif
1060
561cc18b
MH
1061#if defined(CONFIG_AX88180) || defined(CONFIG_AX88180_MODULE)
1062 &ax88180_device,
1063#endif
1064
1394f032
BW
1065#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1066 &bfin_mac_device,
1067#endif
1068
1069#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
1070 &net2272_bfin_device,
1071#endif
1072
1073#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
c6c4d7bb 1074 &bfin_spi0_device,
1394f032
BW
1075#endif
1076
1077#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
1078 &bfin_fb_device,
1079#endif
1080
2043f3f7
MH
1081#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
1082 &bfin_lq035q1_device,
1083#endif
1084
c6c4d7bb
BW
1085#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
1086 &bfin_fb_adv7393_device,
1087#endif
1088
1394f032
BW
1089#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
1090 &bfin_uart_device,
1091#endif
1092
5be36d22
GY
1093#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
1094 &bfin_sir_device,
1095#endif
1096
1394f032
BW
1097#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
1098 &i2c_bfin_twi_device,
1099#endif
1100
1101#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
1102 &bfin_sport0_uart_device,
1103 &bfin_sport1_uart_device,
1104#endif
c6c4d7bb
BW
1105
1106#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
1107 &bfin_pata_device,
1108#endif
2463ef22
MH
1109
1110#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
1111 &bfin_device_gpiokeys,
1112#endif
cad2ab65
MF
1113
1114 &bfin_gpios_device,
793dc27b 1115
fc68911e
MF
1116#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
1117 &bfin_async_nand_device,
1118#endif
1119
793dc27b 1120#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
de8c43f2 1121 &stamp_flash_device,
793dc27b 1122#endif
1394f032
BW
1123};
1124
1125static int __init stamp_init(void)
1126{
b85d858b 1127 printk(KERN_INFO "%s(): registering device resources\n", __func__);
81d9c7f2
BW
1128
1129#ifdef CONFIG_I2C_BOARDINFO
1130 i2c_register_board_info(0, bfin_i2c_board_info,
1131 ARRAY_SIZE(bfin_i2c_board_info));
1132#endif
1133
fc68911e 1134 bfin_plat_nand_init();
1394f032 1135 platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
5bda2723 1136 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
c6c4d7bb
BW
1137
1138#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
1139 irq_desc[PATA_INT].status |= IRQ_NOAUTOEN;
1140#endif
81d9c7f2 1141
1394f032
BW
1142 return 0;
1143}
1144
1145arch_initcall(stamp_init);
c6c4d7bb
BW
1146
1147void native_machine_restart(char *cmd)
1148{
1149 /* workaround reboot hang when booting from SPI */
1150 if ((bfin_read_SYSCR() & 0x7) == 0x3)
1151 bfin_gpio_reset_spi0_ssel1();
1152}
137b1529
MF
1153
1154/*
1155 * Currently the MAC address is saved in Flash by U-Boot
1156 */
1157#define FLASH_MAC 0x203f0000
9862cc52 1158void bfin_get_ether_addr(char *addr)
137b1529
MF
1159{
1160 *(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC);
1161 *(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4);
1162}
9862cc52 1163EXPORT_SYMBOL(bfin_get_ether_addr);