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19381f02 | 1 | /* |
96f1050d | 2 | * Copyright 2007-2008 Analog Devices Inc. |
19381f02 | 3 | * |
96f1050d | 4 | * Licensed under the ADI BSD license or the GPL-2 (or later) |
19381f02 BW |
5 | */ |
6 | ||
7 | #ifndef _DEF_BF527_H | |
8 | #define _DEF_BF527_H | |
9 | ||
10 | /* Include all Core registers and bit definitions */ | |
639f6571 | 11 | #include <asm/def_LPBlackfin.h> |
19381f02 BW |
12 | |
13 | /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */ | |
14 | ||
15 | /* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */ | |
59003145 | 16 | #include "defBF52x_base.h" |
19381f02 BW |
17 | |
18 | /* The following are the #defines needed by ADSP-BF527 that are not in the common header */ | |
19 | /* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ | |
20 | ||
21 | #define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */ | |
22 | #define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */ | |
23 | #define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */ | |
24 | #define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */ | |
25 | #define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */ | |
26 | #define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */ | |
27 | #define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */ | |
28 | #define EMAC_FLC 0xFFC0301C /* Flow Control Register */ | |
29 | #define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */ | |
30 | #define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */ | |
31 | #define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */ | |
32 | #define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */ | |
33 | #define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */ | |
34 | #define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */ | |
35 | #define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */ | |
36 | #define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */ | |
37 | #define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */ | |
38 | #define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */ | |
39 | #define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */ | |
40 | ||
41 | #define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */ | |
42 | #define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */ | |
43 | #define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */ | |
44 | #define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */ | |
45 | #define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */ | |
46 | #define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */ | |
47 | #define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */ | |
48 | #define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */ | |
49 | ||
50 | #define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */ | |
51 | #define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */ | |
52 | #define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */ | |
53 | #define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */ | |
54 | #define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */ | |
55 | ||
56 | #define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */ | |
57 | #define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */ | |
58 | #define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */ | |
59 | #define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */ | |
60 | #define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */ | |
61 | #define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */ | |
62 | #define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */ | |
63 | #define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */ | |
64 | #define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */ | |
65 | #define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */ | |
66 | #define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */ | |
67 | #define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */ | |
68 | #define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */ | |
69 | #define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */ | |
70 | #define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */ | |
71 | #define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */ | |
72 | #define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */ | |
73 | #define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */ | |
74 | #define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */ | |
75 | #define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */ | |
76 | #define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ | |
77 | #define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ | |
78 | #define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ | |
79 | #define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */ | |
80 | ||
81 | #define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */ | |
82 | #define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */ | |
83 | #define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */ | |
84 | #define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */ | |
85 | #define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */ | |
86 | #define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */ | |
87 | #define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */ | |
88 | #define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */ | |
89 | #define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */ | |
90 | #define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */ | |
91 | #define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */ | |
92 | #define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */ | |
93 | #define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */ | |
94 | #define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */ | |
95 | #define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */ | |
96 | #define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */ | |
97 | #define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */ | |
98 | #define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */ | |
99 | #define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ | |
100 | #define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */ | |
101 | #define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ | |
102 | #define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */ | |
103 | #define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */ | |
104 | ||
105 | /* Listing for IEEE-Supported Count Registers */ | |
106 | ||
107 | #define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */ | |
108 | #define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */ | |
109 | #define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */ | |
110 | #define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */ | |
111 | #define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */ | |
112 | #define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */ | |
113 | #define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */ | |
114 | #define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */ | |
115 | #define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */ | |
116 | #define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */ | |
117 | #define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */ | |
118 | #define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */ | |
119 | #define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */ | |
120 | #define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */ | |
121 | #define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */ | |
122 | #define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */ | |
123 | #define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */ | |
124 | #define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */ | |
125 | #define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */ | |
126 | #define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */ | |
127 | #define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ | |
128 | #define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ | |
129 | #define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ | |
130 | #define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */ | |
131 | ||
132 | #define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */ | |
133 | #define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */ | |
134 | #define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */ | |
135 | #define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */ | |
136 | #define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */ | |
137 | #define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */ | |
138 | #define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */ | |
139 | #define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */ | |
140 | #define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */ | |
141 | #define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */ | |
142 | #define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */ | |
143 | #define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */ | |
144 | #define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */ | |
145 | #define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */ | |
146 | #define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */ | |
147 | #define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */ | |
148 | #define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */ | |
149 | #define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */ | |
150 | #define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ | |
151 | #define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */ | |
152 | #define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ | |
153 | #define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */ | |
154 | #define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */ | |
155 | ||
156 | /*********************************************************************************** | |
157 | ** System MMR Register Bits And Macros | |
158 | ** | |
159 | ** Disclaimer: All macros are intended to make C and Assembly code more readable. | |
160 | ** Use these macros carefully, as any that do left shifts for field | |
161 | ** depositing will result in the lower order bits being destroyed. Any | |
162 | ** macro that shifts left to properly position the bit-field should be | |
163 | ** used as part of an OR to initialize a register and NOT as a dynamic | |
164 | ** modifier UNLESS the lower order bits are saved and ORed back in when | |
165 | ** the macro is used. | |
166 | *************************************************************************************/ | |
167 | ||
168 | /************************ ETHERNET 10/100 CONTROLLER MASKS ************************/ | |
169 | ||
170 | /* EMAC_OPMODE Masks */ | |
171 | ||
172 | #define RE 0x00000001 /* Receiver Enable */ | |
173 | #define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */ | |
174 | #define HU 0x00000010 /* Hash Filter Unicast Address */ | |
175 | #define HM 0x00000020 /* Hash Filter Multicast Address */ | |
176 | #define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */ | |
177 | #define PR 0x00000080 /* Promiscuous Mode Enable */ | |
178 | #define IFE 0x00000100 /* Inverse Filtering Enable */ | |
179 | #define DBF 0x00000200 /* Disable Broadcast Frame Reception */ | |
180 | #define PBF 0x00000400 /* Pass Bad Frames Enable */ | |
181 | #define PSF 0x00000800 /* Pass Short Frames Enable */ | |
182 | #define RAF 0x00001000 /* Receive-All Mode */ | |
183 | #define TE 0x00010000 /* Transmitter Enable */ | |
184 | #define DTXPAD 0x00020000 /* Disable Automatic TX Padding */ | |
185 | #define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */ | |
186 | #define DC 0x00080000 /* Deferral Check */ | |
187 | #define BOLMT 0x00300000 /* Back-Off Limit */ | |
188 | #define BOLMT_10 0x00000000 /* 10-bit range */ | |
189 | #define BOLMT_8 0x00100000 /* 8-bit range */ | |
190 | #define BOLMT_4 0x00200000 /* 4-bit range */ | |
191 | #define BOLMT_1 0x00300000 /* 1-bit range */ | |
192 | #define DRTY 0x00400000 /* Disable TX Retry On Collision */ | |
193 | #define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */ | |
194 | #define RMII 0x01000000 /* RMII/MII* Mode */ | |
195 | #define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */ | |
196 | #define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */ | |
197 | #define LB 0x08000000 /* Internal Loopback Enable */ | |
198 | #define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */ | |
199 | ||
200 | /* EMAC_STAADD Masks */ | |
201 | ||
202 | #define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */ | |
203 | #define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */ | |
204 | #define STADISPRE 0x00000004 /* Disable Preamble Generation */ | |
205 | #define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */ | |
206 | #define REGAD 0x000007C0 /* STA Register Address */ | |
207 | #define PHYAD 0x0000F800 /* PHY Device Address */ | |
208 | ||
209 | #define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */ | |
210 | #define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */ | |
211 | ||
212 | /* EMAC_STADAT Mask */ | |
213 | ||
214 | #define STADATA 0x0000FFFF /* Station Management Data */ | |
215 | ||
216 | /* EMAC_FLC Masks */ | |
217 | ||
218 | #define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */ | |
219 | #define FLCE 0x00000002 /* Flow Control Enable */ | |
220 | #define PCF 0x00000004 /* Pass Control Frames */ | |
221 | #define BKPRSEN 0x00000008 /* Enable Backpressure */ | |
222 | #define FLCPAUSE 0xFFFF0000 /* Pause Time */ | |
223 | ||
224 | #define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */ | |
225 | ||
226 | /* EMAC_WKUP_CTL Masks */ | |
227 | ||
228 | #define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */ | |
229 | #define MPKE 0x00000002 /* Magic Packet Enable */ | |
230 | #define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */ | |
231 | #define GUWKE 0x00000008 /* Global Unicast Wake Enable */ | |
232 | #define MPKS 0x00000020 /* Magic Packet Received Status */ | |
233 | #define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */ | |
234 | ||
235 | /* EMAC_WKUP_FFCMD Masks */ | |
236 | ||
237 | #define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */ | |
238 | #define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */ | |
239 | #define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */ | |
240 | #define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */ | |
241 | #define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */ | |
242 | #define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */ | |
243 | #define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */ | |
244 | #define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */ | |
245 | ||
246 | /* EMAC_WKUP_FFOFF Masks */ | |
247 | ||
248 | #define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */ | |
249 | #define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */ | |
250 | #define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */ | |
251 | #define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */ | |
252 | ||
253 | #define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */ | |
254 | #define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */ | |
255 | #define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */ | |
256 | #define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */ | |
257 | /* Set ALL Offsets */ | |
258 | #define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3))) | |
259 | ||
260 | /* EMAC_WKUP_FFCRC0 Masks */ | |
261 | ||
262 | #define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */ | |
263 | #define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */ | |
264 | ||
265 | #define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */ | |
266 | #define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */ | |
267 | ||
268 | /* EMAC_WKUP_FFCRC1 Masks */ | |
269 | ||
270 | #define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */ | |
271 | #define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */ | |
272 | ||
273 | #define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */ | |
274 | #define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */ | |
275 | ||
276 | /* EMAC_SYSCTL Masks */ | |
277 | ||
278 | #define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */ | |
279 | #define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */ | |
280 | #define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */ | |
1c0d20cd | 281 | #define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */ |
19381f02 BW |
282 | #define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */ |
283 | ||
284 | #define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */ | |
285 | ||
286 | /* EMAC_SYSTAT Masks */ | |
287 | ||
288 | #define PHYINT 0x00000001 /* PHY_INT Interrupt Status */ | |
289 | #define MMCINT 0x00000002 /* MMC Counter Interrupt Status */ | |
290 | #define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */ | |
291 | #define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */ | |
292 | #define WAKEDET 0x00000010 /* Wake-Up Detected Status */ | |
293 | #define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */ | |
294 | #define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */ | |
295 | #define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */ | |
296 | ||
297 | /* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */ | |
298 | ||
299 | #define RX_FRLEN 0x000007FF /* Frame Length In Bytes */ | |
300 | #define RX_COMP 0x00001000 /* RX Frame Complete */ | |
301 | #define RX_OK 0x00002000 /* RX Frame Received With No Errors */ | |
302 | #define RX_LONG 0x00004000 /* RX Frame Too Long Error */ | |
303 | #define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */ | |
304 | #define RX_CRC 0x00010000 /* RX Frame CRC Error */ | |
305 | #define RX_LEN 0x00020000 /* RX Frame Length Error */ | |
306 | #define RX_FRAG 0x00040000 /* RX Frame Fragment Error */ | |
307 | #define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */ | |
308 | #define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */ | |
309 | #define RX_PHY 0x00200000 /* RX Frame PHY Error */ | |
310 | #define RX_LATE 0x00400000 /* RX Frame Late Collision Error */ | |
311 | #define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */ | |
312 | #define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */ | |
313 | #define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */ | |
314 | #define RX_CTL 0x04000000 /* RX Control Frame Indicator */ | |
315 | #define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */ | |
316 | #define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */ | |
317 | #define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */ | |
318 | #define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */ | |
319 | #define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */ | |
320 | ||
321 | /* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */ | |
322 | ||
323 | #define TX_COMP 0x00000001 /* TX Frame Complete */ | |
324 | #define TX_OK 0x00000002 /* TX Frame Sent With No Errors */ | |
325 | #define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */ | |
326 | #define TX_LATE 0x00000008 /* TX Frame Late Collision Error */ | |
327 | #define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */ | |
328 | #define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */ | |
329 | #define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */ | |
330 | #define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */ | |
331 | #define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */ | |
332 | #define TX_CCNT 0x00000F00 /* TX Frame Collision Count */ | |
333 | #define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */ | |
334 | #define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */ | |
335 | #define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */ | |
336 | #define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */ | |
337 | #define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */ | |
338 | ||
339 | /* EMAC_MMC_CTL Masks */ | |
340 | #define RSTC 0x00000001 /* Reset All Counters */ | |
341 | #define CROLL 0x00000002 /* Counter Roll-Over Enable */ | |
342 | #define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */ | |
343 | #define MMCE 0x00000008 /* Enable MMC Counter Operation */ | |
344 | ||
345 | /* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */ | |
346 | #define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */ | |
347 | #define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */ | |
348 | #define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */ | |
349 | #define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */ | |
350 | #define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */ | |
351 | #define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */ | |
352 | #define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */ | |
353 | #define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */ | |
354 | #define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */ | |
355 | #define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */ | |
356 | #define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */ | |
357 | #define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */ | |
358 | #define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */ | |
359 | #define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */ | |
360 | #define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */ | |
361 | #define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */ | |
362 | #define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */ | |
363 | #define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */ | |
364 | #define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */ | |
365 | #define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */ | |
366 | #define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */ | |
367 | #define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */ | |
368 | #define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */ | |
369 | #define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */ | |
370 | ||
371 | /* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */ | |
372 | ||
373 | #define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */ | |
374 | #define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */ | |
375 | #define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */ | |
376 | #define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */ | |
377 | #define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */ | |
378 | #define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */ | |
379 | #define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */ | |
380 | #define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */ | |
381 | #define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */ | |
382 | #define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */ | |
383 | #define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */ | |
384 | #define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */ | |
385 | #define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */ | |
386 | #define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */ | |
387 | #define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */ | |
388 | #define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */ | |
389 | #define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */ | |
390 | #define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */ | |
391 | #define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */ | |
392 | #define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */ | |
393 | #define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */ | |
394 | #define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */ | |
395 | #define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */ | |
396 | ||
397 | /* USB Control Registers */ | |
398 | ||
399 | #define USB_FADDR 0xffc03800 /* Function address register */ | |
400 | #define USB_POWER 0xffc03804 /* Power management register */ | |
401 | #define USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ | |
402 | #define USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to 7 */ | |
403 | #define USB_INTRTXE 0xffc03810 /* Interrupt enable register for IntrTx */ | |
404 | #define USB_INTRRXE 0xffc03814 /* Interrupt enable register for IntrRx */ | |
405 | #define USB_INTRUSB 0xffc03818 /* Interrupt register for common USB interrupts */ | |
406 | #define USB_INTRUSBE 0xffc0381c /* Interrupt enable register for IntrUSB */ | |
407 | #define USB_FRAME 0xffc03820 /* USB frame number */ | |
408 | #define USB_INDEX 0xffc03824 /* Index register for selecting the indexed endpoint registers */ | |
409 | #define USB_TESTMODE 0xffc03828 /* Enabled USB 20 test modes */ | |
410 | #define USB_GLOBINTR 0xffc0382c /* Global Interrupt Mask register and Wakeup Exception Interrupt */ | |
411 | #define USB_GLOBAL_CTL 0xffc03830 /* Global Clock Control for the core */ | |
412 | ||
413 | /* USB Packet Control Registers */ | |
414 | ||
415 | #define USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint */ | |
416 | #define USB_CSR0 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ | |
417 | #define USB_TXCSR 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ | |
418 | #define USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint */ | |
419 | #define USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpoint */ | |
420 | #define USB_COUNT0 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ | |
421 | #define USB_RXCOUNT 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ | |
422 | #define USB_TXTYPE 0xffc03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ | |
423 | #define USB_NAKLIMIT0 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ | |
424 | #define USB_TXINTERVAL 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ | |
425 | #define USB_RXTYPE 0xffc0385c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ | |
426 | #define USB_RXINTERVAL 0xffc03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ | |
427 | #define USB_TXCOUNT 0xffc03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */ | |
428 | ||
429 | /* USB Endpoint FIFO Registers */ | |
430 | ||
431 | #define USB_EP0_FIFO 0xffc03880 /* Endpoint 0 FIFO */ | |
432 | #define USB_EP1_FIFO 0xffc03888 /* Endpoint 1 FIFO */ | |
433 | #define USB_EP2_FIFO 0xffc03890 /* Endpoint 2 FIFO */ | |
434 | #define USB_EP3_FIFO 0xffc03898 /* Endpoint 3 FIFO */ | |
435 | #define USB_EP4_FIFO 0xffc038a0 /* Endpoint 4 FIFO */ | |
436 | #define USB_EP5_FIFO 0xffc038a8 /* Endpoint 5 FIFO */ | |
437 | #define USB_EP6_FIFO 0xffc038b0 /* Endpoint 6 FIFO */ | |
438 | #define USB_EP7_FIFO 0xffc038b8 /* Endpoint 7 FIFO */ | |
439 | ||
440 | /* USB OTG Control Registers */ | |
441 | ||
442 | #define USB_OTG_DEV_CTL 0xffc03900 /* OTG Device Control Register */ | |
443 | #define USB_OTG_VBUS_IRQ 0xffc03904 /* OTG VBUS Control Interrupts */ | |
444 | #define USB_OTG_VBUS_MASK 0xffc03908 /* VBUS Control Interrupt Enable */ | |
445 | ||
446 | /* USB Phy Control Registers */ | |
447 | ||
448 | #define USB_LINKINFO 0xffc03948 /* Enables programming of some PHY-side delays */ | |
449 | #define USB_VPLEN 0xffc0394c /* Determines duration of VBUS pulse for VBUS charging */ | |
450 | #define USB_HS_EOF1 0xffc03950 /* Time buffer for High-Speed transactions */ | |
451 | #define USB_FS_EOF1 0xffc03954 /* Time buffer for Full-Speed transactions */ | |
452 | #define USB_LS_EOF1 0xffc03958 /* Time buffer for Low-Speed transactions */ | |
453 | ||
454 | /* (APHY_CNTRL is for ADI usage only) */ | |
455 | ||
456 | #define USB_APHY_CNTRL 0xffc039e0 /* Register that increases visibility of Analog PHY */ | |
457 | ||
458 | /* (APHY_CALIB is for ADI usage only) */ | |
459 | ||
460 | #define USB_APHY_CALIB 0xffc039e4 /* Register used to set some calibration values */ | |
461 | ||
462 | #define USB_APHY_CNTRL2 0xffc039e8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ | |
463 | ||
464 | /* (PHY_TEST is for ADI usage only) */ | |
465 | ||
466 | #define USB_PHY_TEST 0xffc039ec /* Used for reducing simulation time and simplifies FIFO testability */ | |
467 | ||
468 | #define USB_PLLOSC_CTRL 0xffc039f0 /* Used to program different parameters for USB PLL and Oscillator */ | |
469 | #define USB_SRP_CLKDIV 0xffc039f4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ | |
470 | ||
471 | /* USB Endpoint 0 Control Registers */ | |
472 | ||
473 | #define USB_EP_NI0_TXMAXP 0xffc03a00 /* Maximum packet size for Host Tx endpoint0 */ | |
474 | #define USB_EP_NI0_TXCSR 0xffc03a04 /* Control Status register for endpoint 0 */ | |
475 | #define USB_EP_NI0_RXMAXP 0xffc03a08 /* Maximum packet size for Host Rx endpoint0 */ | |
476 | #define USB_EP_NI0_RXCSR 0xffc03a0c /* Control Status register for Host Rx endpoint0 */ | |
477 | #define USB_EP_NI0_RXCOUNT 0xffc03a10 /* Number of bytes received in endpoint 0 FIFO */ | |
478 | #define USB_EP_NI0_TXTYPE 0xffc03a14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ | |
479 | #define USB_EP_NI0_TXINTERVAL 0xffc03a18 /* Sets the NAK response timeout on Endpoint 0 */ | |
480 | #define USB_EP_NI0_RXTYPE 0xffc03a1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ | |
481 | #define USB_EP_NI0_RXINTERVAL 0xffc03a20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ | |
482 | #define USB_EP_NI0_TXCOUNT 0xffc03a28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ | |
483 | ||
484 | /* USB Endpoint 1 Control Registers */ | |
485 | ||
486 | #define USB_EP_NI1_TXMAXP 0xffc03a40 /* Maximum packet size for Host Tx endpoint1 */ | |
487 | #define USB_EP_NI1_TXCSR 0xffc03a44 /* Control Status register for endpoint1 */ | |
488 | #define USB_EP_NI1_RXMAXP 0xffc03a48 /* Maximum packet size for Host Rx endpoint1 */ | |
489 | #define USB_EP_NI1_RXCSR 0xffc03a4c /* Control Status register for Host Rx endpoint1 */ | |
490 | #define USB_EP_NI1_RXCOUNT 0xffc03a50 /* Number of bytes received in endpoint1 FIFO */ | |
491 | #define USB_EP_NI1_TXTYPE 0xffc03a54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ | |
492 | #define USB_EP_NI1_TXINTERVAL 0xffc03a58 /* Sets the NAK response timeout on Endpoint1 */ | |
493 | #define USB_EP_NI1_RXTYPE 0xffc03a5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ | |
494 | #define USB_EP_NI1_RXINTERVAL 0xffc03a60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ | |
495 | #define USB_EP_NI1_TXCOUNT 0xffc03a68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ | |
496 | ||
497 | /* USB Endpoint 2 Control Registers */ | |
498 | ||
499 | #define USB_EP_NI2_TXMAXP 0xffc03a80 /* Maximum packet size for Host Tx endpoint2 */ | |
500 | #define USB_EP_NI2_TXCSR 0xffc03a84 /* Control Status register for endpoint2 */ | |
501 | #define USB_EP_NI2_RXMAXP 0xffc03a88 /* Maximum packet size for Host Rx endpoint2 */ | |
502 | #define USB_EP_NI2_RXCSR 0xffc03a8c /* Control Status register for Host Rx endpoint2 */ | |
503 | #define USB_EP_NI2_RXCOUNT 0xffc03a90 /* Number of bytes received in endpoint2 FIFO */ | |
504 | #define USB_EP_NI2_TXTYPE 0xffc03a94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ | |
505 | #define USB_EP_NI2_TXINTERVAL 0xffc03a98 /* Sets the NAK response timeout on Endpoint2 */ | |
506 | #define USB_EP_NI2_RXTYPE 0xffc03a9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ | |
507 | #define USB_EP_NI2_RXINTERVAL 0xffc03aa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ | |
508 | #define USB_EP_NI2_TXCOUNT 0xffc03aa8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ | |
509 | ||
510 | /* USB Endpoint 3 Control Registers */ | |
511 | ||
512 | #define USB_EP_NI3_TXMAXP 0xffc03ac0 /* Maximum packet size for Host Tx endpoint3 */ | |
513 | #define USB_EP_NI3_TXCSR 0xffc03ac4 /* Control Status register for endpoint3 */ | |
514 | #define USB_EP_NI3_RXMAXP 0xffc03ac8 /* Maximum packet size for Host Rx endpoint3 */ | |
515 | #define USB_EP_NI3_RXCSR 0xffc03acc /* Control Status register for Host Rx endpoint3 */ | |
516 | #define USB_EP_NI3_RXCOUNT 0xffc03ad0 /* Number of bytes received in endpoint3 FIFO */ | |
517 | #define USB_EP_NI3_TXTYPE 0xffc03ad4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ | |
518 | #define USB_EP_NI3_TXINTERVAL 0xffc03ad8 /* Sets the NAK response timeout on Endpoint3 */ | |
519 | #define USB_EP_NI3_RXTYPE 0xffc03adc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ | |
520 | #define USB_EP_NI3_RXINTERVAL 0xffc03ae0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ | |
521 | #define USB_EP_NI3_TXCOUNT 0xffc03ae8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ | |
522 | ||
523 | /* USB Endpoint 4 Control Registers */ | |
524 | ||
525 | #define USB_EP_NI4_TXMAXP 0xffc03b00 /* Maximum packet size for Host Tx endpoint4 */ | |
526 | #define USB_EP_NI4_TXCSR 0xffc03b04 /* Control Status register for endpoint4 */ | |
527 | #define USB_EP_NI4_RXMAXP 0xffc03b08 /* Maximum packet size for Host Rx endpoint4 */ | |
528 | #define USB_EP_NI4_RXCSR 0xffc03b0c /* Control Status register for Host Rx endpoint4 */ | |
529 | #define USB_EP_NI4_RXCOUNT 0xffc03b10 /* Number of bytes received in endpoint4 FIFO */ | |
530 | #define USB_EP_NI4_TXTYPE 0xffc03b14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ | |
531 | #define USB_EP_NI4_TXINTERVAL 0xffc03b18 /* Sets the NAK response timeout on Endpoint4 */ | |
532 | #define USB_EP_NI4_RXTYPE 0xffc03b1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ | |
533 | #define USB_EP_NI4_RXINTERVAL 0xffc03b20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ | |
534 | #define USB_EP_NI4_TXCOUNT 0xffc03b28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ | |
535 | ||
536 | /* USB Endpoint 5 Control Registers */ | |
537 | ||
538 | #define USB_EP_NI5_TXMAXP 0xffc03b40 /* Maximum packet size for Host Tx endpoint5 */ | |
539 | #define USB_EP_NI5_TXCSR 0xffc03b44 /* Control Status register for endpoint5 */ | |
540 | #define USB_EP_NI5_RXMAXP 0xffc03b48 /* Maximum packet size for Host Rx endpoint5 */ | |
541 | #define USB_EP_NI5_RXCSR 0xffc03b4c /* Control Status register for Host Rx endpoint5 */ | |
542 | #define USB_EP_NI5_RXCOUNT 0xffc03b50 /* Number of bytes received in endpoint5 FIFO */ | |
543 | #define USB_EP_NI5_TXTYPE 0xffc03b54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ | |
544 | #define USB_EP_NI5_TXINTERVAL 0xffc03b58 /* Sets the NAK response timeout on Endpoint5 */ | |
545 | #define USB_EP_NI5_RXTYPE 0xffc03b5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ | |
546 | #define USB_EP_NI5_RXINTERVAL 0xffc03b60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ | |
547 | #define USB_EP_NI5_TXCOUNT 0xffc03b68 /* Number of bytes to be written to the endpoint5 Tx FIFO */ | |
548 | ||
549 | /* USB Endpoint 6 Control Registers */ | |
550 | ||
551 | #define USB_EP_NI6_TXMAXP 0xffc03b80 /* Maximum packet size for Host Tx endpoint6 */ | |
552 | #define USB_EP_NI6_TXCSR 0xffc03b84 /* Control Status register for endpoint6 */ | |
553 | #define USB_EP_NI6_RXMAXP 0xffc03b88 /* Maximum packet size for Host Rx endpoint6 */ | |
554 | #define USB_EP_NI6_RXCSR 0xffc03b8c /* Control Status register for Host Rx endpoint6 */ | |
555 | #define USB_EP_NI6_RXCOUNT 0xffc03b90 /* Number of bytes received in endpoint6 FIFO */ | |
556 | #define USB_EP_NI6_TXTYPE 0xffc03b94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ | |
557 | #define USB_EP_NI6_TXINTERVAL 0xffc03b98 /* Sets the NAK response timeout on Endpoint6 */ | |
558 | #define USB_EP_NI6_RXTYPE 0xffc03b9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ | |
559 | #define USB_EP_NI6_RXINTERVAL 0xffc03ba0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ | |
560 | #define USB_EP_NI6_TXCOUNT 0xffc03ba8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ | |
561 | ||
562 | /* USB Endpoint 7 Control Registers */ | |
563 | ||
564 | #define USB_EP_NI7_TXMAXP 0xffc03bc0 /* Maximum packet size for Host Tx endpoint7 */ | |
565 | #define USB_EP_NI7_TXCSR 0xffc03bc4 /* Control Status register for endpoint7 */ | |
566 | #define USB_EP_NI7_RXMAXP 0xffc03bc8 /* Maximum packet size for Host Rx endpoint7 */ | |
567 | #define USB_EP_NI7_RXCSR 0xffc03bcc /* Control Status register for Host Rx endpoint7 */ | |
568 | #define USB_EP_NI7_RXCOUNT 0xffc03bd0 /* Number of bytes received in endpoint7 FIFO */ | |
569 | #define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ | |
570 | #define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */ | |
571 | #define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ | |
572 | #define USB_EP_NI7_RXINTERVAL 0xffc03bf0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ | |
573 | #define USB_EP_NI7_TXCOUNT 0xffc03bf8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ | |
574 | ||
575 | #define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */ | |
576 | ||
577 | /* USB Channel 0 Config Registers */ | |
578 | ||
579 | #define USB_DMA0CONTROL 0xffc03c04 /* DMA master channel 0 configuration */ | |
580 | #define USB_DMA0ADDRLOW 0xffc03c08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ | |
581 | #define USB_DMA0ADDRHIGH 0xffc03c0c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ | |
582 | #define USB_DMA0COUNTLOW 0xffc03c10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ | |
583 | #define USB_DMA0COUNTHIGH 0xffc03c14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ | |
584 | ||
585 | /* USB Channel 1 Config Registers */ | |
586 | ||
587 | #define USB_DMA1CONTROL 0xffc03c24 /* DMA master channel 1 configuration */ | |
588 | #define USB_DMA1ADDRLOW 0xffc03c28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ | |
589 | #define USB_DMA1ADDRHIGH 0xffc03c2c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ | |
590 | #define USB_DMA1COUNTLOW 0xffc03c30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ | |
591 | #define USB_DMA1COUNTHIGH 0xffc03c34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ | |
592 | ||
593 | /* USB Channel 2 Config Registers */ | |
594 | ||
595 | #define USB_DMA2CONTROL 0xffc03c44 /* DMA master channel 2 configuration */ | |
596 | #define USB_DMA2ADDRLOW 0xffc03c48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ | |
597 | #define USB_DMA2ADDRHIGH 0xffc03c4c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ | |
598 | #define USB_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ | |
599 | #define USB_DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ | |
600 | ||
601 | /* USB Channel 3 Config Registers */ | |
602 | ||
603 | #define USB_DMA3CONTROL 0xffc03c64 /* DMA master channel 3 configuration */ | |
604 | #define USB_DMA3ADDRLOW 0xffc03c68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ | |
605 | #define USB_DMA3ADDRHIGH 0xffc03c6c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ | |
606 | #define USB_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ | |
607 | #define USB_DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ | |
608 | ||
609 | /* USB Channel 4 Config Registers */ | |
610 | ||
611 | #define USB_DMA4CONTROL 0xffc03c84 /* DMA master channel 4 configuration */ | |
612 | #define USB_DMA4ADDRLOW 0xffc03c88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ | |
613 | #define USB_DMA4ADDRHIGH 0xffc03c8c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ | |
614 | #define USB_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ | |
615 | #define USB_DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ | |
616 | ||
617 | /* USB Channel 5 Config Registers */ | |
618 | ||
619 | #define USB_DMA5CONTROL 0xffc03ca4 /* DMA master channel 5 configuration */ | |
620 | #define USB_DMA5ADDRLOW 0xffc03ca8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ | |
621 | #define USB_DMA5ADDRHIGH 0xffc03cac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ | |
622 | #define USB_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ | |
623 | #define USB_DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ | |
624 | ||
625 | /* USB Channel 6 Config Registers */ | |
626 | ||
627 | #define USB_DMA6CONTROL 0xffc03cc4 /* DMA master channel 6 configuration */ | |
628 | #define USB_DMA6ADDRLOW 0xffc03cc8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ | |
629 | #define USB_DMA6ADDRHIGH 0xffc03ccc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ | |
630 | #define USB_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ | |
631 | #define USB_DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ | |
632 | ||
633 | /* USB Channel 7 Config Registers */ | |
634 | ||
635 | #define USB_DMA7CONTROL 0xffc03ce4 /* DMA master channel 7 configuration */ | |
636 | #define USB_DMA7ADDRLOW 0xffc03ce8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ | |
637 | #define USB_DMA7ADDRHIGH 0xffc03cec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ | |
638 | #define USB_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ | |
639 | #define USB_DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ | |
640 | ||
641 | /* Bit masks for USB_FADDR */ | |
642 | ||
643 | #define FUNCTION_ADDRESS 0x7f /* Function address */ | |
644 | ||
645 | /* Bit masks for USB_POWER */ | |
646 | ||
647 | #define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ | |
648 | #define nENABLE_SUSPENDM 0x0 | |
649 | #define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ | |
650 | #define nSUSPEND_MODE 0x0 | |
651 | #define RESUME_MODE 0x4 /* DMA Mode */ | |
652 | #define nRESUME_MODE 0x0 | |
653 | #define RESET 0x8 /* Reset indicator */ | |
654 | #define nRESET 0x0 | |
655 | #define HS_MODE 0x10 /* High Speed mode indicator */ | |
656 | #define nHS_MODE 0x0 | |
657 | #define HS_ENABLE 0x20 /* high Speed Enable */ | |
658 | #define nHS_ENABLE 0x0 | |
659 | #define SOFT_CONN 0x40 /* Soft connect */ | |
660 | #define nSOFT_CONN 0x0 | |
661 | #define ISO_UPDATE 0x80 /* Isochronous update */ | |
662 | #define nISO_UPDATE 0x0 | |
663 | ||
664 | /* Bit masks for USB_INTRTX */ | |
665 | ||
666 | #define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ | |
667 | #define nEP0_TX 0x0 | |
668 | #define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ | |
669 | #define nEP1_TX 0x0 | |
670 | #define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ | |
671 | #define nEP2_TX 0x0 | |
672 | #define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ | |
673 | #define nEP3_TX 0x0 | |
674 | #define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ | |
675 | #define nEP4_TX 0x0 | |
676 | #define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ | |
677 | #define nEP5_TX 0x0 | |
678 | #define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ | |
679 | #define nEP6_TX 0x0 | |
680 | #define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ | |
681 | #define nEP7_TX 0x0 | |
682 | ||
683 | /* Bit masks for USB_INTRRX */ | |
684 | ||
685 | #define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ | |
686 | #define nEP1_RX 0x0 | |
687 | #define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ | |
688 | #define nEP2_RX 0x0 | |
689 | #define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ | |
690 | #define nEP3_RX 0x0 | |
691 | #define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ | |
692 | #define nEP4_RX 0x0 | |
693 | #define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ | |
694 | #define nEP5_RX 0x0 | |
695 | #define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ | |
696 | #define nEP6_RX 0x0 | |
697 | #define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ | |
698 | #define nEP7_RX 0x0 | |
699 | ||
700 | /* Bit masks for USB_INTRTXE */ | |
701 | ||
702 | #define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ | |
703 | #define nEP0_TX_E 0x0 | |
704 | #define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ | |
705 | #define nEP1_TX_E 0x0 | |
706 | #define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ | |
707 | #define nEP2_TX_E 0x0 | |
708 | #define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ | |
709 | #define nEP3_TX_E 0x0 | |
710 | #define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ | |
711 | #define nEP4_TX_E 0x0 | |
712 | #define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ | |
713 | #define nEP5_TX_E 0x0 | |
714 | #define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ | |
715 | #define nEP6_TX_E 0x0 | |
716 | #define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ | |
717 | #define nEP7_TX_E 0x0 | |
718 | ||
719 | /* Bit masks for USB_INTRRXE */ | |
720 | ||
721 | #define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ | |
722 | #define nEP1_RX_E 0x0 | |
723 | #define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ | |
724 | #define nEP2_RX_E 0x0 | |
725 | #define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ | |
726 | #define nEP3_RX_E 0x0 | |
727 | #define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ | |
728 | #define nEP4_RX_E 0x0 | |
729 | #define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ | |
730 | #define nEP5_RX_E 0x0 | |
731 | #define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ | |
732 | #define nEP6_RX_E 0x0 | |
733 | #define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ | |
734 | #define nEP7_RX_E 0x0 | |
735 | ||
736 | /* Bit masks for USB_INTRUSB */ | |
737 | ||
738 | #define SUSPEND_B 0x1 /* Suspend indicator */ | |
739 | #define nSUSPEND_B 0x0 | |
740 | #define RESUME_B 0x2 /* Resume indicator */ | |
741 | #define nRESUME_B 0x0 | |
742 | #define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ | |
743 | #define nRESET_OR_BABLE_B 0x0 | |
744 | #define SOF_B 0x8 /* Start of frame */ | |
745 | #define nSOF_B 0x0 | |
746 | #define CONN_B 0x10 /* Connection indicator */ | |
747 | #define nCONN_B 0x0 | |
748 | #define DISCON_B 0x20 /* Disconnect indicator */ | |
749 | #define nDISCON_B 0x0 | |
750 | #define SESSION_REQ_B 0x40 /* Session Request */ | |
751 | #define nSESSION_REQ_B 0x0 | |
752 | #define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ | |
753 | #define nVBUS_ERROR_B 0x0 | |
754 | ||
755 | /* Bit masks for USB_INTRUSBE */ | |
756 | ||
757 | #define SUSPEND_BE 0x1 /* Suspend indicator int enable */ | |
758 | #define nSUSPEND_BE 0x0 | |
759 | #define RESUME_BE 0x2 /* Resume indicator int enable */ | |
760 | #define nRESUME_BE 0x0 | |
761 | #define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ | |
762 | #define nRESET_OR_BABLE_BE 0x0 | |
763 | #define SOF_BE 0x8 /* Start of frame int enable */ | |
764 | #define nSOF_BE 0x0 | |
765 | #define CONN_BE 0x10 /* Connection indicator int enable */ | |
766 | #define nCONN_BE 0x0 | |
767 | #define DISCON_BE 0x20 /* Disconnect indicator int enable */ | |
768 | #define nDISCON_BE 0x0 | |
769 | #define SESSION_REQ_BE 0x40 /* Session Request int enable */ | |
770 | #define nSESSION_REQ_BE 0x0 | |
771 | #define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ | |
772 | #define nVBUS_ERROR_BE 0x0 | |
773 | ||
774 | /* Bit masks for USB_FRAME */ | |
775 | ||
776 | #define FRAME_NUMBER 0x7ff /* Frame number */ | |
777 | ||
778 | /* Bit masks for USB_INDEX */ | |
779 | ||
780 | #define SELECTED_ENDPOINT 0xf /* selected endpoint */ | |
781 | ||
782 | /* Bit masks for USB_GLOBAL_CTL */ | |
783 | ||
784 | #define GLOBAL_ENA 0x1 /* enables USB module */ | |
785 | #define nGLOBAL_ENA 0x0 | |
786 | #define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ | |
787 | #define nEP1_TX_ENA 0x0 | |
788 | #define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ | |
789 | #define nEP2_TX_ENA 0x0 | |
790 | #define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ | |
791 | #define nEP3_TX_ENA 0x0 | |
792 | #define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ | |
793 | #define nEP4_TX_ENA 0x0 | |
794 | #define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ | |
795 | #define nEP5_TX_ENA 0x0 | |
796 | #define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ | |
797 | #define nEP6_TX_ENA 0x0 | |
798 | #define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ | |
799 | #define nEP7_TX_ENA 0x0 | |
800 | #define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ | |
801 | #define nEP1_RX_ENA 0x0 | |
802 | #define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ | |
803 | #define nEP2_RX_ENA 0x0 | |
804 | #define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ | |
805 | #define nEP3_RX_ENA 0x0 | |
806 | #define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ | |
807 | #define nEP4_RX_ENA 0x0 | |
808 | #define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ | |
809 | #define nEP5_RX_ENA 0x0 | |
810 | #define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ | |
811 | #define nEP6_RX_ENA 0x0 | |
812 | #define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ | |
813 | #define nEP7_RX_ENA 0x0 | |
814 | ||
815 | /* Bit masks for USB_OTG_DEV_CTL */ | |
816 | ||
817 | #define SESSION 0x1 /* session indicator */ | |
818 | #define nSESSION 0x0 | |
819 | #define HOST_REQ 0x2 /* Host negotiation request */ | |
820 | #define nHOST_REQ 0x0 | |
821 | #define HOST_MODE 0x4 /* indicates USBDRC is a host */ | |
822 | #define nHOST_MODE 0x0 | |
823 | #define VBUS0 0x8 /* Vbus level indicator[0] */ | |
824 | #define nVBUS0 0x0 | |
825 | #define VBUS1 0x10 /* Vbus level indicator[1] */ | |
826 | #define nVBUS1 0x0 | |
827 | #define LSDEV 0x20 /* Low-speed indicator */ | |
828 | #define nLSDEV 0x0 | |
829 | #define FSDEV 0x40 /* Full or High-speed indicator */ | |
830 | #define nFSDEV 0x0 | |
831 | #define B_DEVICE 0x80 /* A' or 'B' device indicator */ | |
832 | #define nB_DEVICE 0x0 | |
833 | ||
834 | /* Bit masks for USB_OTG_VBUS_IRQ */ | |
835 | ||
836 | #define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ | |
837 | #define nDRIVE_VBUS_ON 0x0 | |
838 | #define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ | |
839 | #define nDRIVE_VBUS_OFF 0x0 | |
840 | #define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ | |
841 | #define nCHRG_VBUS_START 0x0 | |
842 | #define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ | |
843 | #define nCHRG_VBUS_END 0x0 | |
844 | #define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ | |
845 | #define nDISCHRG_VBUS_START 0x0 | |
846 | #define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ | |
847 | #define nDISCHRG_VBUS_END 0x0 | |
848 | ||
849 | /* Bit masks for USB_OTG_VBUS_MASK */ | |
850 | ||
851 | #define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ | |
852 | #define nDRIVE_VBUS_ON_ENA 0x0 | |
853 | #define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ | |
854 | #define nDRIVE_VBUS_OFF_ENA 0x0 | |
855 | #define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ | |
856 | #define nCHRG_VBUS_START_ENA 0x0 | |
857 | #define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ | |
858 | #define nCHRG_VBUS_END_ENA 0x0 | |
859 | #define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ | |
860 | #define nDISCHRG_VBUS_START_ENA 0x0 | |
861 | #define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ | |
862 | #define nDISCHRG_VBUS_END_ENA 0x0 | |
863 | ||
864 | /* Bit masks for USB_CSR0 */ | |
865 | ||
866 | #define RXPKTRDY 0x1 /* data packet receive indicator */ | |
867 | #define nRXPKTRDY 0x0 | |
868 | #define TXPKTRDY 0x2 /* data packet in FIFO indicator */ | |
869 | #define nTXPKTRDY 0x0 | |
870 | #define STALL_SENT 0x4 /* STALL handshake sent */ | |
871 | #define nSTALL_SENT 0x0 | |
872 | #define DATAEND 0x8 /* Data end indicator */ | |
873 | #define nDATAEND 0x0 | |
874 | #define SETUPEND 0x10 /* Setup end */ | |
875 | #define nSETUPEND 0x0 | |
876 | #define SENDSTALL 0x20 /* Send STALL handshake */ | |
877 | #define nSENDSTALL 0x0 | |
878 | #define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ | |
879 | #define nSERVICED_RXPKTRDY 0x0 | |
880 | #define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ | |
881 | #define nSERVICED_SETUPEND 0x0 | |
882 | #define FLUSHFIFO 0x100 /* flush endpoint FIFO */ | |
883 | #define nFLUSHFIFO 0x0 | |
884 | #define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ | |
885 | #define nSTALL_RECEIVED_H 0x0 | |
886 | #define SETUPPKT_H 0x8 /* send Setup token host mode */ | |
887 | #define nSETUPPKT_H 0x0 | |
888 | #define ERROR_H 0x10 /* timeout error indicator host mode */ | |
889 | #define nERROR_H 0x0 | |
890 | #define REQPKT_H 0x20 /* Request an IN transaction host mode */ | |
891 | #define nREQPKT_H 0x0 | |
892 | #define STATUSPKT_H 0x40 /* Status stage transaction host mode */ | |
893 | #define nSTATUSPKT_H 0x0 | |
894 | #define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ | |
895 | #define nNAK_TIMEOUT_H 0x0 | |
896 | ||
897 | /* Bit masks for USB_COUNT0 */ | |
898 | ||
899 | #define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */ | |
900 | ||
901 | /* Bit masks for USB_NAKLIMIT0 */ | |
902 | ||
903 | #define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */ | |
904 | ||
905 | /* Bit masks for USB_TX_MAX_PACKET */ | |
906 | ||
907 | #define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */ | |
908 | ||
909 | /* Bit masks for USB_RX_MAX_PACKET */ | |
910 | ||
911 | #define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */ | |
912 | ||
913 | /* Bit masks for USB_TXCSR */ | |
914 | ||
915 | #define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ | |
916 | #define nTXPKTRDY_T 0x0 | |
917 | #define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ | |
918 | #define nFIFO_NOT_EMPTY_T 0x0 | |
919 | #define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ | |
920 | #define nUNDERRUN_T 0x0 | |
921 | #define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ | |
922 | #define nFLUSHFIFO_T 0x0 | |
923 | #define STALL_SEND_T 0x10 /* issue a Stall handshake */ | |
924 | #define nSTALL_SEND_T 0x0 | |
925 | #define STALL_SENT_T 0x20 /* Stall handshake transmitted */ | |
926 | #define nSTALL_SENT_T 0x0 | |
927 | #define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ | |
928 | #define nCLEAR_DATATOGGLE_T 0x0 | |
929 | #define INCOMPTX_T 0x80 /* indicates that a large packet is split */ | |
930 | #define nINCOMPTX_T 0x0 | |
931 | #define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ | |
932 | #define nDMAREQMODE_T 0x0 | |
933 | #define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ | |
934 | #define nFORCE_DATATOGGLE_T 0x0 | |
935 | #define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ | |
936 | #define nDMAREQ_ENA_T 0x0 | |
937 | #define ISO_T 0x4000 /* enable Isochronous transfers */ | |
938 | #define nISO_T 0x0 | |
939 | #define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ | |
940 | #define nAUTOSET_T 0x0 | |
941 | #define ERROR_TH 0x4 /* error condition host mode */ | |
942 | #define nERROR_TH 0x0 | |
943 | #define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ | |
944 | #define nSTALL_RECEIVED_TH 0x0 | |
945 | #define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ | |
946 | #define nNAK_TIMEOUT_TH 0x0 | |
947 | ||
948 | /* Bit masks for USB_TXCOUNT */ | |
949 | ||
950 | #define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */ | |
951 | ||
952 | /* Bit masks for USB_RXCSR */ | |
953 | ||
954 | #define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ | |
955 | #define nRXPKTRDY_R 0x0 | |
956 | #define FIFO_FULL_R 0x2 /* FIFO not empty */ | |
957 | #define nFIFO_FULL_R 0x0 | |
958 | #define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ | |
959 | #define nOVERRUN_R 0x0 | |
960 | #define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ | |
961 | #define nDATAERROR_R 0x0 | |
962 | #define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ | |
963 | #define nFLUSHFIFO_R 0x0 | |
964 | #define STALL_SEND_R 0x20 /* issue a Stall handshake */ | |
965 | #define nSTALL_SEND_R 0x0 | |
966 | #define STALL_SENT_R 0x40 /* Stall handshake transmitted */ | |
967 | #define nSTALL_SENT_R 0x0 | |
968 | #define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ | |
969 | #define nCLEAR_DATATOGGLE_R 0x0 | |
970 | #define INCOMPRX_R 0x100 /* indicates that a large packet is split */ | |
971 | #define nINCOMPRX_R 0x0 | |
972 | #define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ | |
973 | #define nDMAREQMODE_R 0x0 | |
974 | #define DISNYET_R 0x1000 /* disable Nyet handshakes */ | |
975 | #define nDISNYET_R 0x0 | |
976 | #define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ | |
977 | #define nDMAREQ_ENA_R 0x0 | |
978 | #define ISO_R 0x4000 /* enable Isochronous transfers */ | |
979 | #define nISO_R 0x0 | |
980 | #define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ | |
981 | #define nAUTOCLEAR_R 0x0 | |
982 | #define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ | |
983 | #define nERROR_RH 0x0 | |
984 | #define REQPKT_RH 0x20 /* request an IN transaction host mode */ | |
985 | #define nREQPKT_RH 0x0 | |
986 | #define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ | |
987 | #define nSTALL_RECEIVED_RH 0x0 | |
988 | #define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ | |
989 | #define nINCOMPRX_RH 0x0 | |
990 | #define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ | |
991 | #define nDMAREQMODE_RH 0x0 | |
992 | #define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ | |
993 | #define nAUTOREQ_RH 0x0 | |
994 | ||
995 | /* Bit masks for USB_RXCOUNT */ | |
996 | ||
997 | #define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */ | |
998 | ||
999 | /* Bit masks for USB_TXTYPE */ | |
1000 | ||
1001 | #define TARGET_EP_NO_T 0xf /* EP number */ | |
1002 | #define PROTOCOL_T 0xc /* transfer type */ | |
1003 | ||
1004 | /* Bit masks for USB_TXINTERVAL */ | |
1005 | ||
1006 | #define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */ | |
1007 | ||
1008 | /* Bit masks for USB_RXTYPE */ | |
1009 | ||
1010 | #define TARGET_EP_NO_R 0xf /* EP number */ | |
1011 | #define PROTOCOL_R 0xc /* transfer type */ | |
1012 | ||
1013 | /* Bit masks for USB_RXINTERVAL */ | |
1014 | ||
1015 | #define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */ | |
1016 | ||
1017 | /* Bit masks for USB_DMA_INTERRUPT */ | |
1018 | ||
1019 | #define DMA0_INT 0x1 /* DMA0 pending interrupt */ | |
1020 | #define nDMA0_INT 0x0 | |
1021 | #define DMA1_INT 0x2 /* DMA1 pending interrupt */ | |
1022 | #define nDMA1_INT 0x0 | |
1023 | #define DMA2_INT 0x4 /* DMA2 pending interrupt */ | |
1024 | #define nDMA2_INT 0x0 | |
1025 | #define DMA3_INT 0x8 /* DMA3 pending interrupt */ | |
1026 | #define nDMA3_INT 0x0 | |
1027 | #define DMA4_INT 0x10 /* DMA4 pending interrupt */ | |
1028 | #define nDMA4_INT 0x0 | |
1029 | #define DMA5_INT 0x20 /* DMA5 pending interrupt */ | |
1030 | #define nDMA5_INT 0x0 | |
1031 | #define DMA6_INT 0x40 /* DMA6 pending interrupt */ | |
1032 | #define nDMA6_INT 0x0 | |
1033 | #define DMA7_INT 0x80 /* DMA7 pending interrupt */ | |
1034 | #define nDMA7_INT 0x0 | |
1035 | ||
1036 | /* Bit masks for USB_DMAxCONTROL */ | |
1037 | ||
1038 | #define DMA_ENA 0x1 /* DMA enable */ | |
1039 | #define nDMA_ENA 0x0 | |
1040 | #define DIRECTION 0x2 /* direction of DMA transfer */ | |
1041 | #define nDIRECTION 0x0 | |
1042 | #define MODE 0x4 /* DMA Bus error */ | |
1043 | #define nMODE 0x0 | |
1044 | #define INT_ENA 0x8 /* Interrupt enable */ | |
1045 | #define nINT_ENA 0x0 | |
1046 | #define EPNUM 0xf0 /* EP number */ | |
1047 | #define BUSERROR 0x100 /* DMA Bus error */ | |
1048 | #define nBUSERROR 0x0 | |
1049 | ||
1050 | /* Bit masks for USB_DMAxADDRHIGH */ | |
1051 | ||
1052 | #define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */ | |
1053 | ||
1054 | /* Bit masks for USB_DMAxADDRLOW */ | |
1055 | ||
1056 | #define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */ | |
1057 | ||
1058 | /* Bit masks for USB_DMAxCOUNTHIGH */ | |
1059 | ||
1060 | #define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */ | |
1061 | ||
1062 | /* Bit masks for USB_DMAxCOUNTLOW */ | |
1063 | ||
1064 | #define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */ | |
1065 | ||
1066 | #endif /* _DEF_BF527_H */ |