[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / blackfin / mach-bf527 / include / mach / blackfin.h

/*
 * Copyright 2007-2009 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later
 */

#ifndef _MACH_BLACKFIN_H_
#define _MACH_BLACKFIN_H_

#include "bf527.h"
#include "defBF522.h"
#include "anomaly.h"

#if defined(CONFIG_BF527) || defined(CONFIG_BF526)
#include "defBF527.h"
#endif

#if defined(CONFIG_BF525) || defined(CONFIG_BF524)
#include "defBF525.h"
#endif

#if !defined(__ASSEMBLY__)
#include "cdefBF522.h"

#if defined(CONFIG_BF527) || defined(CONFIG_BF526)
#include "cdefBF527.h"
#endif

#if defined(CONFIG_BF525) || defined(CONFIG_BF524)
#include "cdefBF525.h"
#endif
#endif

#define BFIN_UART_NR_PORTS	2

#define OFFSET_THR              0x00	/* Transmit Holding register            */
#define OFFSET_RBR              0x00	/* Receive Buffer register              */
#define OFFSET_DLL              0x00	/* Divisor Latch (Low-Byte)             */
#define OFFSET_IER              0x04	/* Interrupt Enable Register            */
#define OFFSET_DLH              0x04	/* Divisor Latch (High-Byte)            */
#define OFFSET_IIR              0x08	/* Interrupt Identification Register    */
#define OFFSET_LCR              0x0C	/* Line Control Register                */
#define OFFSET_MCR              0x10	/* Modem Control Register               */
#define OFFSET_LSR              0x14	/* Line Status Register                 */
#define OFFSET_MSR              0x18	/* Modem Status Register                */
#define OFFSET_SCR              0x1C	/* SCR Scratch Register                 */
#define OFFSET_GCTL             0x24	/* Global Control Register              */

/* PLL_DIV Masks													*/
#define CCLK_DIV1 CSEL_DIV1	/*          CCLK = VCO / 1                                  */
#define CCLK_DIV2 CSEL_DIV2	/*          CCLK = VCO / 2                                  */
#define CCLK_DIV4 CSEL_DIV4	/*          CCLK = VCO / 4                                  */
#define CCLK_DIV8 CSEL_DIV8	/*          CCLK = VCO / 8                                  */

#endif
Commit	Line	Data
59003145	1	/*
96f1050d	2	* Copyright 2007-2009 Analog Devices Inc.
59003145	3	*
96f1050d	4	* Licensed under the GPL-2 or later
59003145 MH	5	*/
	6
	7	#ifndef _MACH_BLACKFIN_H_
	8	#define _MACH_BLACKFIN_H_
	9
59003145	10	#include "bf527.h"
59003145 MH	11	#include "defBF522.h"
	12	#include "anomaly.h"
	13
7e291434	14	#if defined(CONFIG_BF527) \|\| defined(CONFIG_BF526)
59003145 MH	15	#include "defBF527.h"
	16	#endif
	17
7e291434	18	#if defined(CONFIG_BF525) \|\| defined(CONFIG_BF524)
59003145 MH	19	#include "defBF525.h"
	20	#endif
	21
	22	#if !defined(__ASSEMBLY__)
	23	#include "cdefBF522.h"
	24
7e291434	25	#if defined(CONFIG_BF527) \|\| defined(CONFIG_BF526)
59003145 MH	26	#include "cdefBF527.h"
	27	#endif
	28
7e291434	29	#if defined(CONFIG_BF525) \|\| defined(CONFIG_BF524)
59003145 MH	30	#include "cdefBF525.h"
	31	#endif
	32	#endif
	33
5be36d22 GY	34	#define BFIN_UART_NR_PORTS 2
	35
	36	#define OFFSET_THR 0x00 /* Transmit Holding register */
	37	#define OFFSET_RBR 0x00 /* Receive Buffer register */
	38	#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
	39	#define OFFSET_IER 0x04 /* Interrupt Enable Register */
	40	#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
	41	#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
	42	#define OFFSET_LCR 0x0C /* Line Control Register */
	43	#define OFFSET_MCR 0x10 /* Modem Control Register */
	44	#define OFFSET_LSR 0x14 /* Line Status Register */
	45	#define OFFSET_MSR 0x18 /* Modem Status Register */
	46	#define OFFSET_SCR 0x1C /* SCR Scratch Register */
	47	#define OFFSET_GCTL 0x24 /* Global Control Register */
	48
59003145 MH	49	/* PLL_DIV Masks */
	50	#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
	51	#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
	52	#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
	53	#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
	54
	55	#endif