Commit | Line | Data |
---|---|---|
bc8c84c9 | 1 | /* |
af5d7fc7 MF |
2 | * DO NOT EDIT THIS FILE |
3 | * This file is under version control at | |
4 | * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ | |
5 | * and can be replaced with that version at any time | |
6 | * DO NOT EDIT THIS FILE | |
bc8c84c9 | 7 | * |
af5d7fc7 MF |
8 | * Copyright 2004-2009 Analog Devices Inc. |
9 | * Licensed under the ADI BSD license. | |
10 | * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd | |
bc8c84c9 MF |
11 | */ |
12 | ||
a413647b | 13 | /* This file should be up to date with: |
bd411b15 | 14 | * - Revision D, 08/14/2009; ADSP-BF526 Blackfin Processor Anomaly List |
af5d7fc7 | 15 | * - Revision G, 08/25/2009; ADSP-BF527 Blackfin Processor Anomaly List |
bc8c84c9 MF |
16 | */ |
17 | ||
18 | #ifndef _MACH_ANOMALY_H_ | |
19 | #define _MACH_ANOMALY_H_ | |
20 | ||
a413647b MF |
21 | /* We do not support old silicon - sorry */ |
22 | #if __SILICON_REVISION__ < 0 | |
23 | # error will not work on BF526/BF527 silicon version | |
24 | #endif | |
25 | ||
4e8086d6 MF |
26 | #if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__) |
27 | # define ANOMALY_BF526 1 | |
28 | #else | |
29 | # define ANOMALY_BF526 0 | |
30 | #endif | |
31 | #if defined(__ADSPBF523__) || defined(__ADSPBF525__) || defined(__ADSPBF527__) | |
32 | # define ANOMALY_BF527 1 | |
33 | #else | |
34 | # define ANOMALY_BF527 0 | |
35 | #endif | |
36 | ||
a413647b MF |
37 | #define _ANOMALY_BF526(rev526) (ANOMALY_BF526 && __SILICON_REVISION__ rev526) |
38 | #define _ANOMALY_BF527(rev527) (ANOMALY_BF527 && __SILICON_REVISION__ rev527) | |
39 | #define _ANOMALY_BF526_BF527(rev526, rev527) (_ANOMALY_BF526(rev526) || _ANOMALY_BF527(rev527)) | |
40 | ||
a200ad22 | 41 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ |
bc8c84c9 | 42 | #define ANOMALY_05000074 (1) |
a70ce072 | 43 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ |
3529e041 | 44 | #define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ |
bc8c84c9 MF |
45 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ |
46 | #define ANOMALY_05000122 (1) | |
a413647b | 47 | /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ |
bc8c84c9 | 48 | #define ANOMALY_05000245 (1) |
a413647b MF |
49 | /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ |
50 | #define ANOMALY_05000254 (1) | |
bc8c84c9 MF |
51 | /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ |
52 | #define ANOMALY_05000265 (1) | |
4e8086d6 MF |
53 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ |
54 | #define ANOMALY_05000310 (1) | |
4e8086d6 | 55 | /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ |
a413647b | 56 | #define ANOMALY_05000313 (_ANOMALY_BF526_BF527(< 1, < 2)) |
bc8c84c9 | 57 | /* Incorrect Access of OTP_STATUS During otp_write() Function */ |
a413647b MF |
58 | #define ANOMALY_05000328 (_ANOMALY_BF527(< 2)) |
59 | /* Host DMA Boot Modes Are Not Functional */ | |
60 | #define ANOMALY_05000330 (__SILICON_REVISION__ < 2) | |
bc8c84c9 | 61 | /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ |
a413647b | 62 | #define ANOMALY_05000337 (_ANOMALY_BF527(< 2)) |
4d555630 | 63 | /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ |
a413647b | 64 | #define ANOMALY_05000341 (_ANOMALY_BF527(< 2)) |
4d555630 | 65 | /* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */ |
a413647b | 66 | #define ANOMALY_05000342 (_ANOMALY_BF527(< 2)) |
4d555630 | 67 | /* USB Calibration Value Is Not Initialized */ |
a413647b | 68 | #define ANOMALY_05000346 (_ANOMALY_BF526_BF527(< 1, < 2)) |
202d7bd9 RG |
69 | /* USB Calibration Value to use */ |
70 | #define ANOMALY_05000346_value 0xE510 | |
4d555630 | 71 | /* Preboot Routine Incorrectly Alters Reset Value of USB Register */ |
a413647b | 72 | #define ANOMALY_05000347 (_ANOMALY_BF527(< 2)) |
4d555630 | 73 | /* Security Features Are Not Functional */ |
a413647b | 74 | #define ANOMALY_05000348 (_ANOMALY_BF527(< 1)) |
4e8086d6 | 75 | /* bfrom_SysControl() Firmware Function Performs Improper System Reset */ |
a413647b | 76 | #define ANOMALY_05000353 (_ANOMALY_BF526(< 1)) |
4d555630 | 77 | /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ |
a413647b | 78 | #define ANOMALY_05000355 (_ANOMALY_BF527(< 2)) |
4d555630 | 79 | /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ |
a413647b | 80 | #define ANOMALY_05000357 (_ANOMALY_BF527(< 2)) |
4d555630 | 81 | /* Incorrect Revision Number in DSPID Register */ |
a413647b | 82 | #define ANOMALY_05000364 (_ANOMALY_BF527(== 1)) |
4d555630 SZ |
83 | /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ |
84 | #define ANOMALY_05000366 (1) | |
4e8086d6 | 85 | /* Incorrect Default CSEL Value in PLL_DIV */ |
a413647b | 86 | #define ANOMALY_05000368 (_ANOMALY_BF527(< 2)) |
4d555630 | 87 | /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ |
a413647b | 88 | #define ANOMALY_05000371 (_ANOMALY_BF527(< 2)) |
4d555630 | 89 | /* Authentication Fails To Initiate */ |
a413647b | 90 | #define ANOMALY_05000376 (_ANOMALY_BF527(< 2)) |
4d555630 | 91 | /* Data Read From L3 Memory by USB DMA May be Corrupted */ |
a413647b | 92 | #define ANOMALY_05000380 (_ANOMALY_BF527(< 2)) |
4e8086d6 | 93 | /* 8-Bit NAND Flash Boot Mode Not Functional */ |
a413647b | 94 | #define ANOMALY_05000382 (_ANOMALY_BF526_BF527(< 1, < 2)) |
4e8086d6 | 95 | /* Boot from OTP Memory Not Functional */ |
a413647b | 96 | #define ANOMALY_05000385 (_ANOMALY_BF527(< 2)) |
4e8086d6 | 97 | /* bfrom_SysControl() Firmware Routine Not Functional */ |
a413647b | 98 | #define ANOMALY_05000386 (_ANOMALY_BF527(< 2)) |
4e8086d6 | 99 | /* Programmable Preboot Settings Not Functional */ |
a413647b | 100 | #define ANOMALY_05000387 (_ANOMALY_BF527(< 2)) |
4e8086d6 | 101 | /* CRC32 Checksum Support Not Functional */ |
a413647b | 102 | #define ANOMALY_05000388 (_ANOMALY_BF526_BF527(< 1, < 2)) |
4d555630 | 103 | /* Reset Vector Must Not Be in SDRAM Memory Space */ |
a413647b | 104 | #define ANOMALY_05000389 (_ANOMALY_BF527(< 2)) |
4e8086d6 | 105 | /* pTempCurrent Not Present in ADI_BOOT_DATA Structure */ |
a413647b | 106 | #define ANOMALY_05000392 (_ANOMALY_BF527(< 2)) |
4e8086d6 | 107 | /* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */ |
a413647b | 108 | #define ANOMALY_05000393 (_ANOMALY_BF527(< 2)) |
4e8086d6 | 109 | /* Log Buffer Not Functional */ |
a413647b | 110 | #define ANOMALY_05000394 (_ANOMALY_BF527(< 2)) |
4e8086d6 | 111 | /* Hook Routine Not Functional */ |
a413647b | 112 | #define ANOMALY_05000395 (_ANOMALY_BF527(< 2)) |
4e8086d6 | 113 | /* Header Indirect Bit Not Functional */ |
a413647b | 114 | #define ANOMALY_05000396 (_ANOMALY_BF527(< 2)) |
4e8086d6 | 115 | /* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */ |
a413647b | 116 | #define ANOMALY_05000397 (_ANOMALY_BF527(< 2)) |
4e8086d6 | 117 | /* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */ |
a413647b | 118 | #define ANOMALY_05000398 (_ANOMALY_BF527(< 2)) |
4e8086d6 | 119 | /* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */ |
a413647b | 120 | #define ANOMALY_05000399 (_ANOMALY_BF527(< 2)) |
4d555630 | 121 | /* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */ |
a413647b | 122 | #define ANOMALY_05000401 (_ANOMALY_BF526_BF527(< 1, < 2)) |
4e8086d6 | 123 | /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ |
a413647b | 124 | #define ANOMALY_05000403 (_ANOMALY_BF526_BF527(< 1, < 2)) |
4e8086d6 | 125 | /* Lockbox SESR Disallows Certain User Interrupts */ |
a413647b | 126 | #define ANOMALY_05000404 (_ANOMALY_BF526_BF527(< 1, < 2)) |
4e8086d6 MF |
127 | /* Lockbox SESR Firmware Does Not Save/Restore Full Context */ |
128 | #define ANOMALY_05000405 (1) | |
129 | /* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */ | |
a413647b | 130 | #define ANOMALY_05000407 (_ANOMALY_BF526_BF527(< 1, < 2)) |
4e8086d6 MF |
131 | /* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */ |
132 | #define ANOMALY_05000408 (1) | |
133 | /* Lockbox firmware leaves MDMA0 channel enabled */ | |
a413647b | 134 | #define ANOMALY_05000409 (_ANOMALY_BF526_BF527(< 1, < 2)) |
4e8086d6 | 135 | /* Incorrect Default Internal Voltage Regulator Setting */ |
a413647b | 136 | #define ANOMALY_05000410 (_ANOMALY_BF527(< 2)) |
4e8086d6 | 137 | /* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */ |
a413647b | 138 | #define ANOMALY_05000411 (_ANOMALY_BF526_BF527(< 1, < 2)) |
4e8086d6 | 139 | /* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */ |
a413647b | 140 | #define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2)) |
4e8086d6 | 141 | /* DEB2_URGENT Bit Not Functional */ |
a413647b | 142 | #define ANOMALY_05000415 (_ANOMALY_BF526_BF527(< 1, < 2)) |
4e8086d6 MF |
143 | /* Speculative Fetches Can Cause Undesired External FIFO Operations */ |
144 | #define ANOMALY_05000416 (1) | |
145 | /* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */ | |
a413647b MF |
146 | #define ANOMALY_05000417 (_ANOMALY_BF527(< 2)) |
147 | /* PPI Timing Requirements tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */ | |
148 | #define ANOMALY_05000418 (_ANOMALY_BF526_BF527(< 1, < 2)) | |
4e8086d6 | 149 | /* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */ |
a413647b | 150 | #define ANOMALY_05000420 (_ANOMALY_BF526_BF527(< 1, < 2)) |
4e8086d6 MF |
151 | /* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */ |
152 | #define ANOMALY_05000421 (1) | |
153 | /* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */ | |
a413647b | 154 | #define ANOMALY_05000422 (_ANOMALY_BF526_BF527(> 0, > 1)) |
4e8086d6 | 155 | /* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */ |
a413647b | 156 | #define ANOMALY_05000423 (_ANOMALY_BF526_BF527(< 1, < 2)) |
4e8086d6 | 157 | /* Internal Voltage Regulator Not Trimmed */ |
a413647b | 158 | #define ANOMALY_05000424 (_ANOMALY_BF527(< 2)) |
4e8086d6 | 159 | /* Multichannel SPORT Channel Misalignment Under Specific Configuration */ |
a413647b MF |
160 | #define ANOMALY_05000425 (_ANOMALY_BF526_BF527(< 1, < 2)) |
161 | /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ | |
4e8086d6 MF |
162 | #define ANOMALY_05000426 (1) |
163 | /* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */ | |
a413647b | 164 | #define ANOMALY_05000429 (_ANOMALY_BF526_BF527(< 1, < 2)) |
4e8086d6 | 165 | /* Software System Reset Corrupts PLL_LOCKCNT Register */ |
a413647b MF |
166 | #define ANOMALY_05000430 (_ANOMALY_BF527(> 1)) |
167 | /* Incorrect Use of Stack in Lockbox Firmware During Authentication */ | |
168 | #define ANOMALY_05000431 (1) | |
4e8086d6 | 169 | /* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */ |
a413647b | 170 | #define ANOMALY_05000432 (_ANOMALY_BF526(< 1)) |
94b28211 | 171 | /* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ |
a413647b MF |
172 | #define ANOMALY_05000435 (_ANOMALY_BF526_BF527(< 1, >= 0)) |
173 | /* Preboot Cannot be Used to Alter the PLL_DIV Register */ | |
174 | #define ANOMALY_05000439 (_ANOMALY_BF526_BF527(< 1, >= 0)) | |
175 | /* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */ | |
176 | #define ANOMALY_05000440 (_ANOMALY_BF526_BF527(< 1, >= 0)) | |
177 | /* OTP Write Accesses Not Supported */ | |
178 | #define ANOMALY_05000442 (_ANOMALY_BF527(< 1)) | |
3529e041 MF |
179 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ |
180 | #define ANOMALY_05000443 (1) | |
a413647b MF |
181 | /* The WURESET Bit in the SYSCR Register is not Functional */ |
182 | #define ANOMALY_05000445 (1) | |
bd411b15 | 183 | /* USB DMA Mode 1 Short Packet Data Corruption */ |
976119bc | 184 | #define ANOMALY_05000450 (1) |
a413647b MF |
185 | /* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */ |
186 | #define ANOMALY_05000451 (1) | |
187 | /* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ | |
188 | #define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0)) | |
189 | /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ | |
190 | #define ANOMALY_05000456 (1) | |
191 | /* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */ | |
192 | #define ANOMALY_05000457 (1) | |
bd411b15 YL |
193 | /* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */ |
194 | #define ANOMALY_05000460 (1) | |
a200ad22 | 195 | /* False Hardware Error when RETI Points to Invalid Memory */ |
a413647b | 196 | #define ANOMALY_05000461 (1) |
bd411b15 YL |
197 | /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ |
198 | #define ANOMALY_05000462 (1) | |
a200ad22 MF |
199 | /* USB Rx DMA hang */ |
200 | #define ANOMALY_05000465 (1) | |
bd411b15 YL |
201 | /* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */ |
202 | #define ANOMALY_05000466 (1) | |
a200ad22 MF |
203 | /* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ |
204 | #define ANOMALY_05000467 (1) | |
bd411b15 YL |
205 | /* PLL Latches Incorrect Settings During Reset */ |
206 | #define ANOMALY_05000469 (1) | |
af5d7fc7 MF |
207 | /* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ |
208 | #define ANOMALY_05000473 (1) | |
209 | /* TESTSET Instruction Cannot Be Interrupted */ | |
210 | #define ANOMALY_05000477 (1) | |
bc8c84c9 | 211 | |
2b39331a | 212 | /* Anomalies that don't exist on this proc */ |
a413647b MF |
213 | #define ANOMALY_05000099 (0) |
214 | #define ANOMALY_05000120 (0) | |
59003145 | 215 | #define ANOMALY_05000125 (0) |
a413647b | 216 | #define ANOMALY_05000149 (0) |
59003145 | 217 | #define ANOMALY_05000158 (0) |
a413647b MF |
218 | #define ANOMALY_05000171 (0) |
219 | #define ANOMALY_05000179 (0) | |
a200ad22 | 220 | #define ANOMALY_05000182 (0) |
4d555630 | 221 | #define ANOMALY_05000183 (0) |
976119bc | 222 | #define ANOMALY_05000189 (0) |
4d555630 | 223 | #define ANOMALY_05000198 (0) |
a200ad22 | 224 | #define ANOMALY_05000202 (0) |
a413647b MF |
225 | #define ANOMALY_05000215 (0) |
226 | #define ANOMALY_05000220 (0) | |
227 | #define ANOMALY_05000227 (0) | |
4d555630 | 228 | #define ANOMALY_05000230 (0) |
a413647b MF |
229 | #define ANOMALY_05000231 (0) |
230 | #define ANOMALY_05000233 (0) | |
a200ad22 | 231 | #define ANOMALY_05000234 (0) |
a413647b | 232 | #define ANOMALY_05000242 (0) |
4d555630 | 233 | #define ANOMALY_05000244 (0) |
a413647b MF |
234 | #define ANOMALY_05000248 (0) |
235 | #define ANOMALY_05000250 (0) | |
a200ad22 | 236 | #define ANOMALY_05000257 (0) |
4d555630 | 237 | #define ANOMALY_05000261 (0) |
59003145 | 238 | #define ANOMALY_05000263 (0) |
4d555630 SZ |
239 | #define ANOMALY_05000266 (0) |
240 | #define ANOMALY_05000273 (0) | |
a413647b | 241 | #define ANOMALY_05000274 (0) |
ee554be9 | 242 | #define ANOMALY_05000278 (0) |
a200ad22 MF |
243 | #define ANOMALY_05000281 (0) |
244 | #define ANOMALY_05000283 (0) | |
4e8086d6 | 245 | #define ANOMALY_05000285 (0) |
a413647b MF |
246 | #define ANOMALY_05000287 (0) |
247 | #define ANOMALY_05000301 (0) | |
c18e99cf | 248 | #define ANOMALY_05000305 (0) |
4e8086d6 | 249 | #define ANOMALY_05000307 (0) |
59003145 | 250 | #define ANOMALY_05000311 (0) |
3529e041 | 251 | #define ANOMALY_05000312 (0) |
a200ad22 | 252 | #define ANOMALY_05000315 (0) |
4d555630 | 253 | #define ANOMALY_05000323 (0) |
a413647b | 254 | #define ANOMALY_05000362 (1) |
4d555630 | 255 | #define ANOMALY_05000363 (0) |
a413647b | 256 | #define ANOMALY_05000400 (0) |
bd411b15 | 257 | #define ANOMALY_05000402 (0) |
6651ece9 | 258 | #define ANOMALY_05000412 (0) |
7dbc3f6e MF |
259 | #define ANOMALY_05000447 (0) |
260 | #define ANOMALY_05000448 (0) | |
af5d7fc7 MF |
261 | #define ANOMALY_05000474 (0) |
262 | #define ANOMALY_05000475 (0) | |
4d555630 | 263 | |
bc8c84c9 | 264 | #endif |