[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / blackfin / include / asm / mmu_context.h

/*
 * Copyright 2004-2009 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later.
 */

#ifndef __BLACKFIN_MMU_CONTEXT_H__
#define __BLACKFIN_MMU_CONTEXT_H__

#include <linux/slab.h>
#include <linux/sched.h>
#include <asm/setup.h>
#include <asm/page.h>
#include <asm/pgalloc.h>
#include <asm/cplbinit.h>
#include <asm/sections.h>

/* Note: L1 stacks are CPU-private things, so we bluntly disable this
   feature in SMP mode, and use the per-CPU scratch SRAM bank only to
   store the PDA instead. */

extern void *current_l1_stack_save;
extern int nr_l1stack_tasks;
extern void *l1_stack_base;
extern unsigned long l1_stack_len;

extern int l1sram_free(const void*);
extern void *l1sram_alloc_max(void*);

static inline void free_l1stack(void)
{
	nr_l1stack_tasks--;
	if (nr_l1stack_tasks == 0)
		l1sram_free(l1_stack_base);
}

static inline unsigned long
alloc_l1stack(unsigned long length, unsigned long *stack_base)
{
	if (nr_l1stack_tasks == 0) {
		l1_stack_base = l1sram_alloc_max(&l1_stack_len);
		if (!l1_stack_base)
			return 0;
	}

	if (l1_stack_len < length) {
		if (nr_l1stack_tasks == 0)
			l1sram_free(l1_stack_base);
		return 0;
	}
	*stack_base = (unsigned long)l1_stack_base;
	nr_l1stack_tasks++;
	return l1_stack_len;
}

static inline int
activate_l1stack(struct mm_struct *mm, unsigned long sp_base)
{
	if (current_l1_stack_save)
		memcpy(current_l1_stack_save, l1_stack_base, l1_stack_len);
	mm->context.l1_stack_save = current_l1_stack_save = (void*)sp_base;
	memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len);
	return 1;
}

#define deactivate_mm(tsk,mm)	do { } while (0)

#define activate_mm(prev, next) switch_mm(prev, next, NULL)

static inline void __switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm,
			       struct task_struct *tsk)
{
#ifdef CONFIG_MPU
	unsigned int cpu = smp_processor_id();
#endif
	if (prev_mm == next_mm)
		return;
#ifdef CONFIG_MPU
	if (prev_mm->context.page_rwx_mask == current_rwx_mask[cpu]) {
		flush_switched_cplbs(cpu);
		set_mask_dcplbs(next_mm->context.page_rwx_mask, cpu);
	}
#endif

#ifdef CONFIG_APP_STACK_L1
	/* L1 stack switching.  */
	if (!next_mm->context.l1_stack_save)
		return;
	if (next_mm->context.l1_stack_save == current_l1_stack_save)
		return;
	if (current_l1_stack_save) {
		memcpy(current_l1_stack_save, l1_stack_base, l1_stack_len);
	}
	current_l1_stack_save = next_mm->context.l1_stack_save;
	memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len);
#endif
}

#ifdef CONFIG_IPIPE
#define lock_mm_switch(flags)	local_irq_save_hw_cond(flags)
#define unlock_mm_switch(flags)	local_irq_restore_hw_cond(flags)
#else
#define lock_mm_switch(flags)	do { (void)(flags); } while (0)
#define unlock_mm_switch(flags)	do { (void)(flags); } while (0)
#endif /* CONFIG_IPIPE */

#ifdef CONFIG_MPU
static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
			     struct task_struct *tsk)
{
	unsigned long flags;
	lock_mm_switch(flags);
	__switch_mm(prev, next, tsk);
	unlock_mm_switch(flags);
}

static inline void protect_page(struct mm_struct *mm, unsigned long addr,
				unsigned long flags)
{
	unsigned long *mask = mm->context.page_rwx_mask;
	unsigned long page;
	unsigned long idx;
	unsigned long bit;

	if (unlikely(addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE))
		page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> 12;
	else
		page = addr >> 12;
	idx = page >> 5;
	bit = 1 << (page & 31);

	if (flags & VM_READ)
		mask[idx] |= bit;
	else
		mask[idx] &= ~bit;
	mask += page_mask_nelts;
	if (flags & VM_WRITE)
		mask[idx] |= bit;
	else
		mask[idx] &= ~bit;
	mask += page_mask_nelts;
	if (flags & VM_EXEC)
		mask[idx] |= bit;
	else
		mask[idx] &= ~bit;
}

static inline void update_protections(struct mm_struct *mm)
{
	unsigned int cpu = smp_processor_id();
	if (mm->context.page_rwx_mask == current_rwx_mask[cpu]) {
		flush_switched_cplbs(cpu);
		set_mask_dcplbs(mm->context.page_rwx_mask, cpu);
	}
}
#else /* !CONFIG_MPU */
static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
			     struct task_struct *tsk)
{
	__switch_mm(prev, next, tsk);
}
#endif

static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
{
}

/* Called when creating a new context during fork() or execve().  */
static inline int
init_new_context(struct task_struct *tsk, struct mm_struct *mm)
{
#ifdef CONFIG_MPU
	unsigned long p = __get_free_pages(GFP_KERNEL, page_mask_order);
	mm->context.page_rwx_mask = (unsigned long *)p;
	memset(mm->context.page_rwx_mask, 0,
	       page_mask_nelts * 3 * sizeof(long));
#endif
	return 0;
}

static inline void destroy_context(struct mm_struct *mm)
{
	struct sram_list_struct *tmp;
#ifdef CONFIG_MPU
	unsigned int cpu = smp_processor_id();
#endif

#ifdef CONFIG_APP_STACK_L1
	if (current_l1_stack_save == mm->context.l1_stack_save)
		current_l1_stack_save = 0;
	if (mm->context.l1_stack_save)
		free_l1stack();
#endif

	while ((tmp = mm->context.sram_list)) {
		mm->context.sram_list = tmp->next;
		sram_free(tmp->addr);
		kfree(tmp);
	}
#ifdef CONFIG_MPU
	if (current_rwx_mask[cpu] == mm->context.page_rwx_mask)
		current_rwx_mask[cpu] = NULL;
	free_pages((unsigned long)mm->context.page_rwx_mask, page_mask_order);
#endif
}

#define ipipe_mm_switch_protect(flags)		\
	local_irq_save_hw_cond(flags)

#define ipipe_mm_switch_unprotect(flags)	\
	local_irq_restore_hw_cond(flags)

#endif
Commit	Line	Data
1394f032	1	/*
96f1050d	2	* Copyright 2004-2009 Analog Devices Inc.
1394f032	3	*
96f1050d	4	* Licensed under the GPL-2 or later.
1394f032 BW	5	*/
	6
	7	#ifndef __BLACKFIN_MMU_CONTEXT_H__
	8	#define __BLACKFIN_MMU_CONTEXT_H__
	9
5a0e3ad6	10	#include <linux/slab.h>
b97b8a99	11	#include <linux/sched.h>
1394f032 BW	12	#include <asm/setup.h>
	13	#include <asm/page.h>
	14	#include <asm/pgalloc.h>
b97b8a99	15	#include <asm/cplbinit.h>
e18e7dd3	16	#include <asm/sections.h>
1394f032	17
b8a98989 GY	18	/* Note: L1 stacks are CPU-private things, so we bluntly disable this
	19	feature in SMP mode, and use the per-CPU scratch SRAM bank only to
	20	store the PDA instead. */
	21
1394f032 BW	22	extern void *current_l1_stack_save;
	23	extern int nr_l1stack_tasks;
	24	extern void *l1_stack_base;
	25	extern unsigned long l1_stack_len;
	26
	27	extern int l1sram_free(const void*);
	28	extern void l1sram_alloc_max(void);
	29
1394f032 BW	30	static inline void free_l1stack(void)
	31	{
	32	nr_l1stack_tasks--;
	33	if (nr_l1stack_tasks == 0)
	34	l1sram_free(l1_stack_base);
	35	}
1394f032 BW	36
	37	static inline unsigned long
	38	alloc_l1stack(unsigned long length, unsigned long *stack_base)
	39	{
	40	if (nr_l1stack_tasks == 0) {
	41	l1_stack_base = l1sram_alloc_max(&l1_stack_len);
	42	if (!l1_stack_base)
	43	return 0;
	44	}
	45
	46	if (l1_stack_len < length) {
	47	if (nr_l1stack_tasks == 0)
	48	l1sram_free(l1_stack_base);
	49	return 0;
	50	}
	51	*stack_base = (unsigned long)l1_stack_base;
	52	nr_l1stack_tasks++;
	53	return l1_stack_len;
	54	}
	55
	56	static inline int
	57	activate_l1stack(struct mm_struct *mm, unsigned long sp_base)
	58	{
	59	if (current_l1_stack_save)
	60	memcpy(current_l1_stack_save, l1_stack_base, l1_stack_len);
	61	mm->context.l1_stack_save = current_l1_stack_save = (void*)sp_base;
	62	memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len);
	63	return 1;
	64	}
	65
	66	#define deactivate_mm(tsk,mm) do { } while (0)
	67
b97b8a99 BS	68	#define activate_mm(prev, next) switch_mm(prev, next, NULL)
b97b8a99 BS	69
4815b883 PG	70	static inline void __switch_mm(struct mm_struct prev_mm, struct mm_struct next_mm,
4815b883 PG	71	struct task_struct *tsk)
1394f032	72	{
b8a98989 GY	73	#ifdef CONFIG_MPU
	74	unsigned int cpu = smp_processor_id();
	75	#endif
b97b8a99 BS	76	if (prev_mm == next_mm)
	77	return;
	78	#ifdef CONFIG_MPU
b8a98989 GY	79	if (prev_mm->context.page_rwx_mask == current_rwx_mask[cpu]) {
	80	flush_switched_cplbs(cpu);
	81	set_mask_dcplbs(next_mm->context.page_rwx_mask, cpu);
b97b8a99 BS	82	}
	83	#endif
	84
ca87b7ad	85	#ifdef CONFIG_APP_STACK_L1
b97b8a99	86	/* L1 stack switching. */
1394f032 BW	87	if (!next_mm->context.l1_stack_save)
	88	return;
	89	if (next_mm->context.l1_stack_save == current_l1_stack_save)
	90	return;
	91	if (current_l1_stack_save) {
	92	memcpy(current_l1_stack_save, l1_stack_base, l1_stack_len);
	93	}
	94	current_l1_stack_save = next_mm->context.l1_stack_save;
	95	memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len);
ca87b7ad	96	#endif
1394f032 BW	97	}
1394f032 BW	98
4815b883 PG	99	#ifdef CONFIG_IPIPE
	100	#define lock_mm_switch(flags) local_irq_save_hw_cond(flags)
	101	#define unlock_mm_switch(flags) local_irq_restore_hw_cond(flags)
	102	#else
	103	#define lock_mm_switch(flags) do { (void)(flags); } while (0)
	104	#define unlock_mm_switch(flags) do { (void)(flags); } while (0)
	105	#endif /* CONFIG_IPIPE */
	106
b97b8a99	107	#ifdef CONFIG_MPU
4815b883 PG	108	static inline void switch_mm(struct mm_struct prev, struct mm_struct next,
	109	struct task_struct *tsk)
	110	{
	111	unsigned long flags;
	112	lock_mm_switch(flags);
	113	__switch_mm(prev, next, tsk);
	114	unlock_mm_switch(flags);
	115	}
	116
b97b8a99 BS	117	static inline void protect_page(struct mm_struct *mm, unsigned long addr,
	118	unsigned long flags)
	119	{
	120	unsigned long *mask = mm->context.page_rwx_mask;
e18e7dd3 BS	121	unsigned long page;
	122	unsigned long idx;
	123	unsigned long bit;
	124
	125	if (unlikely(addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE))
	126	page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> 12;
	127	else
	128	page = addr >> 12;
	129	idx = page >> 5;
	130	bit = 1 << (page & 31);
b97b8a99	131
36b84128	132	if (flags & VM_READ)
b97b8a99 BS	133	mask[idx] \|= bit;
	134	else
	135	mask[idx] &= ~bit;
	136	mask += page_mask_nelts;
36b84128	137	if (flags & VM_WRITE)
b97b8a99 BS	138	mask[idx] \|= bit;
	139	else
	140	mask[idx] &= ~bit;
	141	mask += page_mask_nelts;
36b84128	142	if (flags & VM_EXEC)
b97b8a99 BS	143	mask[idx] \|= bit;
	144	else
	145	mask[idx] &= ~bit;
	146	}
	147
	148	static inline void update_protections(struct mm_struct *mm)
1394f032	149	{
b8a98989 GY	150	unsigned int cpu = smp_processor_id();
	151	if (mm->context.page_rwx_mask == current_rwx_mask[cpu]) {
	152	flush_switched_cplbs(cpu);
	153	set_mask_dcplbs(mm->context.page_rwx_mask, cpu);
3d9b7a5c	154	}
1394f032	155	}
4815b883 PG	156	#else /* !CONFIG_MPU */
	157	static inline void switch_mm(struct mm_struct prev, struct mm_struct next,
	158	struct task_struct *tsk)
	159	{
	160	__switch_mm(prev, next, tsk);
	161	}
b97b8a99	162	#endif
1394f032	163
ca87b7ad GY	164	static inline void enter_lazy_tlb(struct mm_struct mm, struct task_struct tsk)
	165	{
	166	}
	167
	168	/* Called when creating a new context during fork() or execve(). */
	169	static inline int
	170	init_new_context(struct task_struct tsk, struct mm_struct mm)
	171	{
	172	#ifdef CONFIG_MPU
	173	unsigned long p = __get_free_pages(GFP_KERNEL, page_mask_order);
	174	mm->context.page_rwx_mask = (unsigned long *)p;
	175	memset(mm->context.page_rwx_mask, 0,
	176	page_mask_nelts * 3 * sizeof(long));
	177	#endif
	178	return 0;
	179	}
	180
	181	static inline void destroy_context(struct mm_struct *mm)
	182	{
	183	struct sram_list_struct *tmp;
b8a98989 GY	184	#ifdef CONFIG_MPU
	185	unsigned int cpu = smp_processor_id();
	186	#endif
ca87b7ad GY	187
	188	#ifdef CONFIG_APP_STACK_L1
	189	if (current_l1_stack_save == mm->context.l1_stack_save)
	190	current_l1_stack_save = 0;
	191	if (mm->context.l1_stack_save)
	192	free_l1stack();
	193	#endif
	194
	195	while ((tmp = mm->context.sram_list)) {
	196	mm->context.sram_list = tmp->next;
	197	sram_free(tmp->addr);
	198	kfree(tmp);
	199	}
	200	#ifdef CONFIG_MPU
b8a98989 GY	201	if (current_rwx_mask[cpu] == mm->context.page_rwx_mask)
b8a98989 GY	202	current_rwx_mask[cpu] = NULL;
ca87b7ad GY	203	free_pages((unsigned long)mm->context.page_rwx_mask, page_mask_order);
	204	#endif
	205	}
	206
4815b883 PG	207	#define ipipe_mm_switch_protect(flags) \
	208	local_irq_save_hw_cond(flags)
	209
	210	#define ipipe_mm_switch_unprotect(flags) \
	211	local_irq_restore_hw_cond(flags)
	212
1394f032	213	#endif