[GitHub/MotorolaMobilityLLC/kernel-slsi.git] / arch / blackfin / include / asm / cacheflush.h

/*
 * Blackfin low-level cache routines
 *
 * Copyright 2004-2009 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later.
 */

#ifndef _BLACKFIN_CACHEFLUSH_H
#define _BLACKFIN_CACHEFLUSH_H

#include <asm/blackfin.h>	/* for SSYNC() */

extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address);
extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address);
extern void blackfin_dcache_invalidate_range(unsigned long start_address, unsigned long end_address);
extern void blackfin_dflush_page(void *page);
extern void blackfin_invalidate_entire_dcache(void);
extern void blackfin_invalidate_entire_icache(void);

#define flush_dcache_mmap_lock(mapping)		do { } while (0)
#define flush_dcache_mmap_unlock(mapping)	do { } while (0)
#define flush_cache_mm(mm)			do { } while (0)
#define flush_cache_range(vma, start, end)	do { } while (0)
#define flush_cache_page(vma, vmaddr)		do { } while (0)
#define flush_cache_vmap(start, end)		do { } while (0)
#define flush_cache_vunmap(start, end)		do { } while (0)

#ifdef CONFIG_SMP
#define flush_icache_range_others(start, end)	\
	smp_icache_flush_range_others((start), (end))
#else
#define flush_icache_range_others(start, end)	do { } while (0)
#endif

static inline void flush_icache_range(unsigned start, unsigned end)
{
#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
	blackfin_dcache_flush_range(start, end);
#endif

	/* Make sure all write buffers in the data side of the core
	 * are flushed before trying to invalidate the icache.  This
	 * needs to be after the data flush and before the icache
	 * flush so that the SSYNC does the right thing in preventing
	 * the instruction prefetcher from hitting things in cached
	 * memory at the wrong time -- it runs much further ahead than
	 * the pipeline.
	 */
	SSYNC();
#if defined(CONFIG_BFIN_ICACHE)
	blackfin_icache_flush_range(start, end);
	flush_icache_range_others(start, end);
#endif
}

#define copy_to_user_page(vma, page, vaddr, dst, src, len)		\
do { memcpy(dst, src, len);						\
     flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len));	\
} while (0)

#define copy_from_user_page(vma, page, vaddr, dst, src, len)	memcpy(dst, src, len)

#if defined(CONFIG_BFIN_DCACHE)
# define invalidate_dcache_range(start,end)	blackfin_dcache_invalidate_range((start), (end))
#else
# define invalidate_dcache_range(start,end)	do { } while (0)
#endif
#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
# define flush_dcache_range(start,end)		blackfin_dcache_flush_range((start), (end))
#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
# define flush_dcache_page(page)		blackfin_dflush_page(page_address(page))
#else
# define flush_dcache_range(start,end)		do { } while (0)
#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
# define flush_dcache_page(page)		do { } while (0)
#endif

extern unsigned long reserved_mem_dcache_on;
extern unsigned long reserved_mem_icache_on;

static inline int bfin_addr_dcacheable(unsigned long addr)
{
#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
	if (addr < (_ramend - DMA_UNCACHED_REGION))
		return 1;
#endif

	if (reserved_mem_dcache_on &&
		addr >= _ramend && addr < physical_mem_end)
		return 1;

#ifdef CONFIG_BFIN_L2_DCACHEABLE
	if (addr >= L2_START && addr < L2_START + L2_LENGTH)
		return 1;
#endif

	return 0;
}

#endif				/* _BLACKFIN_ICACHEFLUSH_H */
Commit	Line	Data
1394f032	1	/*
96f1050d	2	* Blackfin low-level cache routines
1394f032	3	*
96f1050d	4	* Copyright 2004-2009 Analog Devices Inc.
1394f032	5	*
96f1050d	6	* Licensed under the GPL-2 or later.
1394f032 BW	7	*/
	8
	9	#ifndef _BLACKFIN_CACHEFLUSH_H
	10	#define _BLACKFIN_CACHEFLUSH_H
	11
5d89137a MF	12	#include <asm/blackfin.h> /* for SSYNC() */
5d89137a MF	13
8fb4f8f0 MF	14	extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address);
	15	extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address);
	16	extern void blackfin_dcache_invalidate_range(unsigned long start_address, unsigned long end_address);
	17	extern void blackfin_dflush_page(void *page);
6b3087c6	18	extern void blackfin_invalidate_entire_dcache(void);
47e9dedb	19	extern void blackfin_invalidate_entire_icache(void);
1394f032 BW	20
	21	#define flush_dcache_mmap_lock(mapping) do { } while (0)
	22	#define flush_dcache_mmap_unlock(mapping) do { } while (0)
	23	#define flush_cache_mm(mm) do { } while (0)
	24	#define flush_cache_range(vma, start, end) do { } while (0)
	25	#define flush_cache_page(vma, vmaddr) do { } while (0)
	26	#define flush_cache_vmap(start, end) do { } while (0)
	27	#define flush_cache_vunmap(start, end) do { } while (0)
	28
6b3087c6 GY	29	#ifdef CONFIG_SMP
	30	#define flush_icache_range_others(start, end) \
	31	smp_icache_flush_range_others((start), (end))
	32	#else
	33	#define flush_icache_range_others(start, end) do { } while (0)
	34	#endif
	35
1394f032 BW	36	static inline void flush_icache_range(unsigned start, unsigned end)
1394f032 BW	37	{
41ba653f	38	#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) \|\| defined(CONFIG_BFIN_L2_WRITEBACK)
5d89137a MF	39	blackfin_dcache_flush_range(start, end);
5d89137a MF	40	#endif
1394f032	41
5d89137a MF	42	/* Make sure all write buffers in the data side of the core
	43	* are flushed before trying to invalidate the icache. This
	44	* needs to be after the data flush and before the icache
	45	* flush so that the SSYNC does the right thing in preventing
	46	* the instruction prefetcher from hitting things in cached
	47	* memory at the wrong time -- it runs much further ahead than
	48	* the pipeline.
	49	*/
	50	SSYNC();
	51	#if defined(CONFIG_BFIN_ICACHE)
	52	blackfin_icache_flush_range(start, end);
6b3087c6	53	flush_icache_range_others(start, end);
1394f032 BW	54	#endif
	55	}
	56
6b3087c6 GY	57	#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
	58	do { memcpy(dst, src, len); \
	59	flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \
1394f032	60	} while (0)
6b3087c6	61
1394f032 BW	62	#define copy_from_user_page(vma, page, vaddr, dst, src, len) memcpy(dst, src, len)
1394f032 BW	63
3bebca2d	64	#if defined(CONFIG_BFIN_DCACHE)
1394f032 BW	65	# define invalidate_dcache_range(start,end) blackfin_dcache_invalidate_range((start), (end))
	66	#else
	67	# define invalidate_dcache_range(start,end) do { } while (0)
	68	#endif
41ba653f	69	#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) \|\| defined(CONFIG_BFIN_L2_WRITEBACK)
1394f032	70	# define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end))
2d4dc890	71	#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
41ba653f	72	# define flush_dcache_page(page) blackfin_dflush_page(page_address(page))
1394f032 BW	73	#else
1394f032 BW	74	# define flush_dcache_range(start,end) do { } while (0)
2d4dc890	75	#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
6b3087c6	76	# define flush_dcache_page(page) do { } while (0)
1394f032 BW	77	#endif
1394f032 BW	78
04be80ef MF	79	extern unsigned long reserved_mem_dcache_on;
	80	extern unsigned long reserved_mem_icache_on;
	81
67834fa9	82	static inline int bfin_addr_dcacheable(unsigned long addr)
04be80ef	83	{
41ba653f	84	#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
04be80ef MF	85	if (addr < (_ramend - DMA_UNCACHED_REGION))
	86	return 1;
	87	#endif
	88
	89	if (reserved_mem_dcache_on &&
	90	addr >= _ramend && addr < physical_mem_end)
	91	return 1;
	92
41ba653f	93	#ifdef CONFIG_BFIN_L2_DCACHEABLE
f339f46b MF	94	if (addr >= L2_START && addr < L2_START + L2_LENGTH)
	95	return 1;
	96	#endif
	97
04be80ef MF	98	return 0;
	99	}
	100
3bebca2d	101	#endif /* _BLACKFIN_ICACHEFLUSH_H */