Commit | Line | Data |
---|---|---|
1394f032 BW |
1 | # |
2 | # For a description of the syntax of this configuration file, | |
3 | # see Documentation/kbuild/kconfig-language.txt. | |
4 | # | |
5 | ||
53f8a252 | 6 | mainmenu "Blackfin Kernel Configuration" |
1394f032 BW |
7 | |
8 | config MMU | |
bac7d89e | 9 | def_bool n |
1394f032 BW |
10 | |
11 | config FPU | |
bac7d89e | 12 | def_bool n |
1394f032 BW |
13 | |
14 | config RWSEM_GENERIC_SPINLOCK | |
bac7d89e | 15 | def_bool y |
1394f032 BW |
16 | |
17 | config RWSEM_XCHGADD_ALGORITHM | |
bac7d89e | 18 | def_bool n |
1394f032 BW |
19 | |
20 | config BLACKFIN | |
bac7d89e | 21 | def_bool y |
ec7748b5 | 22 | select HAVE_IDE |
538067c8 MF |
23 | select HAVE_KERNEL_GZIP |
24 | select HAVE_KERNEL_BZIP2 | |
25 | select HAVE_KERNEL_LZMA | |
42d4b839 | 26 | select HAVE_OPROFILE |
a4f0b32c | 27 | select ARCH_WANT_OPTIONAL_GPIOLIB |
1394f032 | 28 | |
70f12567 MF |
29 | config GENERIC_BUG |
30 | def_bool y | |
31 | depends on BUG | |
32 | ||
e3defffe | 33 | config ZONE_DMA |
bac7d89e | 34 | def_bool y |
e3defffe | 35 | |
1394f032 | 36 | config GENERIC_FIND_NEXT_BIT |
bac7d89e | 37 | def_bool y |
1394f032 BW |
38 | |
39 | config GENERIC_HWEIGHT | |
bac7d89e | 40 | def_bool y |
1394f032 BW |
41 | |
42 | config GENERIC_HARDIRQS | |
bac7d89e | 43 | def_bool y |
1394f032 BW |
44 | |
45 | config GENERIC_IRQ_PROBE | |
bac7d89e | 46 | def_bool y |
1394f032 | 47 | |
b2d1583f | 48 | config GENERIC_GPIO |
bac7d89e | 49 | def_bool y |
1394f032 BW |
50 | |
51 | config FORCE_MAX_ZONEORDER | |
52 | int | |
53 | default "14" | |
54 | ||
55 | config GENERIC_CALIBRATE_DELAY | |
bac7d89e | 56 | def_bool y |
1394f032 | 57 | |
8f86001f MF |
58 | config TRACE_IRQFLAGS_SUPPORT |
59 | def_bool y | |
60 | ||
1394f032 | 61 | source "init/Kconfig" |
dc52ddc0 | 62 | |
1394f032 BW |
63 | source "kernel/Kconfig.preempt" |
64 | ||
dc52ddc0 MH |
65 | source "kernel/Kconfig.freezer" |
66 | ||
1394f032 BW |
67 | menu "Blackfin Processor Options" |
68 | ||
69 | comment "Processor and Board Settings" | |
70 | ||
71 | choice | |
72 | prompt "CPU" | |
73 | default BF533 | |
74 | ||
2f6f4bcd BW |
75 | config BF512 |
76 | bool "BF512" | |
77 | help | |
78 | BF512 Processor Support. | |
79 | ||
80 | config BF514 | |
81 | bool "BF514" | |
82 | help | |
83 | BF514 Processor Support. | |
84 | ||
85 | config BF516 | |
86 | bool "BF516" | |
87 | help | |
88 | BF516 Processor Support. | |
89 | ||
90 | config BF518 | |
91 | bool "BF518" | |
92 | help | |
93 | BF518 Processor Support. | |
94 | ||
59003145 MH |
95 | config BF522 |
96 | bool "BF522" | |
97 | help | |
98 | BF522 Processor Support. | |
99 | ||
1545a111 MF |
100 | config BF523 |
101 | bool "BF523" | |
102 | help | |
103 | BF523 Processor Support. | |
104 | ||
105 | config BF524 | |
106 | bool "BF524" | |
107 | help | |
108 | BF524 Processor Support. | |
109 | ||
59003145 MH |
110 | config BF525 |
111 | bool "BF525" | |
112 | help | |
113 | BF525 Processor Support. | |
114 | ||
1545a111 MF |
115 | config BF526 |
116 | bool "BF526" | |
117 | help | |
118 | BF526 Processor Support. | |
119 | ||
59003145 MH |
120 | config BF527 |
121 | bool "BF527" | |
122 | help | |
123 | BF527 Processor Support. | |
124 | ||
1394f032 BW |
125 | config BF531 |
126 | bool "BF531" | |
127 | help | |
128 | BF531 Processor Support. | |
129 | ||
130 | config BF532 | |
131 | bool "BF532" | |
132 | help | |
133 | BF532 Processor Support. | |
134 | ||
135 | config BF533 | |
136 | bool "BF533" | |
137 | help | |
138 | BF533 Processor Support. | |
139 | ||
140 | config BF534 | |
141 | bool "BF534" | |
142 | help | |
143 | BF534 Processor Support. | |
144 | ||
145 | config BF536 | |
146 | bool "BF536" | |
147 | help | |
148 | BF536 Processor Support. | |
149 | ||
150 | config BF537 | |
151 | bool "BF537" | |
152 | help | |
153 | BF537 Processor Support. | |
154 | ||
dc26aec2 MH |
155 | config BF538 |
156 | bool "BF538" | |
157 | help | |
158 | BF538 Processor Support. | |
159 | ||
160 | config BF539 | |
161 | bool "BF539" | |
162 | help | |
163 | BF539 Processor Support. | |
164 | ||
24a07a12 RH |
165 | config BF542 |
166 | bool "BF542" | |
167 | help | |
168 | BF542 Processor Support. | |
169 | ||
2f89c063 MF |
170 | config BF542M |
171 | bool "BF542m" | |
172 | help | |
173 | BF542 Processor Support. | |
174 | ||
24a07a12 RH |
175 | config BF544 |
176 | bool "BF544" | |
177 | help | |
178 | BF544 Processor Support. | |
179 | ||
2f89c063 MF |
180 | config BF544M |
181 | bool "BF544m" | |
182 | help | |
183 | BF544 Processor Support. | |
184 | ||
7c7fd170 MF |
185 | config BF547 |
186 | bool "BF547" | |
187 | help | |
188 | BF547 Processor Support. | |
189 | ||
2f89c063 MF |
190 | config BF547M |
191 | bool "BF547m" | |
192 | help | |
193 | BF547 Processor Support. | |
194 | ||
24a07a12 RH |
195 | config BF548 |
196 | bool "BF548" | |
197 | help | |
198 | BF548 Processor Support. | |
199 | ||
2f89c063 MF |
200 | config BF548M |
201 | bool "BF548m" | |
202 | help | |
203 | BF548 Processor Support. | |
204 | ||
24a07a12 RH |
205 | config BF549 |
206 | bool "BF549" | |
207 | help | |
208 | BF549 Processor Support. | |
209 | ||
2f89c063 MF |
210 | config BF549M |
211 | bool "BF549m" | |
212 | help | |
213 | BF549 Processor Support. | |
214 | ||
1394f032 BW |
215 | config BF561 |
216 | bool "BF561" | |
217 | help | |
cd88b4dc | 218 | BF561 Processor Support. |
1394f032 BW |
219 | |
220 | endchoice | |
221 | ||
46fa5eec GY |
222 | config SMP |
223 | depends on BF561 | |
9b9bfded | 224 | select GENERIC_TIME |
46fa5eec GY |
225 | bool "Symmetric multi-processing support" |
226 | ---help--- | |
227 | This enables support for systems with more than one CPU, | |
228 | like the dual core BF561. If you have a system with only one | |
229 | CPU, say N. If you have a system with more than one CPU, say Y. | |
230 | ||
231 | If you don't know what to do here, say N. | |
232 | ||
233 | config NR_CPUS | |
234 | int | |
235 | depends on SMP | |
236 | default 2 if BF561 | |
237 | ||
238 | config IRQ_PER_CPU | |
239 | bool | |
240 | depends on SMP | |
241 | default y | |
242 | ||
0c0497c2 MF |
243 | config BF_REV_MIN |
244 | int | |
2f89c063 | 245 | default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) |
0c0497c2 | 246 | default 2 if (BF537 || BF536 || BF534) |
2f89c063 | 247 | default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM) |
2f6f4bcd | 248 | default 4 if (BF538 || BF539) |
0c0497c2 MF |
249 | |
250 | config BF_REV_MAX | |
251 | int | |
2f89c063 MF |
252 | default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) |
253 | default 3 if (BF537 || BF536 || BF534 || BF54xM) | |
2f6f4bcd | 254 | default 5 if (BF561 || BF538 || BF539) |
0c0497c2 MF |
255 | default 6 if (BF533 || BF532 || BF531) |
256 | ||
1394f032 BW |
257 | choice |
258 | prompt "Silicon Rev" | |
f8b55651 MF |
259 | default BF_REV_0_0 if (BF51x || BF52x) |
260 | default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM)) | |
2f89c063 | 261 | default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561) |
24a07a12 RH |
262 | |
263 | config BF_REV_0_0 | |
264 | bool "0.0" | |
2f89c063 | 265 | depends on (BF51x || BF52x || (BF54x && !BF54xM)) |
59003145 MH |
266 | |
267 | config BF_REV_0_1 | |
d07f4380 | 268 | bool "0.1" |
2f89c063 | 269 | depends on (BF52x || (BF54x && !BF54xM)) |
1394f032 BW |
270 | |
271 | config BF_REV_0_2 | |
272 | bool "0.2" | |
2f89c063 | 273 | depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM)) |
1394f032 BW |
274 | |
275 | config BF_REV_0_3 | |
276 | bool "0.3" | |
2f89c063 | 277 | depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) |
1394f032 BW |
278 | |
279 | config BF_REV_0_4 | |
280 | bool "0.4" | |
dc26aec2 | 281 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
1394f032 BW |
282 | |
283 | config BF_REV_0_5 | |
284 | bool "0.5" | |
dc26aec2 | 285 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
1394f032 | 286 | |
49f7253c MF |
287 | config BF_REV_0_6 |
288 | bool "0.6" | |
289 | depends on (BF533 || BF532 || BF531) | |
290 | ||
de3025f4 JZ |
291 | config BF_REV_ANY |
292 | bool "any" | |
293 | ||
294 | config BF_REV_NONE | |
295 | bool "none" | |
296 | ||
1394f032 BW |
297 | endchoice |
298 | ||
2f6f4bcd BW |
299 | config BF51x |
300 | bool | |
301 | depends on (BF512 || BF514 || BF516 || BF518) | |
302 | default y | |
303 | ||
59003145 MH |
304 | config BF52x |
305 | bool | |
1545a111 | 306 | depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527) |
59003145 MH |
307 | default y |
308 | ||
24a07a12 RH |
309 | config BF53x |
310 | bool | |
311 | depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) | |
312 | default y | |
313 | ||
2f89c063 MF |
314 | config BF54xM |
315 | bool | |
316 | depends on (BF542M || BF544M || BF547M || BF548M || BF549M) | |
317 | default y | |
318 | ||
24a07a12 RH |
319 | config BF54x |
320 | bool | |
2f89c063 | 321 | depends on (BF542 || BF544 || BF547 || BF548 || BF549 || BF54xM) |
24a07a12 RH |
322 | default y |
323 | ||
1394f032 BW |
324 | config MEM_GENERIC_BOARD |
325 | bool | |
326 | depends on GENERIC_BOARD | |
327 | default y | |
328 | ||
329 | config MEM_MT48LC64M4A2FB_7E | |
330 | bool | |
331 | depends on (BFIN533_STAMP) | |
332 | default y | |
333 | ||
334 | config MEM_MT48LC16M16A2TG_75 | |
335 | bool | |
336 | depends on (BFIN533_EZKIT || BFIN561_EZKIT \ | |
ab472a04 | 337 | || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \ |
9db144fe | 338 | || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM) |
1394f032 BW |
339 | default y |
340 | ||
341 | config MEM_MT48LC32M8A2_75 | |
342 | bool | |
dc26aec2 | 343 | depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT) |
1394f032 BW |
344 | default y |
345 | ||
346 | config MEM_MT48LC8M32B2B5_7 | |
347 | bool | |
348 | depends on (BFIN561_BLUETECHNIX_CM) | |
349 | default y | |
350 | ||
59003145 MH |
351 | config MEM_MT48LC32M16A2TG_75 |
352 | bool | |
8cc7117e | 353 | depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD) |
59003145 MH |
354 | default y |
355 | ||
4934540d SZ |
356 | config MEM_MT48LC32M8A2_75 |
357 | bool | |
358 | depends on (BFIN518F_EZBRD) | |
359 | default y | |
360 | ||
2f6f4bcd | 361 | source "arch/blackfin/mach-bf518/Kconfig" |
59003145 | 362 | source "arch/blackfin/mach-bf527/Kconfig" |
1394f032 BW |
363 | source "arch/blackfin/mach-bf533/Kconfig" |
364 | source "arch/blackfin/mach-bf561/Kconfig" | |
365 | source "arch/blackfin/mach-bf537/Kconfig" | |
dc26aec2 | 366 | source "arch/blackfin/mach-bf538/Kconfig" |
24a07a12 | 367 | source "arch/blackfin/mach-bf548/Kconfig" |
1394f032 BW |
368 | |
369 | menu "Board customizations" | |
370 | ||
371 | config CMDLINE_BOOL | |
372 | bool "Default bootloader kernel arguments" | |
373 | ||
374 | config CMDLINE | |
375 | string "Initial kernel command string" | |
376 | depends on CMDLINE_BOOL | |
377 | default "console=ttyBF0,57600" | |
378 | help | |
379 | If you don't have a boot loader capable of passing a command line string | |
380 | to the kernel, you may specify one here. As a minimum, you should specify | |
381 | the memory size and the root device (e.g., mem=8M, root=/dev/nfs). | |
382 | ||
5f004c20 MF |
383 | config BOOT_LOAD |
384 | hex "Kernel load address for booting" | |
385 | default "0x1000" | |
386 | range 0x1000 0x20000000 | |
387 | help | |
388 | This option allows you to set the load address of the kernel. | |
389 | This can be useful if you are on a board which has a small amount | |
390 | of memory or you wish to reserve some memory at the beginning of | |
391 | the address space. | |
392 | ||
393 | Note that you need to keep this value above 4k (0x1000) as this | |
394 | memory region is used to capture NULL pointer references as well | |
395 | as some core kernel functions. | |
396 | ||
8cc7117e MH |
397 | config ROM_BASE |
398 | hex "Kernel ROM Base" | |
86249911 | 399 | depends on ROMKERNEL |
8cc7117e MH |
400 | default "0x20040000" |
401 | range 0x20000000 0x20400000 if !(BF54x || BF561) | |
402 | range 0x20000000 0x30000000 if (BF54x || BF561) | |
403 | help | |
404 | ||
f16295e7 | 405 | comment "Clock/PLL Setup" |
1394f032 BW |
406 | |
407 | config CLKIN_HZ | |
2fb6cb41 | 408 | int "Frequency of the crystal on the board in Hz" |
1394f032 BW |
409 | default "11059200" if BFIN533_STAMP |
410 | default "27000000" if BFIN533_EZKIT | |
2f6f4bcd | 411 | default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT || BFIN518F-EZBRD) |
1394f032 BW |
412 | default "30000000" if BFIN561_EZKIT |
413 | default "24576000" if PNAV10 | |
5d1617b2 | 414 | default "10000000" if BFIN532_IP0X |
1394f032 BW |
415 | help |
416 | The frequency of CLKIN crystal oscillator on the board in Hz. | |
2fb6cb41 SZ |
417 | Warning: This value should match the crystal on the board. Otherwise, |
418 | peripherals won't work properly. | |
1394f032 | 419 | |
f16295e7 RG |
420 | config BFIN_KERNEL_CLOCK |
421 | bool "Re-program Clocks while Kernel boots?" | |
422 | default n | |
423 | help | |
424 | This option decides if kernel clocks are re-programed from the | |
425 | bootloader settings. If the clocks are not set, the SDRAM settings | |
426 | are also not changed, and the Bootloader does 100% of the hardware | |
427 | configuration. | |
428 | ||
429 | config PLL_BYPASS | |
e4e9a7ad MF |
430 | bool "Bypass PLL" |
431 | depends on BFIN_KERNEL_CLOCK | |
432 | default n | |
f16295e7 RG |
433 | |
434 | config CLKIN_HALF | |
435 | bool "Half Clock In" | |
436 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
437 | default n | |
438 | help | |
439 | If this is set the clock will be divided by 2, before it goes to the PLL. | |
440 | ||
441 | config VCO_MULT | |
442 | int "VCO Multiplier" | |
443 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
444 | range 1 64 | |
445 | default "22" if BFIN533_EZKIT | |
446 | default "45" if BFIN533_STAMP | |
dc26aec2 | 447 | default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT) |
f16295e7 | 448 | default "22" if BFIN533_BLUETECHNIX_CM |
9db144fe | 449 | default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) |
f16295e7 | 450 | default "20" if BFIN561_EZKIT |
2f6f4bcd | 451 | default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD) |
f16295e7 RG |
452 | help |
453 | This controls the frequency of the on-chip PLL. This can be between 1 and 64. | |
454 | PLL Frequency = (Crystal Frequency) * (this setting) | |
455 | ||
456 | choice | |
457 | prompt "Core Clock Divider" | |
458 | depends on BFIN_KERNEL_CLOCK | |
459 | default CCLK_DIV_1 | |
460 | help | |
461 | This sets the frequency of the core. It can be 1, 2, 4 or 8 | |
462 | Core Frequency = (PLL frequency) / (this setting) | |
463 | ||
464 | config CCLK_DIV_1 | |
465 | bool "1" | |
466 | ||
467 | config CCLK_DIV_2 | |
468 | bool "2" | |
469 | ||
470 | config CCLK_DIV_4 | |
471 | bool "4" | |
472 | ||
473 | config CCLK_DIV_8 | |
474 | bool "8" | |
475 | endchoice | |
476 | ||
477 | config SCLK_DIV | |
478 | int "System Clock Divider" | |
479 | depends on BFIN_KERNEL_CLOCK | |
480 | range 1 15 | |
5f004c20 | 481 | default 5 |
f16295e7 RG |
482 | help |
483 | This sets the frequency of the system clock (including SDRAM or DDR). | |
484 | This can be between 1 and 15 | |
485 | System Clock = (PLL frequency) / (this setting) | |
486 | ||
5f004c20 MF |
487 | choice |
488 | prompt "DDR SDRAM Chip Type" | |
489 | depends on BFIN_KERNEL_CLOCK | |
490 | depends on BF54x | |
491 | default MEM_MT46V32M16_5B | |
492 | ||
493 | config MEM_MT46V32M16_6T | |
494 | bool "MT46V32M16_6T" | |
495 | ||
496 | config MEM_MT46V32M16_5B | |
497 | bool "MT46V32M16_5B" | |
498 | endchoice | |
499 | ||
73feb5c0 MH |
500 | choice |
501 | prompt "DDR/SDRAM Timing" | |
502 | depends on BFIN_KERNEL_CLOCK | |
503 | default BFIN_KERNEL_CLOCK_MEMINIT_CALC | |
504 | help | |
505 | This option allows you to specify Blackfin SDRAM/DDR Timing parameters | |
506 | The calculated SDRAM timing parameters may not be 100% | |
507 | accurate - This option is therefore marked experimental. | |
508 | ||
509 | config BFIN_KERNEL_CLOCK_MEMINIT_CALC | |
510 | bool "Calculate Timings (EXPERIMENTAL)" | |
511 | depends on EXPERIMENTAL | |
512 | ||
513 | config BFIN_KERNEL_CLOCK_MEMINIT_SPEC | |
514 | bool "Provide accurate Timings based on target SCLK" | |
515 | help | |
516 | Please consult the Blackfin Hardware Reference Manuals as well | |
517 | as the memory device datasheet. | |
518 | http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram | |
519 | endchoice | |
520 | ||
521 | menu "Memory Init Control" | |
522 | depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC | |
523 | ||
524 | config MEM_DDRCTL0 | |
525 | depends on BF54x | |
526 | hex "DDRCTL0" | |
527 | default 0x0 | |
528 | ||
529 | config MEM_DDRCTL1 | |
530 | depends on BF54x | |
531 | hex "DDRCTL1" | |
532 | default 0x0 | |
533 | ||
534 | config MEM_DDRCTL2 | |
535 | depends on BF54x | |
536 | hex "DDRCTL2" | |
537 | default 0x0 | |
538 | ||
539 | config MEM_EBIU_DDRQUE | |
540 | depends on BF54x | |
541 | hex "DDRQUE" | |
542 | default 0x0 | |
543 | ||
544 | config MEM_SDRRC | |
545 | depends on !BF54x | |
546 | hex "SDRRC" | |
547 | default 0x0 | |
548 | ||
549 | config MEM_SDGCTL | |
550 | depends on !BF54x | |
551 | hex "SDGCTL" | |
552 | default 0x0 | |
553 | endmenu | |
554 | ||
f16295e7 RG |
555 | # |
556 | # Max & Min Speeds for various Chips | |
557 | # | |
558 | config MAX_VCO_HZ | |
559 | int | |
2f6f4bcd BW |
560 | default 400000000 if BF512 |
561 | default 400000000 if BF514 | |
562 | default 400000000 if BF516 | |
563 | default 400000000 if BF518 | |
f16295e7 | 564 | default 600000000 if BF522 |
1545a111 MF |
565 | default 400000000 if BF523 |
566 | default 400000000 if BF524 | |
f16295e7 | 567 | default 600000000 if BF525 |
1545a111 | 568 | default 400000000 if BF526 |
f16295e7 RG |
569 | default 600000000 if BF527 |
570 | default 400000000 if BF531 | |
571 | default 400000000 if BF532 | |
572 | default 750000000 if BF533 | |
573 | default 500000000 if BF534 | |
574 | default 400000000 if BF536 | |
575 | default 600000000 if BF537 | |
f72eecb9 RG |
576 | default 533333333 if BF538 |
577 | default 533333333 if BF539 | |
f16295e7 | 578 | default 600000000 if BF542 |
f72eecb9 | 579 | default 533333333 if BF544 |
1545a111 MF |
580 | default 600000000 if BF547 |
581 | default 600000000 if BF548 | |
f72eecb9 | 582 | default 533333333 if BF549 |
f16295e7 RG |
583 | default 600000000 if BF561 |
584 | ||
585 | config MIN_VCO_HZ | |
586 | int | |
587 | default 50000000 | |
588 | ||
589 | config MAX_SCLK_HZ | |
590 | int | |
f72eecb9 | 591 | default 133333333 |
f16295e7 RG |
592 | |
593 | config MIN_SCLK_HZ | |
594 | int | |
595 | default 27000000 | |
596 | ||
597 | comment "Kernel Timer/Scheduler" | |
598 | ||
599 | source kernel/Kconfig.hz | |
600 | ||
8b5f79f9 VM |
601 | config GENERIC_TIME |
602 | bool "Generic time" | |
603 | default y | |
604 | ||
605 | config GENERIC_CLOCKEVENTS | |
606 | bool "Generic clock events" | |
607 | depends on GENERIC_TIME | |
608 | default y | |
609 | ||
1fa9be72 GY |
610 | choice |
611 | prompt "Kernel Tick Source" | |
612 | depends on GENERIC_CLOCKEVENTS | |
613 | default TICKSOURCE_CORETMR | |
614 | ||
615 | config TICKSOURCE_GPTMR0 | |
616 | bool "Gptimer0 (SCLK domain)" | |
617 | select BFIN_GPTIMERS | |
618 | depends on !IPIPE | |
619 | ||
620 | config TICKSOURCE_CORETMR | |
621 | bool "Core timer (CCLK domain)" | |
622 | ||
623 | endchoice | |
624 | ||
8b5f79f9 | 625 | config CYCLES_CLOCKSOURCE |
1fa9be72 | 626 | bool "Use 'CYCLES' as a clocksource" |
8b5f79f9 VM |
627 | depends on GENERIC_CLOCKEVENTS |
628 | depends on !BFIN_SCRATCH_REG_CYCLES | |
1fa9be72 | 629 | depends on !SMP |
8b5f79f9 VM |
630 | help |
631 | If you say Y here, you will enable support for using the 'cycles' | |
632 | registers as a clock source. Doing so means you will be unable to | |
633 | safely write to the 'cycles' register during runtime. You will | |
634 | still be able to read it (such as for performance monitoring), but | |
635 | writing the registers will most likely crash the kernel. | |
636 | ||
1fa9be72 GY |
637 | config GPTMR0_CLOCKSOURCE |
638 | bool "Use GPTimer0 as a clocksource (higher rating)" | |
639 | depends on GENERIC_CLOCKEVENTS | |
640 | depends on !TICKSOURCE_GPTMR0 | |
641 | ||
8b5f79f9 VM |
642 | source kernel/time/Kconfig |
643 | ||
5f004c20 | 644 | comment "Misc" |
971d5bc4 | 645 | |
f0b5d12f MF |
646 | choice |
647 | prompt "Blackfin Exception Scratch Register" | |
648 | default BFIN_SCRATCH_REG_RETN | |
649 | help | |
650 | Select the resource to reserve for the Exception handler: | |
651 | - RETN: Non-Maskable Interrupt (NMI) | |
652 | - RETE: Exception Return (JTAG/ICE) | |
653 | - CYCLES: Performance counter | |
654 | ||
655 | If you are unsure, please select "RETN". | |
656 | ||
657 | config BFIN_SCRATCH_REG_RETN | |
658 | bool "RETN" | |
659 | help | |
660 | Use the RETN register in the Blackfin exception handler | |
661 | as a stack scratch register. This means you cannot | |
662 | safely use NMI on the Blackfin while running Linux, but | |
663 | you can debug the system with a JTAG ICE and use the | |
664 | CYCLES performance registers. | |
665 | ||
666 | If you are unsure, please select "RETN". | |
667 | ||
668 | config BFIN_SCRATCH_REG_RETE | |
669 | bool "RETE" | |
670 | help | |
671 | Use the RETE register in the Blackfin exception handler | |
672 | as a stack scratch register. This means you cannot | |
673 | safely use a JTAG ICE while debugging a Blackfin board, | |
674 | but you can safely use the CYCLES performance registers | |
675 | and the NMI. | |
676 | ||
677 | If you are unsure, please select "RETN". | |
678 | ||
679 | config BFIN_SCRATCH_REG_CYCLES | |
680 | bool "CYCLES" | |
681 | help | |
682 | Use the CYCLES register in the Blackfin exception handler | |
683 | as a stack scratch register. This means you cannot | |
684 | safely use the CYCLES performance registers on a Blackfin | |
685 | board at anytime, but you can debug the system with a JTAG | |
686 | ICE and use the NMI. | |
687 | ||
688 | If you are unsure, please select "RETN". | |
689 | ||
690 | endchoice | |
691 | ||
1394f032 BW |
692 | endmenu |
693 | ||
694 | ||
695 | menu "Blackfin Kernel Optimizations" | |
46fa5eec | 696 | depends on !SMP |
1394f032 | 697 | |
1394f032 BW |
698 | comment "Memory Optimizations" |
699 | ||
700 | config I_ENTRY_L1 | |
701 | bool "Locate interrupt entry code in L1 Memory" | |
702 | default y | |
703 | help | |
01dd2fbf ML |
704 | If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked |
705 | into L1 instruction memory. (less latency) | |
1394f032 BW |
706 | |
707 | config EXCPT_IRQ_SYSC_L1 | |
01dd2fbf | 708 | bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" |
1394f032 BW |
709 | default y |
710 | help | |
01dd2fbf | 711 | If enabled, the entire ASM lowlevel exception and interrupt entry code |
cfefe3c6 | 712 | (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. |
01dd2fbf | 713 | (less latency) |
1394f032 BW |
714 | |
715 | config DO_IRQ_L1 | |
716 | bool "Locate frequently called do_irq dispatcher function in L1 Memory" | |
717 | default y | |
718 | help | |
01dd2fbf ML |
719 | If enabled, the frequently called do_irq dispatcher function is linked |
720 | into L1 instruction memory. (less latency) | |
1394f032 BW |
721 | |
722 | config CORE_TIMER_IRQ_L1 | |
723 | bool "Locate frequently called timer_interrupt() function in L1 Memory" | |
724 | default y | |
725 | help | |
01dd2fbf ML |
726 | If enabled, the frequently called timer_interrupt() function is linked |
727 | into L1 instruction memory. (less latency) | |
1394f032 BW |
728 | |
729 | config IDLE_L1 | |
730 | bool "Locate frequently idle function in L1 Memory" | |
731 | default y | |
732 | help | |
01dd2fbf ML |
733 | If enabled, the frequently called idle function is linked |
734 | into L1 instruction memory. (less latency) | |
1394f032 BW |
735 | |
736 | config SCHEDULE_L1 | |
737 | bool "Locate kernel schedule function in L1 Memory" | |
738 | default y | |
739 | help | |
01dd2fbf ML |
740 | If enabled, the frequently called kernel schedule is linked |
741 | into L1 instruction memory. (less latency) | |
1394f032 BW |
742 | |
743 | config ARITHMETIC_OPS_L1 | |
744 | bool "Locate kernel owned arithmetic functions in L1 Memory" | |
745 | default y | |
746 | help | |
01dd2fbf ML |
747 | If enabled, arithmetic functions are linked |
748 | into L1 instruction memory. (less latency) | |
1394f032 BW |
749 | |
750 | config ACCESS_OK_L1 | |
751 | bool "Locate access_ok function in L1 Memory" | |
752 | default y | |
753 | help | |
01dd2fbf ML |
754 | If enabled, the access_ok function is linked |
755 | into L1 instruction memory. (less latency) | |
1394f032 BW |
756 | |
757 | config MEMSET_L1 | |
758 | bool "Locate memset function in L1 Memory" | |
759 | default y | |
760 | help | |
01dd2fbf ML |
761 | If enabled, the memset function is linked |
762 | into L1 instruction memory. (less latency) | |
1394f032 BW |
763 | |
764 | config MEMCPY_L1 | |
765 | bool "Locate memcpy function in L1 Memory" | |
766 | default y | |
767 | help | |
01dd2fbf ML |
768 | If enabled, the memcpy function is linked |
769 | into L1 instruction memory. (less latency) | |
1394f032 BW |
770 | |
771 | config SYS_BFIN_SPINLOCK_L1 | |
772 | bool "Locate sys_bfin_spinlock function in L1 Memory" | |
773 | default y | |
774 | help | |
01dd2fbf ML |
775 | If enabled, sys_bfin_spinlock function is linked |
776 | into L1 instruction memory. (less latency) | |
1394f032 BW |
777 | |
778 | config IP_CHECKSUM_L1 | |
779 | bool "Locate IP Checksum function in L1 Memory" | |
780 | default n | |
781 | help | |
01dd2fbf ML |
782 | If enabled, the IP Checksum function is linked |
783 | into L1 instruction memory. (less latency) | |
1394f032 BW |
784 | |
785 | config CACHELINE_ALIGNED_L1 | |
786 | bool "Locate cacheline_aligned data to L1 Data Memory" | |
157cc5aa MH |
787 | default y if !BF54x |
788 | default n if BF54x | |
1394f032 BW |
789 | depends on !BF531 |
790 | help | |
692105b8 | 791 | If enabled, cacheline_aligned data is linked |
01dd2fbf | 792 | into L1 data memory. (less latency) |
1394f032 BW |
793 | |
794 | config SYSCALL_TAB_L1 | |
795 | bool "Locate Syscall Table L1 Data Memory" | |
796 | default n | |
797 | depends on !BF531 | |
798 | help | |
01dd2fbf ML |
799 | If enabled, the Syscall LUT is linked |
800 | into L1 data memory. (less latency) | |
1394f032 BW |
801 | |
802 | config CPLB_SWITCH_TAB_L1 | |
803 | bool "Locate CPLB Switch Tables L1 Data Memory" | |
804 | default n | |
805 | depends on !BF531 | |
806 | help | |
01dd2fbf ML |
807 | If enabled, the CPLB Switch Tables are linked |
808 | into L1 data memory. (less latency) | |
1394f032 | 809 | |
ca87b7ad GY |
810 | config APP_STACK_L1 |
811 | bool "Support locating application stack in L1 Scratch Memory" | |
812 | default y | |
813 | help | |
814 | If enabled the application stack can be located in L1 | |
815 | scratch memory (less latency). | |
816 | ||
817 | Currently only works with FLAT binaries. | |
818 | ||
6ad2b84c MF |
819 | config EXCEPTION_L1_SCRATCH |
820 | bool "Locate exception stack in L1 Scratch Memory" | |
821 | default n | |
f82e0a0c | 822 | depends on !APP_STACK_L1 |
6ad2b84c MF |
823 | help |
824 | Whenever an exception occurs, use the L1 Scratch memory for | |
825 | stack storage. You cannot place the stacks of FLAT binaries | |
826 | in L1 when using this option. | |
827 | ||
828 | If you don't use L1 Scratch, then you should say Y here. | |
829 | ||
251383c7 RG |
830 | comment "Speed Optimizations" |
831 | config BFIN_INS_LOWOVERHEAD | |
832 | bool "ins[bwl] low overhead, higher interrupt latency" | |
833 | default y | |
834 | help | |
835 | Reads on the Blackfin are speculative. In Blackfin terms, this means | |
836 | they can be interrupted at any time (even after they have been issued | |
837 | on to the external bus), and re-issued after the interrupt occurs. | |
838 | For memory - this is not a big deal, since memory does not change if | |
839 | it sees a read. | |
840 | ||
841 | If a FIFO is sitting on the end of the read, it will see two reads, | |
842 | when the core only sees one since the FIFO receives both the read | |
843 | which is cancelled (and not delivered to the core) and the one which | |
844 | is re-issued (which is delivered to the core). | |
845 | ||
846 | To solve this, interrupts are turned off before reads occur to | |
847 | I/O space. This option controls which the overhead/latency of | |
848 | controlling interrupts during this time | |
849 | "n" turns interrupts off every read | |
850 | (higher overhead, but lower interrupt latency) | |
851 | "y" turns interrupts off every loop | |
852 | (low overhead, but longer interrupt latency) | |
853 | ||
854 | default behavior is to leave this set to on (type "Y"). If you are experiencing | |
855 | interrupt latency issues, it is safe and OK to turn this off. | |
856 | ||
1394f032 BW |
857 | endmenu |
858 | ||
1394f032 BW |
859 | choice |
860 | prompt "Kernel executes from" | |
861 | help | |
862 | Choose the memory type that the kernel will be running in. | |
863 | ||
864 | config RAMKERNEL | |
865 | bool "RAM" | |
866 | help | |
867 | The kernel will be resident in RAM when running. | |
868 | ||
869 | config ROMKERNEL | |
870 | bool "ROM" | |
871 | help | |
872 | The kernel will be resident in FLASH/ROM when running. | |
873 | ||
874 | endchoice | |
875 | ||
876 | source "mm/Kconfig" | |
877 | ||
780431e3 MF |
878 | config BFIN_GPTIMERS |
879 | tristate "Enable Blackfin General Purpose Timers API" | |
880 | default n | |
881 | help | |
882 | Enable support for the General Purpose Timers API. If you | |
883 | are unsure, say N. | |
884 | ||
885 | To compile this driver as a module, choose M here: the module | |
886 | will be called gptimers.ko. | |
887 | ||
1394f032 | 888 | choice |
d292b000 | 889 | prompt "Uncached DMA region" |
1394f032 | 890 | default DMA_UNCACHED_1M |
86ad7932 CC |
891 | config DMA_UNCACHED_4M |
892 | bool "Enable 4M DMA region" | |
1394f032 BW |
893 | config DMA_UNCACHED_2M |
894 | bool "Enable 2M DMA region" | |
895 | config DMA_UNCACHED_1M | |
896 | bool "Enable 1M DMA region" | |
897 | config DMA_UNCACHED_NONE | |
898 | bool "Disable DMA region" | |
899 | endchoice | |
900 | ||
901 | ||
902 | comment "Cache Support" | |
3bebca2d | 903 | config BFIN_ICACHE |
1394f032 | 904 | bool "Enable ICACHE" |
3bebca2d | 905 | config BFIN_DCACHE |
1394f032 | 906 | bool "Enable DCACHE" |
3bebca2d | 907 | config BFIN_DCACHE_BANKA |
1394f032 | 908 | bool "Enable only 16k BankA DCACHE - BankB is SRAM" |
3bebca2d | 909 | depends on BFIN_DCACHE && !BF531 |
1394f032 | 910 | default n |
3bebca2d RG |
911 | config BFIN_ICACHE_LOCK |
912 | bool "Enable Instruction Cache Locking" | |
1394f032 BW |
913 | |
914 | choice | |
5ba76675 | 915 | prompt "External memory cache policy" |
3bebca2d | 916 | depends on BFIN_DCACHE |
46fa5eec GY |
917 | default BFIN_WB if !SMP |
918 | default BFIN_WT if SMP | |
3bebca2d | 919 | config BFIN_WB |
1394f032 | 920 | bool "Write back" |
46fa5eec | 921 | depends on !SMP |
1394f032 BW |
922 | help |
923 | Write Back Policy: | |
924 | Cached data will be written back to SDRAM only when needed. | |
925 | This can give a nice increase in performance, but beware of | |
926 | broken drivers that do not properly invalidate/flush their | |
927 | cache. | |
928 | ||
929 | Write Through Policy: | |
930 | Cached data will always be written back to SDRAM when the | |
931 | cache is updated. This is a completely safe setting, but | |
932 | performance is worse than Write Back. | |
933 | ||
934 | If you are unsure of the options and you want to be safe, | |
935 | then go with Write Through. | |
936 | ||
3bebca2d | 937 | config BFIN_WT |
1394f032 BW |
938 | bool "Write through" |
939 | help | |
940 | Write Back Policy: | |
941 | Cached data will be written back to SDRAM only when needed. | |
942 | This can give a nice increase in performance, but beware of | |
943 | broken drivers that do not properly invalidate/flush their | |
944 | cache. | |
945 | ||
946 | Write Through Policy: | |
947 | Cached data will always be written back to SDRAM when the | |
948 | cache is updated. This is a completely safe setting, but | |
949 | performance is worse than Write Back. | |
950 | ||
951 | If you are unsure of the options and you want to be safe, | |
952 | then go with Write Through. | |
953 | ||
954 | endchoice | |
955 | ||
5ba76675 GY |
956 | choice |
957 | prompt "L2 SRAM cache policy" | |
958 | depends on (BF54x || BF561) | |
959 | default BFIN_L2_WT | |
960 | config BFIN_L2_WB | |
961 | bool "Write back" | |
962 | depends on !SMP | |
963 | ||
964 | config BFIN_L2_WT | |
965 | bool "Write through" | |
966 | depends on !SMP | |
967 | ||
968 | config BFIN_L2_NOT_CACHED | |
969 | bool "Not cached" | |
970 | ||
971 | endchoice | |
f099f39a | 972 | |
b97b8a99 BS |
973 | config MPU |
974 | bool "Enable the memory protection unit (EXPERIMENTAL)" | |
975 | default n | |
976 | help | |
977 | Use the processor's MPU to protect applications from accessing | |
978 | memory they do not own. This comes at a performance penalty | |
979 | and is recommended only for debugging. | |
980 | ||
692105b8 | 981 | comment "Asynchronous Memory Configuration" |
1394f032 | 982 | |
ddf416b2 | 983 | menu "EBIU_AMGCTL Global Control" |
1394f032 BW |
984 | config C_AMCKEN |
985 | bool "Enable CLKOUT" | |
986 | default y | |
987 | ||
988 | config C_CDPRIO | |
989 | bool "DMA has priority over core for ext. accesses" | |
990 | default n | |
991 | ||
992 | config C_B0PEN | |
993 | depends on BF561 | |
994 | bool "Bank 0 16 bit packing enable" | |
995 | default y | |
996 | ||
997 | config C_B1PEN | |
998 | depends on BF561 | |
999 | bool "Bank 1 16 bit packing enable" | |
1000 | default y | |
1001 | ||
1002 | config C_B2PEN | |
1003 | depends on BF561 | |
1004 | bool "Bank 2 16 bit packing enable" | |
1005 | default y | |
1006 | ||
1007 | config C_B3PEN | |
1008 | depends on BF561 | |
1009 | bool "Bank 3 16 bit packing enable" | |
1010 | default n | |
1011 | ||
1012 | choice | |
692105b8 | 1013 | prompt "Enable Asynchronous Memory Banks" |
1394f032 BW |
1014 | default C_AMBEN_ALL |
1015 | ||
1016 | config C_AMBEN | |
1017 | bool "Disable All Banks" | |
1018 | ||
1019 | config C_AMBEN_B0 | |
1020 | bool "Enable Bank 0" | |
1021 | ||
1022 | config C_AMBEN_B0_B1 | |
1023 | bool "Enable Bank 0 & 1" | |
1024 | ||
1025 | config C_AMBEN_B0_B1_B2 | |
1026 | bool "Enable Bank 0 & 1 & 2" | |
1027 | ||
1028 | config C_AMBEN_ALL | |
1029 | bool "Enable All Banks" | |
1030 | endchoice | |
1031 | endmenu | |
1032 | ||
1033 | menu "EBIU_AMBCTL Control" | |
1034 | config BANK_0 | |
c8342f87 | 1035 | hex "Bank 0 (AMBCTL0.L)" |
1394f032 | 1036 | default 0x7BB0 |
c8342f87 MF |
1037 | help |
1038 | These are the low 16 bits of the EBIU_AMBCTL0 MMR which are | |
1039 | used to control the Asynchronous Memory Bank 0 settings. | |
1394f032 BW |
1040 | |
1041 | config BANK_1 | |
c8342f87 | 1042 | hex "Bank 1 (AMBCTL0.H)" |
1394f032 | 1043 | default 0x7BB0 |
197fba56 | 1044 | default 0x5558 if BF54x |
c8342f87 MF |
1045 | help |
1046 | These are the high 16 bits of the EBIU_AMBCTL0 MMR which are | |
1047 | used to control the Asynchronous Memory Bank 1 settings. | |
1394f032 BW |
1048 | |
1049 | config BANK_2 | |
c8342f87 | 1050 | hex "Bank 2 (AMBCTL1.L)" |
1394f032 | 1051 | default 0x7BB0 |
c8342f87 MF |
1052 | help |
1053 | These are the low 16 bits of the EBIU_AMBCTL1 MMR which are | |
1054 | used to control the Asynchronous Memory Bank 2 settings. | |
1394f032 BW |
1055 | |
1056 | config BANK_3 | |
c8342f87 | 1057 | hex "Bank 3 (AMBCTL1.H)" |
1394f032 | 1058 | default 0x99B3 |
c8342f87 MF |
1059 | help |
1060 | These are the high 16 bits of the EBIU_AMBCTL1 MMR which are | |
1061 | used to control the Asynchronous Memory Bank 3 settings. | |
1062 | ||
1394f032 BW |
1063 | endmenu |
1064 | ||
e40540b3 SZ |
1065 | config EBIU_MBSCTLVAL |
1066 | hex "EBIU Bank Select Control Register" | |
1067 | depends on BF54x | |
1068 | default 0 | |
1069 | ||
1070 | config EBIU_MODEVAL | |
1071 | hex "Flash Memory Mode Control Register" | |
1072 | depends on BF54x | |
1073 | default 1 | |
1074 | ||
1075 | config EBIU_FCTLVAL | |
1076 | hex "Flash Memory Bank Control Register" | |
1077 | depends on BF54x | |
1078 | default 6 | |
1394f032 BW |
1079 | endmenu |
1080 | ||
1081 | ############################################################################# | |
1082 | menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" | |
1083 | ||
1084 | config PCI | |
1085 | bool "PCI support" | |
a95ca3b2 | 1086 | depends on BROKEN |
1394f032 BW |
1087 | help |
1088 | Support for PCI bus. | |
1089 | ||
1090 | source "drivers/pci/Kconfig" | |
1091 | ||
1092 | config HOTPLUG | |
1093 | bool "Support for hot-pluggable device" | |
1094 | help | |
1095 | Say Y here if you want to plug devices into your computer while | |
1096 | the system is running, and be able to use them quickly. In many | |
1097 | cases, the devices can likewise be unplugged at any time too. | |
1098 | ||
1099 | One well known example of this is PCMCIA- or PC-cards, credit-card | |
1100 | size devices such as network cards, modems or hard drives which are | |
1101 | plugged into slots found on all modern laptop computers. Another | |
1102 | example, used on modern desktops as well as laptops, is USB. | |
1103 | ||
a81792f6 JB |
1104 | Enable HOTPLUG and build a modular kernel. Get agent software |
1105 | (from <http://linux-hotplug.sourceforge.net/>) and install it. | |
1394f032 BW |
1106 | Then your kernel will automatically call out to a user mode "policy |
1107 | agent" (/sbin/hotplug) to load modules and set up software needed | |
1108 | to use devices as you hotplug them. | |
1109 | ||
1110 | source "drivers/pcmcia/Kconfig" | |
1111 | ||
1112 | source "drivers/pci/hotplug/Kconfig" | |
1113 | ||
1114 | endmenu | |
1115 | ||
1116 | menu "Executable file formats" | |
1117 | ||
1118 | source "fs/Kconfig.binfmt" | |
1119 | ||
1120 | endmenu | |
1121 | ||
1122 | menu "Power management options" | |
1123 | source "kernel/power/Kconfig" | |
1124 | ||
f4cb5700 JB |
1125 | config ARCH_SUSPEND_POSSIBLE |
1126 | def_bool y | |
1127 | depends on !SMP | |
1128 | ||
1394f032 | 1129 | choice |
1efc80b5 | 1130 | prompt "Standby Power Saving Mode" |
1394f032 | 1131 | depends on PM |
cfefe3c6 MH |
1132 | default PM_BFIN_SLEEP_DEEPER |
1133 | config PM_BFIN_SLEEP_DEEPER | |
1134 | bool "Sleep Deeper" | |
1135 | help | |
1136 | Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic | |
1137 | power dissipation by disabling the clock to the processor core (CCLK). | |
1138 | Furthermore, Standby sets the internal power supply voltage (VDDINT) | |
1139 | to 0.85 V to provide the greatest power savings, while preserving the | |
1140 | processor state. | |
1141 | The PLL and system clock (SCLK) continue to operate at a very low | |
1142 | frequency of about 3.3 MHz. To preserve data integrity in the SDRAM, | |
1143 | the SDRAM is put into Self Refresh Mode. Typically an external event | |
1144 | such as GPIO interrupt or RTC activity wakes up the processor. | |
1145 | Various Peripherals such as UART, SPORT, PPI may not function as | |
1146 | normal during Sleep Deeper, due to the reduced SCLK frequency. | |
1147 | When in the sleep mode, system DMA access to L1 memory is not supported. | |
1148 | ||
1efc80b5 MH |
1149 | If unsure, select "Sleep Deeper". |
1150 | ||
cfefe3c6 MH |
1151 | config PM_BFIN_SLEEP |
1152 | bool "Sleep" | |
1153 | help | |
1154 | Sleep Mode (High Power Savings) - The sleep mode reduces power | |
1155 | dissipation by disabling the clock to the processor core (CCLK). | |
1156 | The PLL and system clock (SCLK), however, continue to operate in | |
1157 | this mode. Typically an external event or RTC activity will wake | |
1efc80b5 MH |
1158 | up the processor. When in the sleep mode, system DMA access to L1 |
1159 | memory is not supported. | |
1160 | ||
1161 | If unsure, select "Sleep Deeper". | |
cfefe3c6 | 1162 | endchoice |
1394f032 | 1163 | |
1394f032 | 1164 | config PM_WAKEUP_BY_GPIO |
1efc80b5 | 1165 | bool "Allow Wakeup from Standby by GPIO" |
ff19fed4 | 1166 | depends on PM && !BF54x |
1394f032 BW |
1167 | |
1168 | config PM_WAKEUP_GPIO_NUMBER | |
1efc80b5 | 1169 | int "GPIO number" |
1394f032 BW |
1170 | range 0 47 |
1171 | depends on PM_WAKEUP_BY_GPIO | |
d1a3336e | 1172 | default 2 |
1394f032 BW |
1173 | |
1174 | choice | |
1175 | prompt "GPIO Polarity" | |
1176 | depends on PM_WAKEUP_BY_GPIO | |
1177 | default PM_WAKEUP_GPIO_POLAR_H | |
1178 | config PM_WAKEUP_GPIO_POLAR_H | |
1179 | bool "Active High" | |
1180 | config PM_WAKEUP_GPIO_POLAR_L | |
1181 | bool "Active Low" | |
1182 | config PM_WAKEUP_GPIO_POLAR_EDGE_F | |
1183 | bool "Falling EDGE" | |
1184 | config PM_WAKEUP_GPIO_POLAR_EDGE_R | |
1185 | bool "Rising EDGE" | |
1186 | config PM_WAKEUP_GPIO_POLAR_EDGE_B | |
1187 | bool "Both EDGE" | |
1188 | endchoice | |
1189 | ||
1efc80b5 MH |
1190 | comment "Possible Suspend Mem / Hibernate Wake-Up Sources" |
1191 | depends on PM | |
1192 | ||
1efc80b5 MH |
1193 | config PM_BFIN_WAKE_PH6 |
1194 | bool "Allow Wake-Up from on-chip PHY or PH6 GP" | |
2f6f4bcd | 1195 | depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537) |
1efc80b5 MH |
1196 | default n |
1197 | help | |
1198 | Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up) | |
1199 | ||
1efc80b5 MH |
1200 | config PM_BFIN_WAKE_GP |
1201 | bool "Allow Wake-Up from GPIOs" | |
1202 | depends on PM && BF54x | |
1203 | default n | |
1204 | help | |
1205 | Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) | |
19986289 MH |
1206 | (all processors, except ADSP-BF549). This option sets |
1207 | the general-purpose wake-up enable (GPWE) control bit to enable | |
1208 | wake-up upon detection of an active low signal on the /GPW (PH7) pin. | |
1209 | On ADSP-BF549 this option enables the the same functionality on the | |
1210 | /MRXON pin also PH7. | |
1211 | ||
1394f032 BW |
1212 | endmenu |
1213 | ||
1394f032 BW |
1214 | menu "CPU Frequency scaling" |
1215 | ||
1216 | source "drivers/cpufreq/Kconfig" | |
1217 | ||
5ad2ca5f MH |
1218 | config BFIN_CPU_FREQ |
1219 | bool | |
1220 | depends on CPU_FREQ | |
1221 | select CPU_FREQ_TABLE | |
1222 | default y | |
1223 | ||
14b03204 MH |
1224 | config CPU_VOLTAGE |
1225 | bool "CPU Voltage scaling" | |
73feb5c0 | 1226 | depends on EXPERIMENTAL |
14b03204 MH |
1227 | depends on CPU_FREQ |
1228 | default n | |
1229 | help | |
1230 | Say Y here if you want CPU voltage scaling according to the CPU frequency. | |
1231 | This option violates the PLL BYPASS recommendation in the Blackfin Processor | |
73feb5c0 | 1232 | manuals. There is a theoretical risk that during VDDINT transitions |
14b03204 MH |
1233 | the PLL may unlock. |
1234 | ||
1394f032 BW |
1235 | endmenu |
1236 | ||
1394f032 BW |
1237 | source "net/Kconfig" |
1238 | ||
1239 | source "drivers/Kconfig" | |
1240 | ||
1241 | source "fs/Kconfig" | |
1242 | ||
74ce8322 | 1243 | source "arch/blackfin/Kconfig.debug" |
1394f032 BW |
1244 | |
1245 | source "security/Kconfig" | |
1246 | ||
1247 | source "crypto/Kconfig" | |
1248 | ||
1249 | source "lib/Kconfig" |