Commit | Line | Data |
---|---|---|
1394f032 BW |
1 | # |
2 | # For a description of the syntax of this configuration file, | |
3 | # see Documentation/kbuild/kconfig-language.txt. | |
4 | # | |
5 | ||
53f8a252 | 6 | mainmenu "Blackfin Kernel Configuration" |
1394f032 BW |
7 | |
8 | config MMU | |
9 | bool | |
10 | default n | |
11 | ||
12 | config FPU | |
13 | bool | |
14 | default n | |
15 | ||
16 | config RWSEM_GENERIC_SPINLOCK | |
17 | bool | |
18 | default y | |
19 | ||
20 | config RWSEM_XCHGADD_ALGORITHM | |
21 | bool | |
22 | default n | |
23 | ||
24 | config BLACKFIN | |
25 | bool | |
26 | default y | |
42d4b839 | 27 | select HAVE_OPROFILE |
1394f032 | 28 | |
e3defffe AL |
29 | config ZONE_DMA |
30 | bool | |
31 | default y | |
32 | ||
1394f032 BW |
33 | config SEMAPHORE_SLEEPERS |
34 | bool | |
35 | default y | |
36 | ||
37 | config GENERIC_FIND_NEXT_BIT | |
38 | bool | |
39 | default y | |
40 | ||
41 | config GENERIC_HWEIGHT | |
42 | bool | |
43 | default y | |
44 | ||
45 | config GENERIC_HARDIRQS | |
46 | bool | |
47 | default y | |
48 | ||
49 | config GENERIC_IRQ_PROBE | |
e4e9a7ad | 50 | bool |
1394f032 BW |
51 | default y |
52 | ||
53 | config GENERIC_TIME | |
54 | bool | |
55 | default n | |
56 | ||
b2d1583f | 57 | config GENERIC_GPIO |
1394f032 BW |
58 | bool |
59 | default y | |
60 | ||
61 | config FORCE_MAX_ZONEORDER | |
62 | int | |
63 | default "14" | |
64 | ||
65 | config GENERIC_CALIBRATE_DELAY | |
66 | bool | |
67 | default y | |
68 | ||
7d2284b0 MD |
69 | config HARDWARE_PM |
70 | def_bool y | |
71 | depends on OPROFILE | |
72 | ||
1394f032 BW |
73 | source "init/Kconfig" |
74 | source "kernel/Kconfig.preempt" | |
75 | ||
76 | menu "Blackfin Processor Options" | |
77 | ||
78 | comment "Processor and Board Settings" | |
79 | ||
80 | choice | |
81 | prompt "CPU" | |
82 | default BF533 | |
83 | ||
59003145 MH |
84 | config BF522 |
85 | bool "BF522" | |
86 | help | |
87 | BF522 Processor Support. | |
88 | ||
1545a111 MF |
89 | config BF523 |
90 | bool "BF523" | |
91 | help | |
92 | BF523 Processor Support. | |
93 | ||
94 | config BF524 | |
95 | bool "BF524" | |
96 | help | |
97 | BF524 Processor Support. | |
98 | ||
59003145 MH |
99 | config BF525 |
100 | bool "BF525" | |
101 | help | |
102 | BF525 Processor Support. | |
103 | ||
1545a111 MF |
104 | config BF526 |
105 | bool "BF526" | |
106 | help | |
107 | BF526 Processor Support. | |
108 | ||
59003145 MH |
109 | config BF527 |
110 | bool "BF527" | |
111 | help | |
112 | BF527 Processor Support. | |
113 | ||
1394f032 BW |
114 | config BF531 |
115 | bool "BF531" | |
116 | help | |
117 | BF531 Processor Support. | |
118 | ||
119 | config BF532 | |
120 | bool "BF532" | |
121 | help | |
122 | BF532 Processor Support. | |
123 | ||
124 | config BF533 | |
125 | bool "BF533" | |
126 | help | |
127 | BF533 Processor Support. | |
128 | ||
129 | config BF534 | |
130 | bool "BF534" | |
131 | help | |
132 | BF534 Processor Support. | |
133 | ||
134 | config BF536 | |
135 | bool "BF536" | |
136 | help | |
137 | BF536 Processor Support. | |
138 | ||
139 | config BF537 | |
140 | bool "BF537" | |
141 | help | |
142 | BF537 Processor Support. | |
143 | ||
24a07a12 RH |
144 | config BF542 |
145 | bool "BF542" | |
146 | help | |
147 | BF542 Processor Support. | |
148 | ||
149 | config BF544 | |
150 | bool "BF544" | |
151 | help | |
152 | BF544 Processor Support. | |
153 | ||
7c7fd170 MF |
154 | config BF547 |
155 | bool "BF547" | |
156 | help | |
157 | BF547 Processor Support. | |
158 | ||
24a07a12 RH |
159 | config BF548 |
160 | bool "BF548" | |
161 | help | |
162 | BF548 Processor Support. | |
163 | ||
164 | config BF549 | |
165 | bool "BF549" | |
166 | help | |
167 | BF549 Processor Support. | |
168 | ||
1394f032 BW |
169 | config BF561 |
170 | bool "BF561" | |
171 | help | |
172 | Not Supported Yet - Work in progress - BF561 Processor Support. | |
173 | ||
174 | endchoice | |
175 | ||
176 | choice | |
177 | prompt "Silicon Rev" | |
59003145 | 178 | default BF_REV_0_1 if BF527 |
1394f032 BW |
179 | default BF_REV_0_2 if BF537 |
180 | default BF_REV_0_3 if BF533 | |
24a07a12 RH |
181 | default BF_REV_0_0 if BF549 |
182 | ||
183 | config BF_REV_0_0 | |
184 | bool "0.0" | |
d07f4380 | 185 | depends on (BF52x || BF54x) |
59003145 MH |
186 | |
187 | config BF_REV_0_1 | |
d07f4380 MF |
188 | bool "0.1" |
189 | depends on (BF52x || BF54x) | |
1394f032 BW |
190 | |
191 | config BF_REV_0_2 | |
192 | bool "0.2" | |
193 | depends on (BF537 || BF536 || BF534) | |
194 | ||
195 | config BF_REV_0_3 | |
196 | bool "0.3" | |
197 | depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) | |
198 | ||
199 | config BF_REV_0_4 | |
200 | bool "0.4" | |
201 | depends on (BF561 || BF533 || BF532 || BF531) | |
202 | ||
203 | config BF_REV_0_5 | |
204 | bool "0.5" | |
205 | depends on (BF561 || BF533 || BF532 || BF531) | |
206 | ||
de3025f4 JZ |
207 | config BF_REV_ANY |
208 | bool "any" | |
209 | ||
210 | config BF_REV_NONE | |
211 | bool "none" | |
212 | ||
1394f032 BW |
213 | endchoice |
214 | ||
59003145 MH |
215 | config BF52x |
216 | bool | |
1545a111 | 217 | depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527) |
59003145 MH |
218 | default y |
219 | ||
24a07a12 RH |
220 | config BF53x |
221 | bool | |
222 | depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) | |
223 | default y | |
224 | ||
225 | config BF54x | |
226 | bool | |
7c7fd170 | 227 | depends on (BF542 || BF544 || BF547 || BF548 || BF549) |
24a07a12 RH |
228 | default y |
229 | ||
1394f032 BW |
230 | config BFIN_DUAL_CORE |
231 | bool | |
232 | depends on (BF561) | |
233 | default y | |
234 | ||
235 | config BFIN_SINGLE_CORE | |
236 | bool | |
237 | depends on !BFIN_DUAL_CORE | |
238 | default y | |
239 | ||
1394f032 BW |
240 | config MEM_GENERIC_BOARD |
241 | bool | |
242 | depends on GENERIC_BOARD | |
243 | default y | |
244 | ||
245 | config MEM_MT48LC64M4A2FB_7E | |
246 | bool | |
247 | depends on (BFIN533_STAMP) | |
248 | default y | |
249 | ||
250 | config MEM_MT48LC16M16A2TG_75 | |
251 | bool | |
252 | depends on (BFIN533_EZKIT || BFIN561_EZKIT \ | |
ab472a04 JH |
253 | || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \ |
254 | || H8606_HVSISTEMAS) | |
1394f032 BW |
255 | default y |
256 | ||
257 | config MEM_MT48LC32M8A2_75 | |
258 | bool | |
259 | depends on (BFIN537_STAMP || PNAV10) | |
260 | default y | |
261 | ||
262 | config MEM_MT48LC8M32B2B5_7 | |
263 | bool | |
264 | depends on (BFIN561_BLUETECHNIX_CM) | |
265 | default y | |
266 | ||
59003145 MH |
267 | config MEM_MT48LC32M16A2TG_75 |
268 | bool | |
269 | depends on (BFIN527_EZKIT) | |
270 | default y | |
271 | ||
59003145 | 272 | source "arch/blackfin/mach-bf527/Kconfig" |
1394f032 BW |
273 | source "arch/blackfin/mach-bf533/Kconfig" |
274 | source "arch/blackfin/mach-bf561/Kconfig" | |
275 | source "arch/blackfin/mach-bf537/Kconfig" | |
24a07a12 | 276 | source "arch/blackfin/mach-bf548/Kconfig" |
1394f032 BW |
277 | |
278 | menu "Board customizations" | |
279 | ||
280 | config CMDLINE_BOOL | |
281 | bool "Default bootloader kernel arguments" | |
282 | ||
283 | config CMDLINE | |
284 | string "Initial kernel command string" | |
285 | depends on CMDLINE_BOOL | |
286 | default "console=ttyBF0,57600" | |
287 | help | |
288 | If you don't have a boot loader capable of passing a command line string | |
289 | to the kernel, you may specify one here. As a minimum, you should specify | |
290 | the memory size and the root device (e.g., mem=8M, root=/dev/nfs). | |
291 | ||
f16295e7 | 292 | comment "Clock/PLL Setup" |
1394f032 BW |
293 | |
294 | config CLKIN_HZ | |
295 | int "Crystal Frequency in Hz" | |
296 | default "11059200" if BFIN533_STAMP | |
297 | default "27000000" if BFIN533_EZKIT | |
ab472a04 | 298 | default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS) |
1394f032 BW |
299 | default "30000000" if BFIN561_EZKIT |
300 | default "24576000" if PNAV10 | |
301 | help | |
302 | The frequency of CLKIN crystal oscillator on the board in Hz. | |
303 | ||
f16295e7 RG |
304 | config BFIN_KERNEL_CLOCK |
305 | bool "Re-program Clocks while Kernel boots?" | |
306 | default n | |
307 | help | |
308 | This option decides if kernel clocks are re-programed from the | |
309 | bootloader settings. If the clocks are not set, the SDRAM settings | |
310 | are also not changed, and the Bootloader does 100% of the hardware | |
311 | configuration. | |
312 | ||
313 | config PLL_BYPASS | |
e4e9a7ad MF |
314 | bool "Bypass PLL" |
315 | depends on BFIN_KERNEL_CLOCK | |
316 | default n | |
f16295e7 RG |
317 | |
318 | config CLKIN_HALF | |
319 | bool "Half Clock In" | |
320 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
321 | default n | |
322 | help | |
323 | If this is set the clock will be divided by 2, before it goes to the PLL. | |
324 | ||
325 | config VCO_MULT | |
326 | int "VCO Multiplier" | |
327 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
328 | range 1 64 | |
329 | default "22" if BFIN533_EZKIT | |
330 | default "45" if BFIN533_STAMP | |
971d5bc4 | 331 | default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT) |
f16295e7 RG |
332 | default "22" if BFIN533_BLUETECHNIX_CM |
333 | default "20" if BFIN537_BLUETECHNIX_CM | |
334 | default "20" if BFIN561_BLUETECHNIX_CM | |
335 | default "20" if BFIN561_EZKIT | |
ab472a04 | 336 | default "16" if H8606_HVSISTEMAS |
f16295e7 RG |
337 | help |
338 | This controls the frequency of the on-chip PLL. This can be between 1 and 64. | |
339 | PLL Frequency = (Crystal Frequency) * (this setting) | |
340 | ||
341 | choice | |
342 | prompt "Core Clock Divider" | |
343 | depends on BFIN_KERNEL_CLOCK | |
344 | default CCLK_DIV_1 | |
345 | help | |
346 | This sets the frequency of the core. It can be 1, 2, 4 or 8 | |
347 | Core Frequency = (PLL frequency) / (this setting) | |
348 | ||
349 | config CCLK_DIV_1 | |
350 | bool "1" | |
351 | ||
352 | config CCLK_DIV_2 | |
353 | bool "2" | |
354 | ||
355 | config CCLK_DIV_4 | |
356 | bool "4" | |
357 | ||
358 | config CCLK_DIV_8 | |
359 | bool "8" | |
360 | endchoice | |
361 | ||
362 | config SCLK_DIV | |
363 | int "System Clock Divider" | |
364 | depends on BFIN_KERNEL_CLOCK | |
365 | range 1 15 | |
366 | default 5 if BFIN533_EZKIT | |
367 | default 5 if BFIN533_STAMP | |
971d5bc4 | 368 | default 4 if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT) |
f16295e7 RG |
369 | default 5 if BFIN533_BLUETECHNIX_CM |
370 | default 4 if BFIN537_BLUETECHNIX_CM | |
371 | default 4 if BFIN561_BLUETECHNIX_CM | |
372 | default 5 if BFIN561_EZKIT | |
ab472a04 | 373 | default 3 if H8606_HVSISTEMAS |
f16295e7 RG |
374 | help |
375 | This sets the frequency of the system clock (including SDRAM or DDR). | |
376 | This can be between 1 and 15 | |
377 | System Clock = (PLL frequency) / (this setting) | |
378 | ||
379 | # | |
380 | # Max & Min Speeds for various Chips | |
381 | # | |
382 | config MAX_VCO_HZ | |
383 | int | |
384 | default 600000000 if BF522 | |
1545a111 MF |
385 | default 400000000 if BF523 |
386 | default 400000000 if BF524 | |
f16295e7 | 387 | default 600000000 if BF525 |
1545a111 | 388 | default 400000000 if BF526 |
f16295e7 RG |
389 | default 600000000 if BF527 |
390 | default 400000000 if BF531 | |
391 | default 400000000 if BF532 | |
392 | default 750000000 if BF533 | |
393 | default 500000000 if BF534 | |
394 | default 400000000 if BF536 | |
395 | default 600000000 if BF537 | |
f72eecb9 RG |
396 | default 533333333 if BF538 |
397 | default 533333333 if BF539 | |
f16295e7 | 398 | default 600000000 if BF542 |
f72eecb9 | 399 | default 533333333 if BF544 |
1545a111 MF |
400 | default 600000000 if BF547 |
401 | default 600000000 if BF548 | |
f72eecb9 | 402 | default 533333333 if BF549 |
f16295e7 RG |
403 | default 600000000 if BF561 |
404 | ||
405 | config MIN_VCO_HZ | |
406 | int | |
407 | default 50000000 | |
408 | ||
409 | config MAX_SCLK_HZ | |
410 | int | |
f72eecb9 | 411 | default 133333333 |
f16295e7 RG |
412 | |
413 | config MIN_SCLK_HZ | |
414 | int | |
415 | default 27000000 | |
416 | ||
417 | comment "Kernel Timer/Scheduler" | |
418 | ||
419 | source kernel/Kconfig.hz | |
420 | ||
421 | comment "Memory Setup" | |
422 | ||
1394f032 BW |
423 | config MEM_SIZE |
424 | int "SDRAM Memory Size in MBytes" | |
425 | default 32 if BFIN533_EZKIT | |
59003145 | 426 | default 64 if BFIN527_EZKIT |
1394f032 | 427 | default 64 if BFIN537_STAMP |
971d5bc4 | 428 | default 64 if BFIN548_EZKIT |
1394f032 BW |
429 | default 64 if BFIN561_EZKIT |
430 | default 128 if BFIN533_STAMP | |
431 | default 64 if PNAV10 | |
ab472a04 | 432 | default 32 if H8606_HVSISTEMAS |
1394f032 BW |
433 | |
434 | config MEM_ADD_WIDTH | |
435 | int "SDRAM Memory Address Width" | |
971d5bc4 | 436 | depends on (!BF54x) |
1394f032 BW |
437 | default 9 if BFIN533_EZKIT |
438 | default 9 if BFIN561_EZKIT | |
ab472a04 | 439 | default 9 if H8606_HVSISTEMAS |
59003145 | 440 | default 10 if BFIN527_EZKIT |
1394f032 BW |
441 | default 10 if BFIN537_STAMP |
442 | default 11 if BFIN533_STAMP | |
443 | default 10 if PNAV10 | |
444 | ||
971d5bc4 SZ |
445 | |
446 | choice | |
447 | prompt "DDR SDRAM Chip Type" | |
448 | depends on BFIN548_EZKIT | |
449 | default MEM_MT46V32M16_5B | |
450 | ||
451 | config MEM_MT46V32M16_6T | |
452 | bool "MT46V32M16_6T" | |
453 | ||
454 | config MEM_MT46V32M16_5B | |
455 | bool "MT46V32M16_5B" | |
456 | endchoice | |
457 | ||
1394f032 BW |
458 | config ENET_FLASH_PIN |
459 | int "PF port/pin used for flash and ethernet sharing" | |
460 | depends on (BFIN533_STAMP) | |
461 | default 0 | |
462 | help | |
463 | PF port/pin used for flash and ethernet sharing to allow other PF | |
464 | pins to be used on other platforms without having to touch common | |
465 | code. | |
466 | For example: PF0 --> 0,PF1 --> 1,PF2 --> 2, etc. | |
467 | ||
468 | config BOOT_LOAD | |
469 | hex "Kernel load address for booting" | |
470 | default "0x1000" | |
2d8f161f | 471 | range 0x1000 0x20000000 |
1394f032 BW |
472 | help |
473 | This option allows you to set the load address of the kernel. | |
474 | This can be useful if you are on a board which has a small amount | |
475 | of memory or you wish to reserve some memory at the beginning of | |
476 | the address space. | |
477 | ||
2d8f161f MF |
478 | Note that you need to keep this value above 4k (0x1000) as this |
479 | memory region is used to capture NULL pointer references as well | |
480 | as some core kernel functions. | |
1394f032 | 481 | |
f0b5d12f MF |
482 | choice |
483 | prompt "Blackfin Exception Scratch Register" | |
484 | default BFIN_SCRATCH_REG_RETN | |
485 | help | |
486 | Select the resource to reserve for the Exception handler: | |
487 | - RETN: Non-Maskable Interrupt (NMI) | |
488 | - RETE: Exception Return (JTAG/ICE) | |
489 | - CYCLES: Performance counter | |
490 | ||
491 | If you are unsure, please select "RETN". | |
492 | ||
493 | config BFIN_SCRATCH_REG_RETN | |
494 | bool "RETN" | |
495 | help | |
496 | Use the RETN register in the Blackfin exception handler | |
497 | as a stack scratch register. This means you cannot | |
498 | safely use NMI on the Blackfin while running Linux, but | |
499 | you can debug the system with a JTAG ICE and use the | |
500 | CYCLES performance registers. | |
501 | ||
502 | If you are unsure, please select "RETN". | |
503 | ||
504 | config BFIN_SCRATCH_REG_RETE | |
505 | bool "RETE" | |
506 | help | |
507 | Use the RETE register in the Blackfin exception handler | |
508 | as a stack scratch register. This means you cannot | |
509 | safely use a JTAG ICE while debugging a Blackfin board, | |
510 | but you can safely use the CYCLES performance registers | |
511 | and the NMI. | |
512 | ||
513 | If you are unsure, please select "RETN". | |
514 | ||
515 | config BFIN_SCRATCH_REG_CYCLES | |
516 | bool "CYCLES" | |
517 | help | |
518 | Use the CYCLES register in the Blackfin exception handler | |
519 | as a stack scratch register. This means you cannot | |
520 | safely use the CYCLES performance registers on a Blackfin | |
521 | board at anytime, but you can debug the system with a JTAG | |
522 | ICE and use the NMI. | |
523 | ||
524 | If you are unsure, please select "RETN". | |
525 | ||
526 | endchoice | |
527 | ||
1394f032 BW |
528 | endmenu |
529 | ||
530 | ||
531 | menu "Blackfin Kernel Optimizations" | |
532 | ||
1394f032 BW |
533 | comment "Memory Optimizations" |
534 | ||
535 | config I_ENTRY_L1 | |
536 | bool "Locate interrupt entry code in L1 Memory" | |
537 | default y | |
538 | help | |
01dd2fbf ML |
539 | If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked |
540 | into L1 instruction memory. (less latency) | |
1394f032 BW |
541 | |
542 | config EXCPT_IRQ_SYSC_L1 | |
01dd2fbf | 543 | bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" |
1394f032 BW |
544 | default y |
545 | help | |
01dd2fbf ML |
546 | If enabled, the entire ASM lowlevel exception and interrupt entry code |
547 | (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. | |
548 | (less latency) | |
1394f032 BW |
549 | |
550 | config DO_IRQ_L1 | |
551 | bool "Locate frequently called do_irq dispatcher function in L1 Memory" | |
552 | default y | |
553 | help | |
01dd2fbf ML |
554 | If enabled, the frequently called do_irq dispatcher function is linked |
555 | into L1 instruction memory. (less latency) | |
1394f032 BW |
556 | |
557 | config CORE_TIMER_IRQ_L1 | |
558 | bool "Locate frequently called timer_interrupt() function in L1 Memory" | |
559 | default y | |
560 | help | |
01dd2fbf ML |
561 | If enabled, the frequently called timer_interrupt() function is linked |
562 | into L1 instruction memory. (less latency) | |
1394f032 BW |
563 | |
564 | config IDLE_L1 | |
565 | bool "Locate frequently idle function in L1 Memory" | |
566 | default y | |
567 | help | |
01dd2fbf ML |
568 | If enabled, the frequently called idle function is linked |
569 | into L1 instruction memory. (less latency) | |
1394f032 BW |
570 | |
571 | config SCHEDULE_L1 | |
572 | bool "Locate kernel schedule function in L1 Memory" | |
573 | default y | |
574 | help | |
01dd2fbf ML |
575 | If enabled, the frequently called kernel schedule is linked |
576 | into L1 instruction memory. (less latency) | |
1394f032 BW |
577 | |
578 | config ARITHMETIC_OPS_L1 | |
579 | bool "Locate kernel owned arithmetic functions in L1 Memory" | |
580 | default y | |
581 | help | |
01dd2fbf ML |
582 | If enabled, arithmetic functions are linked |
583 | into L1 instruction memory. (less latency) | |
1394f032 BW |
584 | |
585 | config ACCESS_OK_L1 | |
586 | bool "Locate access_ok function in L1 Memory" | |
587 | default y | |
588 | help | |
01dd2fbf ML |
589 | If enabled, the access_ok function is linked |
590 | into L1 instruction memory. (less latency) | |
1394f032 BW |
591 | |
592 | config MEMSET_L1 | |
593 | bool "Locate memset function in L1 Memory" | |
594 | default y | |
595 | help | |
01dd2fbf ML |
596 | If enabled, the memset function is linked |
597 | into L1 instruction memory. (less latency) | |
1394f032 BW |
598 | |
599 | config MEMCPY_L1 | |
600 | bool "Locate memcpy function in L1 Memory" | |
601 | default y | |
602 | help | |
01dd2fbf ML |
603 | If enabled, the memcpy function is linked |
604 | into L1 instruction memory. (less latency) | |
1394f032 BW |
605 | |
606 | config SYS_BFIN_SPINLOCK_L1 | |
607 | bool "Locate sys_bfin_spinlock function in L1 Memory" | |
608 | default y | |
609 | help | |
01dd2fbf ML |
610 | If enabled, sys_bfin_spinlock function is linked |
611 | into L1 instruction memory. (less latency) | |
1394f032 BW |
612 | |
613 | config IP_CHECKSUM_L1 | |
614 | bool "Locate IP Checksum function in L1 Memory" | |
615 | default n | |
616 | help | |
01dd2fbf ML |
617 | If enabled, the IP Checksum function is linked |
618 | into L1 instruction memory. (less latency) | |
1394f032 BW |
619 | |
620 | config CACHELINE_ALIGNED_L1 | |
621 | bool "Locate cacheline_aligned data to L1 Data Memory" | |
157cc5aa MH |
622 | default y if !BF54x |
623 | default n if BF54x | |
1394f032 BW |
624 | depends on !BF531 |
625 | help | |
01dd2fbf ML |
626 | If enabled, cacheline_anligned data is linked |
627 | into L1 data memory. (less latency) | |
1394f032 BW |
628 | |
629 | config SYSCALL_TAB_L1 | |
630 | bool "Locate Syscall Table L1 Data Memory" | |
631 | default n | |
632 | depends on !BF531 | |
633 | help | |
01dd2fbf ML |
634 | If enabled, the Syscall LUT is linked |
635 | into L1 data memory. (less latency) | |
1394f032 BW |
636 | |
637 | config CPLB_SWITCH_TAB_L1 | |
638 | bool "Locate CPLB Switch Tables L1 Data Memory" | |
639 | default n | |
640 | depends on !BF531 | |
641 | help | |
01dd2fbf ML |
642 | If enabled, the CPLB Switch Tables are linked |
643 | into L1 data memory. (less latency) | |
1394f032 BW |
644 | |
645 | endmenu | |
646 | ||
647 | ||
648 | choice | |
649 | prompt "Kernel executes from" | |
650 | help | |
651 | Choose the memory type that the kernel will be running in. | |
652 | ||
653 | config RAMKERNEL | |
654 | bool "RAM" | |
655 | help | |
656 | The kernel will be resident in RAM when running. | |
657 | ||
658 | config ROMKERNEL | |
659 | bool "ROM" | |
660 | help | |
661 | The kernel will be resident in FLASH/ROM when running. | |
662 | ||
663 | endchoice | |
664 | ||
665 | source "mm/Kconfig" | |
666 | ||
db0fa206 BW |
667 | config LARGE_ALLOCS |
668 | bool "Allow allocating large blocks (> 1MB) of memory" | |
669 | help | |
670 | Allow the slab memory allocator to keep chains for very large | |
671 | memory sizes - upto 32MB. You may need this if your system has | |
672 | a lot of RAM, and you need to able to allocate very large | |
673 | contiguous chunks. If unsure, say N. | |
674 | ||
780431e3 MF |
675 | config BFIN_GPTIMERS |
676 | tristate "Enable Blackfin General Purpose Timers API" | |
677 | default n | |
678 | help | |
679 | Enable support for the General Purpose Timers API. If you | |
680 | are unsure, say N. | |
681 | ||
682 | To compile this driver as a module, choose M here: the module | |
683 | will be called gptimers.ko. | |
684 | ||
1394f032 BW |
685 | config BFIN_DMA_5XX |
686 | bool "Enable DMA Support" | |
59003145 | 687 | depends on (BF52x || BF53x || BF561 || BF54x) |
1394f032 BW |
688 | default y |
689 | help | |
690 | DMA driver for BF5xx. | |
691 | ||
692 | choice | |
693 | prompt "Uncached SDRAM region" | |
694 | default DMA_UNCACHED_1M | |
247537b9 | 695 | depends on BFIN_DMA_5XX |
1394f032 BW |
696 | config DMA_UNCACHED_2M |
697 | bool "Enable 2M DMA region" | |
698 | config DMA_UNCACHED_1M | |
699 | bool "Enable 1M DMA region" | |
700 | config DMA_UNCACHED_NONE | |
701 | bool "Disable DMA region" | |
702 | endchoice | |
703 | ||
704 | ||
705 | comment "Cache Support" | |
3bebca2d | 706 | config BFIN_ICACHE |
1394f032 | 707 | bool "Enable ICACHE" |
3bebca2d | 708 | config BFIN_DCACHE |
1394f032 | 709 | bool "Enable DCACHE" |
3bebca2d | 710 | config BFIN_DCACHE_BANKA |
1394f032 | 711 | bool "Enable only 16k BankA DCACHE - BankB is SRAM" |
3bebca2d | 712 | depends on BFIN_DCACHE && !BF531 |
1394f032 | 713 | default n |
3bebca2d RG |
714 | config BFIN_ICACHE_LOCK |
715 | bool "Enable Instruction Cache Locking" | |
1394f032 BW |
716 | |
717 | choice | |
718 | prompt "Policy" | |
3bebca2d RG |
719 | depends on BFIN_DCACHE |
720 | default BFIN_WB | |
721 | config BFIN_WB | |
1394f032 BW |
722 | bool "Write back" |
723 | help | |
724 | Write Back Policy: | |
725 | Cached data will be written back to SDRAM only when needed. | |
726 | This can give a nice increase in performance, but beware of | |
727 | broken drivers that do not properly invalidate/flush their | |
728 | cache. | |
729 | ||
730 | Write Through Policy: | |
731 | Cached data will always be written back to SDRAM when the | |
732 | cache is updated. This is a completely safe setting, but | |
733 | performance is worse than Write Back. | |
734 | ||
735 | If you are unsure of the options and you want to be safe, | |
736 | then go with Write Through. | |
737 | ||
3bebca2d | 738 | config BFIN_WT |
1394f032 BW |
739 | bool "Write through" |
740 | help | |
741 | Write Back Policy: | |
742 | Cached data will be written back to SDRAM only when needed. | |
743 | This can give a nice increase in performance, but beware of | |
744 | broken drivers that do not properly invalidate/flush their | |
745 | cache. | |
746 | ||
747 | Write Through Policy: | |
748 | Cached data will always be written back to SDRAM when the | |
749 | cache is updated. This is a completely safe setting, but | |
750 | performance is worse than Write Back. | |
751 | ||
752 | If you are unsure of the options and you want to be safe, | |
753 | then go with Write Through. | |
754 | ||
755 | endchoice | |
756 | ||
757 | config L1_MAX_PIECE | |
758 | int "Set the max L1 SRAM pieces" | |
759 | default 16 | |
760 | help | |
761 | Set the max memory pieces for the L1 SRAM allocation algorithm. | |
762 | Min value is 16. Max value is 1024. | |
763 | ||
b97b8a99 BS |
764 | |
765 | config MPU | |
766 | bool "Enable the memory protection unit (EXPERIMENTAL)" | |
767 | default n | |
768 | help | |
769 | Use the processor's MPU to protect applications from accessing | |
770 | memory they do not own. This comes at a performance penalty | |
771 | and is recommended only for debugging. | |
772 | ||
1394f032 BW |
773 | comment "Asynchonous Memory Configuration" |
774 | ||
ddf416b2 | 775 | menu "EBIU_AMGCTL Global Control" |
1394f032 BW |
776 | config C_AMCKEN |
777 | bool "Enable CLKOUT" | |
778 | default y | |
779 | ||
780 | config C_CDPRIO | |
781 | bool "DMA has priority over core for ext. accesses" | |
782 | default n | |
783 | ||
784 | config C_B0PEN | |
785 | depends on BF561 | |
786 | bool "Bank 0 16 bit packing enable" | |
787 | default y | |
788 | ||
789 | config C_B1PEN | |
790 | depends on BF561 | |
791 | bool "Bank 1 16 bit packing enable" | |
792 | default y | |
793 | ||
794 | config C_B2PEN | |
795 | depends on BF561 | |
796 | bool "Bank 2 16 bit packing enable" | |
797 | default y | |
798 | ||
799 | config C_B3PEN | |
800 | depends on BF561 | |
801 | bool "Bank 3 16 bit packing enable" | |
802 | default n | |
803 | ||
804 | choice | |
805 | prompt"Enable Asynchonous Memory Banks" | |
806 | default C_AMBEN_ALL | |
807 | ||
808 | config C_AMBEN | |
809 | bool "Disable All Banks" | |
810 | ||
811 | config C_AMBEN_B0 | |
812 | bool "Enable Bank 0" | |
813 | ||
814 | config C_AMBEN_B0_B1 | |
815 | bool "Enable Bank 0 & 1" | |
816 | ||
817 | config C_AMBEN_B0_B1_B2 | |
818 | bool "Enable Bank 0 & 1 & 2" | |
819 | ||
820 | config C_AMBEN_ALL | |
821 | bool "Enable All Banks" | |
822 | endchoice | |
823 | endmenu | |
824 | ||
825 | menu "EBIU_AMBCTL Control" | |
826 | config BANK_0 | |
827 | hex "Bank 0" | |
828 | default 0x7BB0 | |
829 | ||
830 | config BANK_1 | |
831 | hex "Bank 1" | |
832 | default 0x7BB0 | |
833 | ||
834 | config BANK_2 | |
835 | hex "Bank 2" | |
836 | default 0x7BB0 | |
837 | ||
838 | config BANK_3 | |
839 | hex "Bank 3" | |
840 | default 0x99B3 | |
841 | endmenu | |
842 | ||
e40540b3 SZ |
843 | config EBIU_MBSCTLVAL |
844 | hex "EBIU Bank Select Control Register" | |
845 | depends on BF54x | |
846 | default 0 | |
847 | ||
848 | config EBIU_MODEVAL | |
849 | hex "Flash Memory Mode Control Register" | |
850 | depends on BF54x | |
851 | default 1 | |
852 | ||
853 | config EBIU_FCTLVAL | |
854 | hex "Flash Memory Bank Control Register" | |
855 | depends on BF54x | |
856 | default 6 | |
1394f032 BW |
857 | endmenu |
858 | ||
859 | ############################################################################# | |
860 | menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" | |
861 | ||
862 | config PCI | |
863 | bool "PCI support" | |
864 | help | |
865 | Support for PCI bus. | |
866 | ||
867 | source "drivers/pci/Kconfig" | |
868 | ||
869 | config HOTPLUG | |
870 | bool "Support for hot-pluggable device" | |
871 | help | |
872 | Say Y here if you want to plug devices into your computer while | |
873 | the system is running, and be able to use them quickly. In many | |
874 | cases, the devices can likewise be unplugged at any time too. | |
875 | ||
876 | One well known example of this is PCMCIA- or PC-cards, credit-card | |
877 | size devices such as network cards, modems or hard drives which are | |
878 | plugged into slots found on all modern laptop computers. Another | |
879 | example, used on modern desktops as well as laptops, is USB. | |
880 | ||
881 | Enable HOTPLUG and KMOD, and build a modular kernel. Get agent | |
882 | software (at <http://linux-hotplug.sourceforge.net/>) and install it. | |
883 | Then your kernel will automatically call out to a user mode "policy | |
884 | agent" (/sbin/hotplug) to load modules and set up software needed | |
885 | to use devices as you hotplug them. | |
886 | ||
887 | source "drivers/pcmcia/Kconfig" | |
888 | ||
889 | source "drivers/pci/hotplug/Kconfig" | |
890 | ||
891 | endmenu | |
892 | ||
893 | menu "Executable file formats" | |
894 | ||
895 | source "fs/Kconfig.binfmt" | |
896 | ||
897 | endmenu | |
898 | ||
899 | menu "Power management options" | |
900 | source "kernel/power/Kconfig" | |
901 | ||
f4cb5700 JB |
902 | config ARCH_SUSPEND_POSSIBLE |
903 | def_bool y | |
904 | depends on !SMP | |
905 | ||
1394f032 BW |
906 | choice |
907 | prompt "Select PM Wakeup Event Source" | |
908 | default PM_WAKEUP_GPIO_BY_SIC_IWR | |
909 | depends on PM | |
910 | help | |
911 | If you have a GPIO already configured as input with the corresponding PORTx_MASK | |
912 | bit set - "Specify Wakeup Event by SIC_IWR value" | |
913 | ||
914 | config PM_WAKEUP_GPIO_BY_SIC_IWR | |
915 | bool "Specify Wakeup Event by SIC_IWR value" | |
916 | config PM_WAKEUP_BY_GPIO | |
917 | bool "Cause Wakeup Event by GPIO" | |
918 | config PM_WAKEUP_GPIO_API | |
919 | bool "Configure Wakeup Event by PM GPIO API" | |
920 | ||
921 | endchoice | |
922 | ||
923 | config PM_WAKEUP_SIC_IWR | |
924 | hex "Wakeup Events (SIC_IWR)" | |
925 | depends on PM_WAKEUP_GPIO_BY_SIC_IWR | |
03c57328 SZ |
926 | default 0x8 if (BF537 || BF536 || BF534) |
927 | default 0x80 if (BF533 || BF532 || BF531) | |
928 | default 0x80 if (BF54x) | |
929 | default 0x80 if (BF52x) | |
1394f032 BW |
930 | |
931 | config PM_WAKEUP_GPIO_NUMBER | |
932 | int "Wakeup GPIO number" | |
933 | range 0 47 | |
934 | depends on PM_WAKEUP_BY_GPIO | |
935 | default 2 if BFIN537_STAMP | |
936 | ||
937 | choice | |
938 | prompt "GPIO Polarity" | |
939 | depends on PM_WAKEUP_BY_GPIO | |
940 | default PM_WAKEUP_GPIO_POLAR_H | |
941 | config PM_WAKEUP_GPIO_POLAR_H | |
942 | bool "Active High" | |
943 | config PM_WAKEUP_GPIO_POLAR_L | |
944 | bool "Active Low" | |
945 | config PM_WAKEUP_GPIO_POLAR_EDGE_F | |
946 | bool "Falling EDGE" | |
947 | config PM_WAKEUP_GPIO_POLAR_EDGE_R | |
948 | bool "Rising EDGE" | |
949 | config PM_WAKEUP_GPIO_POLAR_EDGE_B | |
950 | bool "Both EDGE" | |
951 | endchoice | |
952 | ||
953 | endmenu | |
954 | ||
24a07a12 | 955 | if (BF537 || BF533 || BF54x) |
1394f032 BW |
956 | |
957 | menu "CPU Frequency scaling" | |
958 | ||
959 | source "drivers/cpufreq/Kconfig" | |
960 | ||
961 | config CPU_FREQ | |
962 | bool | |
963 | default n | |
964 | help | |
965 | If you want to enable this option, you should select the | |
966 | DPMC driver from Character Devices. | |
967 | endmenu | |
968 | ||
969 | endif | |
970 | ||
971 | source "net/Kconfig" | |
972 | ||
973 | source "drivers/Kconfig" | |
974 | ||
975 | source "fs/Kconfig" | |
976 | ||
74ce8322 | 977 | source "arch/blackfin/Kconfig.debug" |
1394f032 BW |
978 | |
979 | source "security/Kconfig" | |
980 | ||
981 | source "crypto/Kconfig" | |
982 | ||
983 | source "lib/Kconfig" |