Commit | Line | Data |
---|---|---|
9e1b9b80 AJ |
1 | config SYMBOL_PREFIX |
2 | string | |
3 | default "_" | |
4 | ||
1394f032 | 5 | config MMU |
bac7d89e | 6 | def_bool n |
1394f032 BW |
7 | |
8 | config FPU | |
bac7d89e | 9 | def_bool n |
1394f032 BW |
10 | |
11 | config RWSEM_GENERIC_SPINLOCK | |
bac7d89e | 12 | def_bool y |
1394f032 BW |
13 | |
14 | config RWSEM_XCHGADD_ALGORITHM | |
bac7d89e | 15 | def_bool n |
1394f032 BW |
16 | |
17 | config BLACKFIN | |
bac7d89e | 18 | def_bool y |
652afdc3 | 19 | select HAVE_ARCH_KGDB |
e8f263df | 20 | select HAVE_ARCH_TRACEHOOK |
f5074429 MF |
21 | select HAVE_DYNAMIC_FTRACE |
22 | select HAVE_FTRACE_MCOUNT_RECORD | |
1ee76d7e | 23 | select HAVE_FUNCTION_GRAPH_TRACER |
1c873be7 | 24 | select HAVE_FUNCTION_TRACER |
aebfef03 | 25 | select HAVE_FUNCTION_TRACE_MCOUNT_TEST |
ec7748b5 | 26 | select HAVE_IDE |
7db79172 | 27 | select HAVE_IRQ_WORK |
d86bfb16 BS |
28 | select HAVE_KERNEL_GZIP if RAMKERNEL |
29 | select HAVE_KERNEL_BZIP2 if RAMKERNEL | |
30 | select HAVE_KERNEL_LZMA if RAMKERNEL | |
67df6cc6 | 31 | select HAVE_KERNEL_LZO if RAMKERNEL |
42d4b839 | 32 | select HAVE_OPROFILE |
7db79172 | 33 | select HAVE_PERF_EVENTS |
7563bbf8 | 34 | select ARCH_HAVE_CUSTOM_GPIO_H |
a4f0b32c | 35 | select ARCH_WANT_OPTIONAL_GPIOLIB |
7b028863 | 36 | select HAVE_GENERIC_HARDIRQS |
bee18beb | 37 | select GENERIC_ATOMIC64 |
7b028863 TG |
38 | select GENERIC_IRQ_PROBE |
39 | select IRQ_PER_CPU if SMP | |
d314d74c | 40 | select HAVE_NMI_WATCHDOG if NMI_WATCHDOG |
6bba2682 | 41 | select GENERIC_SMP_IDLE_THREAD |
dfbaec06 | 42 | select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS |
1394f032 | 43 | |
ddf9ddac MF |
44 | config GENERIC_CSUM |
45 | def_bool y | |
46 | ||
70f12567 MF |
47 | config GENERIC_BUG |
48 | def_bool y | |
49 | depends on BUG | |
50 | ||
e3defffe | 51 | config ZONE_DMA |
bac7d89e | 52 | def_bool y |
e3defffe | 53 | |
b2d1583f | 54 | config GENERIC_GPIO |
bac7d89e | 55 | def_bool y |
1394f032 BW |
56 | |
57 | config FORCE_MAX_ZONEORDER | |
58 | int | |
59 | default "14" | |
60 | ||
61 | config GENERIC_CALIBRATE_DELAY | |
bac7d89e | 62 | def_bool y |
1394f032 | 63 | |
6fa68e7a MF |
64 | config LOCKDEP_SUPPORT |
65 | def_bool y | |
66 | ||
c7b412f4 MF |
67 | config STACKTRACE_SUPPORT |
68 | def_bool y | |
69 | ||
8f86001f MF |
70 | config TRACE_IRQFLAGS_SUPPORT |
71 | def_bool y | |
1394f032 | 72 | |
1394f032 | 73 | source "init/Kconfig" |
dc52ddc0 | 74 | |
1394f032 BW |
75 | source "kernel/Kconfig.preempt" |
76 | ||
dc52ddc0 MH |
77 | source "kernel/Kconfig.freezer" |
78 | ||
1394f032 BW |
79 | menu "Blackfin Processor Options" |
80 | ||
81 | comment "Processor and Board Settings" | |
82 | ||
83 | choice | |
84 | prompt "CPU" | |
85 | default BF533 | |
86 | ||
2f6f4bcd BW |
87 | config BF512 |
88 | bool "BF512" | |
89 | help | |
90 | BF512 Processor Support. | |
91 | ||
92 | config BF514 | |
93 | bool "BF514" | |
94 | help | |
95 | BF514 Processor Support. | |
96 | ||
97 | config BF516 | |
98 | bool "BF516" | |
99 | help | |
100 | BF516 Processor Support. | |
101 | ||
102 | config BF518 | |
103 | bool "BF518" | |
104 | help | |
105 | BF518 Processor Support. | |
106 | ||
59003145 MH |
107 | config BF522 |
108 | bool "BF522" | |
109 | help | |
110 | BF522 Processor Support. | |
111 | ||
1545a111 MF |
112 | config BF523 |
113 | bool "BF523" | |
114 | help | |
115 | BF523 Processor Support. | |
116 | ||
117 | config BF524 | |
118 | bool "BF524" | |
119 | help | |
120 | BF524 Processor Support. | |
121 | ||
59003145 MH |
122 | config BF525 |
123 | bool "BF525" | |
124 | help | |
125 | BF525 Processor Support. | |
126 | ||
1545a111 MF |
127 | config BF526 |
128 | bool "BF526" | |
129 | help | |
130 | BF526 Processor Support. | |
131 | ||
59003145 MH |
132 | config BF527 |
133 | bool "BF527" | |
134 | help | |
135 | BF527 Processor Support. | |
136 | ||
1394f032 BW |
137 | config BF531 |
138 | bool "BF531" | |
139 | help | |
140 | BF531 Processor Support. | |
141 | ||
142 | config BF532 | |
143 | bool "BF532" | |
144 | help | |
145 | BF532 Processor Support. | |
146 | ||
147 | config BF533 | |
148 | bool "BF533" | |
149 | help | |
150 | BF533 Processor Support. | |
151 | ||
152 | config BF534 | |
153 | bool "BF534" | |
154 | help | |
155 | BF534 Processor Support. | |
156 | ||
157 | config BF536 | |
158 | bool "BF536" | |
159 | help | |
160 | BF536 Processor Support. | |
161 | ||
162 | config BF537 | |
163 | bool "BF537" | |
164 | help | |
165 | BF537 Processor Support. | |
166 | ||
dc26aec2 MH |
167 | config BF538 |
168 | bool "BF538" | |
169 | help | |
170 | BF538 Processor Support. | |
171 | ||
172 | config BF539 | |
173 | bool "BF539" | |
174 | help | |
175 | BF539 Processor Support. | |
176 | ||
5df326ac | 177 | config BF542_std |
24a07a12 RH |
178 | bool "BF542" |
179 | help | |
180 | BF542 Processor Support. | |
181 | ||
2f89c063 MF |
182 | config BF542M |
183 | bool "BF542m" | |
184 | help | |
185 | BF542 Processor Support. | |
186 | ||
5df326ac | 187 | config BF544_std |
24a07a12 RH |
188 | bool "BF544" |
189 | help | |
190 | BF544 Processor Support. | |
191 | ||
2f89c063 MF |
192 | config BF544M |
193 | bool "BF544m" | |
194 | help | |
195 | BF544 Processor Support. | |
196 | ||
5df326ac | 197 | config BF547_std |
7c7fd170 MF |
198 | bool "BF547" |
199 | help | |
200 | BF547 Processor Support. | |
201 | ||
2f89c063 MF |
202 | config BF547M |
203 | bool "BF547m" | |
204 | help | |
205 | BF547 Processor Support. | |
206 | ||
5df326ac | 207 | config BF548_std |
24a07a12 RH |
208 | bool "BF548" |
209 | help | |
210 | BF548 Processor Support. | |
211 | ||
2f89c063 MF |
212 | config BF548M |
213 | bool "BF548m" | |
214 | help | |
215 | BF548 Processor Support. | |
216 | ||
5df326ac | 217 | config BF549_std |
24a07a12 RH |
218 | bool "BF549" |
219 | help | |
220 | BF549 Processor Support. | |
221 | ||
2f89c063 MF |
222 | config BF549M |
223 | bool "BF549m" | |
224 | help | |
225 | BF549 Processor Support. | |
226 | ||
1394f032 BW |
227 | config BF561 |
228 | bool "BF561" | |
229 | help | |
cd88b4dc | 230 | BF561 Processor Support. |
1394f032 | 231 | |
b5affb01 BL |
232 | config BF609 |
233 | bool "BF609" | |
234 | select CLKDEV_LOOKUP | |
235 | help | |
236 | BF609 Processor Support. | |
237 | ||
1394f032 BW |
238 | endchoice |
239 | ||
46fa5eec GY |
240 | config SMP |
241 | depends on BF561 | |
0d152c27 | 242 | select TICKSOURCE_CORETMR |
46fa5eec GY |
243 | bool "Symmetric multi-processing support" |
244 | ---help--- | |
245 | This enables support for systems with more than one CPU, | |
246 | like the dual core BF561. If you have a system with only one | |
247 | CPU, say N. If you have a system with more than one CPU, say Y. | |
248 | ||
249 | If you don't know what to do here, say N. | |
250 | ||
251 | config NR_CPUS | |
252 | int | |
253 | depends on SMP | |
254 | default 2 if BF561 | |
255 | ||
0b39db28 GY |
256 | config HOTPLUG_CPU |
257 | bool "Support for hot-pluggable CPUs" | |
258 | depends on SMP && HOTPLUG | |
259 | default y | |
260 | ||
0c0497c2 MF |
261 | config BF_REV_MIN |
262 | int | |
b5affb01 | 263 | default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x |
0c0497c2 | 264 | default 2 if (BF537 || BF536 || BF534) |
2f89c063 | 265 | default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM) |
2f6f4bcd | 266 | default 4 if (BF538 || BF539) |
0c0497c2 MF |
267 | |
268 | config BF_REV_MAX | |
269 | int | |
b5affb01 | 270 | default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x |
2f89c063 | 271 | default 3 if (BF537 || BF536 || BF534 || BF54xM) |
2f6f4bcd | 272 | default 5 if (BF561 || BF538 || BF539) |
0c0497c2 MF |
273 | default 6 if (BF533 || BF532 || BF531) |
274 | ||
1394f032 BW |
275 | choice |
276 | prompt "Silicon Rev" | |
b5affb01 | 277 | default BF_REV_0_0 if (BF51x || BF52x || BF60x) |
f8b55651 | 278 | default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM)) |
2f89c063 | 279 | default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561) |
24a07a12 RH |
280 | |
281 | config BF_REV_0_0 | |
282 | bool "0.0" | |
b5affb01 | 283 | depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x) |
59003145 MH |
284 | |
285 | config BF_REV_0_1 | |
d07f4380 | 286 | bool "0.1" |
3d15f302 | 287 | depends on (BF51x || BF52x || (BF54x && !BF54xM)) |
1394f032 BW |
288 | |
289 | config BF_REV_0_2 | |
290 | bool "0.2" | |
8060bb6f | 291 | depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM)) |
1394f032 BW |
292 | |
293 | config BF_REV_0_3 | |
294 | bool "0.3" | |
2f89c063 | 295 | depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) |
1394f032 BW |
296 | |
297 | config BF_REV_0_4 | |
298 | bool "0.4" | |
dc26aec2 | 299 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
1394f032 BW |
300 | |
301 | config BF_REV_0_5 | |
302 | bool "0.5" | |
dc26aec2 | 303 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
1394f032 | 304 | |
49f7253c MF |
305 | config BF_REV_0_6 |
306 | bool "0.6" | |
307 | depends on (BF533 || BF532 || BF531) | |
308 | ||
de3025f4 JZ |
309 | config BF_REV_ANY |
310 | bool "any" | |
311 | ||
312 | config BF_REV_NONE | |
313 | bool "none" | |
314 | ||
1394f032 BW |
315 | endchoice |
316 | ||
24a07a12 RH |
317 | config BF53x |
318 | bool | |
319 | depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) | |
320 | default y | |
321 | ||
1394f032 BW |
322 | config MEM_MT48LC64M4A2FB_7E |
323 | bool | |
324 | depends on (BFIN533_STAMP) | |
325 | default y | |
326 | ||
327 | config MEM_MT48LC16M16A2TG_75 | |
328 | bool | |
329 | depends on (BFIN533_EZKIT || BFIN561_EZKIT \ | |
60584344 HK |
330 | || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \ |
331 | || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \ | |
332 | || BFIN527_BLUETECHNIX_CM) | |
1394f032 BW |
333 | default y |
334 | ||
335 | config MEM_MT48LC32M8A2_75 | |
336 | bool | |
084f9ebf | 337 | depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT) |
1394f032 BW |
338 | default y |
339 | ||
340 | config MEM_MT48LC8M32B2B5_7 | |
341 | bool | |
342 | depends on (BFIN561_BLUETECHNIX_CM) | |
343 | default y | |
344 | ||
59003145 MH |
345 | config MEM_MT48LC32M16A2TG_75 |
346 | bool | |
8effc4a6 | 347 | depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL) |
59003145 MH |
348 | default y |
349 | ||
ee48efb5 GY |
350 | config MEM_MT48H32M16LFCJ_75 |
351 | bool | |
352 | depends on (BFIN526_EZBRD) | |
353 | default y | |
354 | ||
f82f16d2 BL |
355 | config MEM_MT47H64M16 |
356 | bool | |
357 | depends on (BFIN609_EZKIT) | |
358 | default y | |
359 | ||
2f6f4bcd | 360 | source "arch/blackfin/mach-bf518/Kconfig" |
59003145 | 361 | source "arch/blackfin/mach-bf527/Kconfig" |
1394f032 BW |
362 | source "arch/blackfin/mach-bf533/Kconfig" |
363 | source "arch/blackfin/mach-bf561/Kconfig" | |
364 | source "arch/blackfin/mach-bf537/Kconfig" | |
dc26aec2 | 365 | source "arch/blackfin/mach-bf538/Kconfig" |
24a07a12 | 366 | source "arch/blackfin/mach-bf548/Kconfig" |
b5affb01 | 367 | source "arch/blackfin/mach-bf609/Kconfig" |
1394f032 BW |
368 | |
369 | menu "Board customizations" | |
370 | ||
371 | config CMDLINE_BOOL | |
372 | bool "Default bootloader kernel arguments" | |
373 | ||
374 | config CMDLINE | |
375 | string "Initial kernel command string" | |
376 | depends on CMDLINE_BOOL | |
377 | default "console=ttyBF0,57600" | |
378 | help | |
379 | If you don't have a boot loader capable of passing a command line string | |
380 | to the kernel, you may specify one here. As a minimum, you should specify | |
381 | the memory size and the root device (e.g., mem=8M, root=/dev/nfs). | |
382 | ||
5f004c20 MF |
383 | config BOOT_LOAD |
384 | hex "Kernel load address for booting" | |
385 | default "0x1000" | |
386 | range 0x1000 0x20000000 | |
387 | help | |
388 | This option allows you to set the load address of the kernel. | |
389 | This can be useful if you are on a board which has a small amount | |
390 | of memory or you wish to reserve some memory at the beginning of | |
391 | the address space. | |
392 | ||
393 | Note that you need to keep this value above 4k (0x1000) as this | |
394 | memory region is used to capture NULL pointer references as well | |
395 | as some core kernel functions. | |
396 | ||
b5affb01 BL |
397 | config PHY_RAM_BASE_ADDRESS |
398 | hex "Physical RAM Base" | |
399 | default 0x0 | |
400 | help | |
401 | set BF609 FPGA physical SRAM base address | |
402 | ||
8cc7117e MH |
403 | config ROM_BASE |
404 | hex "Kernel ROM Base" | |
86249911 | 405 | depends on ROMKERNEL |
d86bfb16 | 406 | default "0x20040040" |
3003668c | 407 | range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x) |
8cc7117e | 408 | range 0x20000000 0x30000000 if (BF54x || BF561) |
3003668c | 409 | range 0xB0000000 0xC0000000 if (BF60x) |
8cc7117e | 410 | help |
d86bfb16 BS |
411 | Make sure your ROM base does not include any file-header |
412 | information that is prepended to the kernel. | |
413 | ||
414 | For example, the bootable U-Boot format (created with | |
415 | mkimage) has a 64 byte header (0x40). So while the image | |
416 | you write to flash might start at say 0x20080000, you have | |
417 | to add 0x40 to get the kernel's ROM base as it will come | |
418 | after the header. | |
8cc7117e | 419 | |
f16295e7 | 420 | comment "Clock/PLL Setup" |
1394f032 BW |
421 | |
422 | config CLKIN_HZ | |
2fb6cb41 | 423 | int "Frequency of the crystal on the board in Hz" |
d0cb9b4e | 424 | default "10000000" if BFIN532_IP0X |
1394f032 | 425 | default "11059200" if BFIN533_STAMP |
d0cb9b4e MF |
426 | default "24576000" if PNAV10 |
427 | default "25000000" # most people use this | |
1394f032 | 428 | default "27000000" if BFIN533_EZKIT |
1394f032 | 429 | default "30000000" if BFIN561_EZKIT |
8effc4a6 | 430 | default "24000000" if BFIN527_AD7160EVAL |
1394f032 BW |
431 | help |
432 | The frequency of CLKIN crystal oscillator on the board in Hz. | |
2fb6cb41 SZ |
433 | Warning: This value should match the crystal on the board. Otherwise, |
434 | peripherals won't work properly. | |
1394f032 | 435 | |
f16295e7 RG |
436 | config BFIN_KERNEL_CLOCK |
437 | bool "Re-program Clocks while Kernel boots?" | |
438 | default n | |
439 | help | |
440 | This option decides if kernel clocks are re-programed from the | |
441 | bootloader settings. If the clocks are not set, the SDRAM settings | |
442 | are also not changed, and the Bootloader does 100% of the hardware | |
443 | configuration. | |
444 | ||
445 | config PLL_BYPASS | |
e4e9a7ad | 446 | bool "Bypass PLL" |
7c141c1c | 447 | depends on BFIN_KERNEL_CLOCK && (!BF60x) |
e4e9a7ad | 448 | default n |
f16295e7 RG |
449 | |
450 | config CLKIN_HALF | |
451 | bool "Half Clock In" | |
452 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
453 | default n | |
454 | help | |
455 | If this is set the clock will be divided by 2, before it goes to the PLL. | |
456 | ||
457 | config VCO_MULT | |
458 | int "VCO Multiplier" | |
459 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
460 | range 1 64 | |
461 | default "22" if BFIN533_EZKIT | |
462 | default "45" if BFIN533_STAMP | |
6924dfb0 | 463 | default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT) |
f16295e7 | 464 | default "22" if BFIN533_BLUETECHNIX_CM |
60584344 | 465 | default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) |
7c141c1c | 466 | default "20" if (BFIN561_EZKIT || BF609) |
2f6f4bcd | 467 | default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD) |
8effc4a6 | 468 | default "25" if BFIN527_AD7160EVAL |
f16295e7 RG |
469 | help |
470 | This controls the frequency of the on-chip PLL. This can be between 1 and 64. | |
471 | PLL Frequency = (Crystal Frequency) * (this setting) | |
472 | ||
473 | choice | |
474 | prompt "Core Clock Divider" | |
475 | depends on BFIN_KERNEL_CLOCK | |
476 | default CCLK_DIV_1 | |
477 | help | |
478 | This sets the frequency of the core. It can be 1, 2, 4 or 8 | |
479 | Core Frequency = (PLL frequency) / (this setting) | |
480 | ||
481 | config CCLK_DIV_1 | |
482 | bool "1" | |
483 | ||
484 | config CCLK_DIV_2 | |
485 | bool "2" | |
486 | ||
487 | config CCLK_DIV_4 | |
488 | bool "4" | |
489 | ||
490 | config CCLK_DIV_8 | |
491 | bool "8" | |
492 | endchoice | |
493 | ||
494 | config SCLK_DIV | |
495 | int "System Clock Divider" | |
496 | depends on BFIN_KERNEL_CLOCK | |
497 | range 1 15 | |
7c141c1c | 498 | default 4 |
f16295e7 | 499 | help |
7c141c1c BL |
500 | This sets the frequency of the system clock (including SDRAM or DDR) on |
501 | !BF60x else it set the clock for system buses and provides the | |
502 | source from which SCLK0 and SCLK1 are derived. | |
f16295e7 RG |
503 | This can be between 1 and 15 |
504 | System Clock = (PLL frequency) / (this setting) | |
505 | ||
7c141c1c BL |
506 | config SCLK0_DIV |
507 | int "System Clock0 Divider" | |
508 | depends on BFIN_KERNEL_CLOCK && BF60x | |
509 | range 1 15 | |
510 | default 1 | |
511 | help | |
512 | This sets the frequency of the system clock0 for PVP and all other | |
513 | peripherals not clocked by SCLK1. | |
514 | This can be between 1 and 15 | |
515 | System Clock0 = (System Clock) / (this setting) | |
516 | ||
517 | config SCLK1_DIV | |
518 | int "System Clock1 Divider" | |
519 | depends on BFIN_KERNEL_CLOCK && BF60x | |
520 | range 1 15 | |
521 | default 1 | |
522 | help | |
523 | This sets the frequency of the system clock1 (including SPORT, SPI and ACM). | |
524 | This can be between 1 and 15 | |
525 | System Clock1 = (System Clock) / (this setting) | |
526 | ||
527 | config DCLK_DIV | |
528 | int "DDR Clock Divider" | |
529 | depends on BFIN_KERNEL_CLOCK && BF60x | |
530 | range 1 15 | |
531 | default 2 | |
532 | help | |
533 | This sets the frequency of the DDR memory. | |
534 | This can be between 1 and 15 | |
535 | DDR Clock = (PLL frequency) / (this setting) | |
536 | ||
5f004c20 MF |
537 | choice |
538 | prompt "DDR SDRAM Chip Type" | |
539 | depends on BFIN_KERNEL_CLOCK | |
540 | depends on BF54x | |
541 | default MEM_MT46V32M16_5B | |
542 | ||
543 | config MEM_MT46V32M16_6T | |
544 | bool "MT46V32M16_6T" | |
545 | ||
546 | config MEM_MT46V32M16_5B | |
547 | bool "MT46V32M16_5B" | |
548 | endchoice | |
549 | ||
73feb5c0 MH |
550 | choice |
551 | prompt "DDR/SDRAM Timing" | |
7c141c1c | 552 | depends on BFIN_KERNEL_CLOCK && !BF60x |
73feb5c0 MH |
553 | default BFIN_KERNEL_CLOCK_MEMINIT_CALC |
554 | help | |
555 | This option allows you to specify Blackfin SDRAM/DDR Timing parameters | |
556 | The calculated SDRAM timing parameters may not be 100% | |
557 | accurate - This option is therefore marked experimental. | |
558 | ||
559 | config BFIN_KERNEL_CLOCK_MEMINIT_CALC | |
560 | bool "Calculate Timings (EXPERIMENTAL)" | |
561 | depends on EXPERIMENTAL | |
562 | ||
563 | config BFIN_KERNEL_CLOCK_MEMINIT_SPEC | |
564 | bool "Provide accurate Timings based on target SCLK" | |
565 | help | |
566 | Please consult the Blackfin Hardware Reference Manuals as well | |
567 | as the memory device datasheet. | |
568 | http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram | |
569 | endchoice | |
570 | ||
571 | menu "Memory Init Control" | |
572 | depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC | |
573 | ||
574 | config MEM_DDRCTL0 | |
575 | depends on BF54x | |
576 | hex "DDRCTL0" | |
577 | default 0x0 | |
578 | ||
579 | config MEM_DDRCTL1 | |
580 | depends on BF54x | |
581 | hex "DDRCTL1" | |
582 | default 0x0 | |
583 | ||
584 | config MEM_DDRCTL2 | |
585 | depends on BF54x | |
586 | hex "DDRCTL2" | |
587 | default 0x0 | |
588 | ||
589 | config MEM_EBIU_DDRQUE | |
590 | depends on BF54x | |
591 | hex "DDRQUE" | |
592 | default 0x0 | |
593 | ||
594 | config MEM_SDRRC | |
595 | depends on !BF54x | |
596 | hex "SDRRC" | |
597 | default 0x0 | |
598 | ||
599 | config MEM_SDGCTL | |
600 | depends on !BF54x | |
601 | hex "SDGCTL" | |
602 | default 0x0 | |
603 | endmenu | |
604 | ||
f16295e7 RG |
605 | # |
606 | # Max & Min Speeds for various Chips | |
607 | # | |
608 | config MAX_VCO_HZ | |
609 | int | |
2f6f4bcd BW |
610 | default 400000000 if BF512 |
611 | default 400000000 if BF514 | |
612 | default 400000000 if BF516 | |
613 | default 400000000 if BF518 | |
7b06263b MF |
614 | default 400000000 if BF522 |
615 | default 600000000 if BF523 | |
1545a111 | 616 | default 400000000 if BF524 |
f16295e7 | 617 | default 600000000 if BF525 |
1545a111 | 618 | default 400000000 if BF526 |
f16295e7 RG |
619 | default 600000000 if BF527 |
620 | default 400000000 if BF531 | |
621 | default 400000000 if BF532 | |
622 | default 750000000 if BF533 | |
623 | default 500000000 if BF534 | |
624 | default 400000000 if BF536 | |
625 | default 600000000 if BF537 | |
f72eecb9 RG |
626 | default 533333333 if BF538 |
627 | default 533333333 if BF539 | |
f16295e7 | 628 | default 600000000 if BF542 |
f72eecb9 | 629 | default 533333333 if BF544 |
1545a111 MF |
630 | default 600000000 if BF547 |
631 | default 600000000 if BF548 | |
f72eecb9 | 632 | default 533333333 if BF549 |
f16295e7 | 633 | default 600000000 if BF561 |
7c141c1c | 634 | default 800000000 if BF609 |
f16295e7 RG |
635 | |
636 | config MIN_VCO_HZ | |
637 | int | |
638 | default 50000000 | |
639 | ||
640 | config MAX_SCLK_HZ | |
641 | int | |
7c141c1c | 642 | default 200000000 if BF609 |
f72eecb9 | 643 | default 133333333 |
f16295e7 RG |
644 | |
645 | config MIN_SCLK_HZ | |
646 | int | |
647 | default 27000000 | |
648 | ||
649 | comment "Kernel Timer/Scheduler" | |
650 | ||
651 | source kernel/Kconfig.hz | |
652 | ||
dfbaec06 | 653 | config SET_GENERIC_CLOCKEVENTS |
8b5f79f9 | 654 | bool "Generic clock events" |
8b5f79f9 | 655 | default y |
dfbaec06 | 656 | select GENERIC_CLOCKEVENTS |
8b5f79f9 | 657 | |
0d152c27 | 658 | menu "Clock event device" |
1fa9be72 | 659 | depends on GENERIC_CLOCKEVENTS |
1fa9be72 | 660 | config TICKSOURCE_GPTMR0 |
0d152c27 YL |
661 | bool "GPTimer0" |
662 | depends on !SMP | |
1fa9be72 | 663 | select BFIN_GPTIMERS |
1fa9be72 GY |
664 | |
665 | config TICKSOURCE_CORETMR | |
0d152c27 YL |
666 | bool "Core timer" |
667 | default y | |
668 | endmenu | |
1fa9be72 | 669 | |
0d152c27 | 670 | menu "Clock souce" |
8b5f79f9 | 671 | depends on GENERIC_CLOCKEVENTS |
0d152c27 YL |
672 | config CYCLES_CLOCKSOURCE |
673 | bool "CYCLES" | |
674 | default y | |
8b5f79f9 | 675 | depends on !BFIN_SCRATCH_REG_CYCLES |
1fa9be72 | 676 | depends on !SMP |
8b5f79f9 VM |
677 | help |
678 | If you say Y here, you will enable support for using the 'cycles' | |
679 | registers as a clock source. Doing so means you will be unable to | |
680 | safely write to the 'cycles' register during runtime. You will | |
681 | still be able to read it (such as for performance monitoring), but | |
682 | writing the registers will most likely crash the kernel. | |
683 | ||
1fa9be72 | 684 | config GPTMR0_CLOCKSOURCE |
0d152c27 | 685 | bool "GPTimer0" |
3aca47c0 | 686 | select BFIN_GPTIMERS |
1fa9be72 | 687 | depends on !TICKSOURCE_GPTMR0 |
0d152c27 | 688 | endmenu |
1fa9be72 | 689 | |
5f004c20 | 690 | comment "Misc" |
971d5bc4 | 691 | |
f0b5d12f MF |
692 | choice |
693 | prompt "Blackfin Exception Scratch Register" | |
694 | default BFIN_SCRATCH_REG_RETN | |
695 | help | |
696 | Select the resource to reserve for the Exception handler: | |
697 | - RETN: Non-Maskable Interrupt (NMI) | |
698 | - RETE: Exception Return (JTAG/ICE) | |
699 | - CYCLES: Performance counter | |
700 | ||
701 | If you are unsure, please select "RETN". | |
702 | ||
703 | config BFIN_SCRATCH_REG_RETN | |
704 | bool "RETN" | |
705 | help | |
706 | Use the RETN register in the Blackfin exception handler | |
707 | as a stack scratch register. This means you cannot | |
708 | safely use NMI on the Blackfin while running Linux, but | |
709 | you can debug the system with a JTAG ICE and use the | |
710 | CYCLES performance registers. | |
711 | ||
712 | If you are unsure, please select "RETN". | |
713 | ||
714 | config BFIN_SCRATCH_REG_RETE | |
715 | bool "RETE" | |
716 | help | |
717 | Use the RETE register in the Blackfin exception handler | |
718 | as a stack scratch register. This means you cannot | |
719 | safely use a JTAG ICE while debugging a Blackfin board, | |
720 | but you can safely use the CYCLES performance registers | |
721 | and the NMI. | |
722 | ||
723 | If you are unsure, please select "RETN". | |
724 | ||
725 | config BFIN_SCRATCH_REG_CYCLES | |
726 | bool "CYCLES" | |
727 | help | |
728 | Use the CYCLES register in the Blackfin exception handler | |
729 | as a stack scratch register. This means you cannot | |
730 | safely use the CYCLES performance registers on a Blackfin | |
731 | board at anytime, but you can debug the system with a JTAG | |
732 | ICE and use the NMI. | |
733 | ||
734 | If you are unsure, please select "RETN". | |
735 | ||
736 | endchoice | |
737 | ||
1394f032 BW |
738 | endmenu |
739 | ||
740 | ||
741 | menu "Blackfin Kernel Optimizations" | |
742 | ||
1394f032 BW |
743 | comment "Memory Optimizations" |
744 | ||
745 | config I_ENTRY_L1 | |
746 | bool "Locate interrupt entry code in L1 Memory" | |
747 | default y | |
820b127d | 748 | depends on !SMP |
1394f032 | 749 | help |
01dd2fbf ML |
750 | If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked |
751 | into L1 instruction memory. (less latency) | |
1394f032 BW |
752 | |
753 | config EXCPT_IRQ_SYSC_L1 | |
01dd2fbf | 754 | bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" |
1394f032 | 755 | default y |
820b127d | 756 | depends on !SMP |
1394f032 | 757 | help |
01dd2fbf | 758 | If enabled, the entire ASM lowlevel exception and interrupt entry code |
cfefe3c6 | 759 | (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. |
01dd2fbf | 760 | (less latency) |
1394f032 BW |
761 | |
762 | config DO_IRQ_L1 | |
763 | bool "Locate frequently called do_irq dispatcher function in L1 Memory" | |
764 | default y | |
820b127d | 765 | depends on !SMP |
1394f032 | 766 | help |
01dd2fbf ML |
767 | If enabled, the frequently called do_irq dispatcher function is linked |
768 | into L1 instruction memory. (less latency) | |
1394f032 BW |
769 | |
770 | config CORE_TIMER_IRQ_L1 | |
771 | bool "Locate frequently called timer_interrupt() function in L1 Memory" | |
772 | default y | |
820b127d | 773 | depends on !SMP |
1394f032 | 774 | help |
01dd2fbf ML |
775 | If enabled, the frequently called timer_interrupt() function is linked |
776 | into L1 instruction memory. (less latency) | |
1394f032 BW |
777 | |
778 | config IDLE_L1 | |
779 | bool "Locate frequently idle function in L1 Memory" | |
780 | default y | |
820b127d | 781 | depends on !SMP |
1394f032 | 782 | help |
01dd2fbf ML |
783 | If enabled, the frequently called idle function is linked |
784 | into L1 instruction memory. (less latency) | |
1394f032 BW |
785 | |
786 | config SCHEDULE_L1 | |
787 | bool "Locate kernel schedule function in L1 Memory" | |
788 | default y | |
820b127d | 789 | depends on !SMP |
1394f032 | 790 | help |
01dd2fbf ML |
791 | If enabled, the frequently called kernel schedule is linked |
792 | into L1 instruction memory. (less latency) | |
1394f032 BW |
793 | |
794 | config ARITHMETIC_OPS_L1 | |
795 | bool "Locate kernel owned arithmetic functions in L1 Memory" | |
796 | default y | |
820b127d | 797 | depends on !SMP |
1394f032 | 798 | help |
01dd2fbf ML |
799 | If enabled, arithmetic functions are linked |
800 | into L1 instruction memory. (less latency) | |
1394f032 BW |
801 | |
802 | config ACCESS_OK_L1 | |
803 | bool "Locate access_ok function in L1 Memory" | |
804 | default y | |
820b127d | 805 | depends on !SMP |
1394f032 | 806 | help |
01dd2fbf ML |
807 | If enabled, the access_ok function is linked |
808 | into L1 instruction memory. (less latency) | |
1394f032 BW |
809 | |
810 | config MEMSET_L1 | |
811 | bool "Locate memset function in L1 Memory" | |
812 | default y | |
820b127d | 813 | depends on !SMP |
1394f032 | 814 | help |
01dd2fbf ML |
815 | If enabled, the memset function is linked |
816 | into L1 instruction memory. (less latency) | |
1394f032 BW |
817 | |
818 | config MEMCPY_L1 | |
819 | bool "Locate memcpy function in L1 Memory" | |
820 | default y | |
820b127d | 821 | depends on !SMP |
1394f032 | 822 | help |
01dd2fbf ML |
823 | If enabled, the memcpy function is linked |
824 | into L1 instruction memory. (less latency) | |
1394f032 | 825 | |
479ba603 RG |
826 | config STRCMP_L1 |
827 | bool "locate strcmp function in L1 Memory" | |
828 | default y | |
820b127d | 829 | depends on !SMP |
479ba603 RG |
830 | help |
831 | If enabled, the strcmp function is linked | |
832 | into L1 instruction memory (less latency). | |
833 | ||
834 | config STRNCMP_L1 | |
835 | bool "locate strncmp function in L1 Memory" | |
836 | default y | |
820b127d | 837 | depends on !SMP |
479ba603 RG |
838 | help |
839 | If enabled, the strncmp function is linked | |
840 | into L1 instruction memory (less latency). | |
841 | ||
842 | config STRCPY_L1 | |
843 | bool "locate strcpy function in L1 Memory" | |
844 | default y | |
820b127d | 845 | depends on !SMP |
479ba603 RG |
846 | help |
847 | If enabled, the strcpy function is linked | |
848 | into L1 instruction memory (less latency). | |
849 | ||
850 | config STRNCPY_L1 | |
851 | bool "locate strncpy function in L1 Memory" | |
852 | default y | |
820b127d | 853 | depends on !SMP |
479ba603 RG |
854 | help |
855 | If enabled, the strncpy function is linked | |
856 | into L1 instruction memory (less latency). | |
857 | ||
1394f032 BW |
858 | config SYS_BFIN_SPINLOCK_L1 |
859 | bool "Locate sys_bfin_spinlock function in L1 Memory" | |
860 | default y | |
820b127d | 861 | depends on !SMP |
1394f032 | 862 | help |
01dd2fbf ML |
863 | If enabled, sys_bfin_spinlock function is linked |
864 | into L1 instruction memory. (less latency) | |
1394f032 BW |
865 | |
866 | config IP_CHECKSUM_L1 | |
867 | bool "Locate IP Checksum function in L1 Memory" | |
868 | default n | |
820b127d | 869 | depends on !SMP |
1394f032 | 870 | help |
01dd2fbf ML |
871 | If enabled, the IP Checksum function is linked |
872 | into L1 instruction memory. (less latency) | |
1394f032 BW |
873 | |
874 | config CACHELINE_ALIGNED_L1 | |
875 | bool "Locate cacheline_aligned data to L1 Data Memory" | |
157cc5aa MH |
876 | default y if !BF54x |
877 | default n if BF54x | |
95fc2d8f | 878 | depends on !SMP && !BF531 && !CRC32 |
1394f032 | 879 | help |
692105b8 | 880 | If enabled, cacheline_aligned data is linked |
01dd2fbf | 881 | into L1 data memory. (less latency) |
1394f032 BW |
882 | |
883 | config SYSCALL_TAB_L1 | |
884 | bool "Locate Syscall Table L1 Data Memory" | |
885 | default n | |
820b127d | 886 | depends on !SMP && !BF531 |
1394f032 | 887 | help |
01dd2fbf ML |
888 | If enabled, the Syscall LUT is linked |
889 | into L1 data memory. (less latency) | |
1394f032 BW |
890 | |
891 | config CPLB_SWITCH_TAB_L1 | |
892 | bool "Locate CPLB Switch Tables L1 Data Memory" | |
893 | default n | |
820b127d | 894 | depends on !SMP && !BF531 |
1394f032 | 895 | help |
01dd2fbf ML |
896 | If enabled, the CPLB Switch Tables are linked |
897 | into L1 data memory. (less latency) | |
1394f032 | 898 | |
820b127d MF |
899 | config ICACHE_FLUSH_L1 |
900 | bool "Locate icache flush funcs in L1 Inst Memory" | |
74181295 MF |
901 | default y |
902 | help | |
820b127d | 903 | If enabled, the Blackfin icache flushing functions are linked |
74181295 MF |
904 | into L1 instruction memory. |
905 | ||
906 | Note that this might be required to address anomalies, but | |
907 | these functions are pretty small, so it shouldn't be too bad. | |
908 | If you are using a processor affected by an anomaly, the build | |
909 | system will double check for you and prevent it. | |
910 | ||
820b127d MF |
911 | config DCACHE_FLUSH_L1 |
912 | bool "Locate dcache flush funcs in L1 Inst Memory" | |
913 | default y | |
914 | depends on !SMP | |
915 | help | |
916 | If enabled, the Blackfin dcache flushing functions are linked | |
917 | into L1 instruction memory. | |
918 | ||
ca87b7ad GY |
919 | config APP_STACK_L1 |
920 | bool "Support locating application stack in L1 Scratch Memory" | |
921 | default y | |
820b127d | 922 | depends on !SMP |
ca87b7ad GY |
923 | help |
924 | If enabled the application stack can be located in L1 | |
925 | scratch memory (less latency). | |
926 | ||
927 | Currently only works with FLAT binaries. | |
928 | ||
6ad2b84c MF |
929 | config EXCEPTION_L1_SCRATCH |
930 | bool "Locate exception stack in L1 Scratch Memory" | |
931 | default n | |
820b127d | 932 | depends on !SMP && !APP_STACK_L1 |
6ad2b84c MF |
933 | help |
934 | Whenever an exception occurs, use the L1 Scratch memory for | |
935 | stack storage. You cannot place the stacks of FLAT binaries | |
936 | in L1 when using this option. | |
937 | ||
938 | If you don't use L1 Scratch, then you should say Y here. | |
939 | ||
251383c7 RG |
940 | comment "Speed Optimizations" |
941 | config BFIN_INS_LOWOVERHEAD | |
942 | bool "ins[bwl] low overhead, higher interrupt latency" | |
943 | default y | |
820b127d | 944 | depends on !SMP |
251383c7 RG |
945 | help |
946 | Reads on the Blackfin are speculative. In Blackfin terms, this means | |
947 | they can be interrupted at any time (even after they have been issued | |
948 | on to the external bus), and re-issued after the interrupt occurs. | |
949 | For memory - this is not a big deal, since memory does not change if | |
950 | it sees a read. | |
951 | ||
952 | If a FIFO is sitting on the end of the read, it will see two reads, | |
953 | when the core only sees one since the FIFO receives both the read | |
954 | which is cancelled (and not delivered to the core) and the one which | |
955 | is re-issued (which is delivered to the core). | |
956 | ||
957 | To solve this, interrupts are turned off before reads occur to | |
958 | I/O space. This option controls which the overhead/latency of | |
959 | controlling interrupts during this time | |
960 | "n" turns interrupts off every read | |
961 | (higher overhead, but lower interrupt latency) | |
962 | "y" turns interrupts off every loop | |
963 | (low overhead, but longer interrupt latency) | |
964 | ||
965 | default behavior is to leave this set to on (type "Y"). If you are experiencing | |
966 | interrupt latency issues, it is safe and OK to turn this off. | |
967 | ||
1394f032 BW |
968 | endmenu |
969 | ||
1394f032 BW |
970 | choice |
971 | prompt "Kernel executes from" | |
972 | help | |
973 | Choose the memory type that the kernel will be running in. | |
974 | ||
975 | config RAMKERNEL | |
976 | bool "RAM" | |
977 | help | |
978 | The kernel will be resident in RAM when running. | |
979 | ||
980 | config ROMKERNEL | |
981 | bool "ROM" | |
982 | help | |
983 | The kernel will be resident in FLASH/ROM when running. | |
984 | ||
985 | endchoice | |
986 | ||
56b4f07a MF |
987 | # Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both |
988 | config XIP_KERNEL | |
989 | bool | |
990 | default y | |
991 | depends on ROMKERNEL | |
992 | ||
1394f032 BW |
993 | source "mm/Kconfig" |
994 | ||
780431e3 MF |
995 | config BFIN_GPTIMERS |
996 | tristate "Enable Blackfin General Purpose Timers API" | |
997 | default n | |
998 | help | |
999 | Enable support for the General Purpose Timers API. If you | |
1000 | are unsure, say N. | |
1001 | ||
1002 | To compile this driver as a module, choose M here: the module | |
4737f097 | 1003 | will be called gptimers. |
780431e3 | 1004 | |
006669ec MF |
1005 | config HAVE_PWM |
1006 | tristate "Enable PWM API support" | |
1007 | depends on BFIN_GPTIMERS | |
1008 | help | |
1009 | Enable support for the Pulse Width Modulation framework (as | |
1010 | found in linux/pwm.h). | |
1011 | ||
1012 | To compile this driver as a module, choose M here: the module | |
1013 | will be called pwm. | |
1014 | ||
1394f032 | 1015 | choice |
d292b000 | 1016 | prompt "Uncached DMA region" |
1394f032 | 1017 | default DMA_UNCACHED_1M |
c8d11a06 SJ |
1018 | config DMA_UNCACHED_32M |
1019 | bool "Enable 32M DMA region" | |
1020 | config DMA_UNCACHED_16M | |
1021 | bool "Enable 16M DMA region" | |
1022 | config DMA_UNCACHED_8M | |
1023 | bool "Enable 8M DMA region" | |
86ad7932 CC |
1024 | config DMA_UNCACHED_4M |
1025 | bool "Enable 4M DMA region" | |
1394f032 BW |
1026 | config DMA_UNCACHED_2M |
1027 | bool "Enable 2M DMA region" | |
1028 | config DMA_UNCACHED_1M | |
1029 | bool "Enable 1M DMA region" | |
c45c0659 BS |
1030 | config DMA_UNCACHED_512K |
1031 | bool "Enable 512K DMA region" | |
1032 | config DMA_UNCACHED_256K | |
1033 | bool "Enable 256K DMA region" | |
1034 | config DMA_UNCACHED_128K | |
1035 | bool "Enable 128K DMA region" | |
1394f032 BW |
1036 | config DMA_UNCACHED_NONE |
1037 | bool "Disable DMA region" | |
1038 | endchoice | |
1039 | ||
1040 | ||
1041 | comment "Cache Support" | |
41ba653f | 1042 | |
3bebca2d | 1043 | config BFIN_ICACHE |
1394f032 | 1044 | bool "Enable ICACHE" |
41ba653f | 1045 | default y |
41ba653f JZ |
1046 | config BFIN_EXTMEM_ICACHEABLE |
1047 | bool "Enable ICACHE for external memory" | |
1048 | depends on BFIN_ICACHE | |
1049 | default y | |
1050 | config BFIN_L2_ICACHEABLE | |
1051 | bool "Enable ICACHE for L2 SRAM" | |
1052 | depends on BFIN_ICACHE | |
b0ce61d5 | 1053 | depends on (BF54x || BF561 || BF60x) && !SMP |
41ba653f JZ |
1054 | default n |
1055 | ||
3bebca2d | 1056 | config BFIN_DCACHE |
1394f032 | 1057 | bool "Enable DCACHE" |
41ba653f | 1058 | default y |
3bebca2d | 1059 | config BFIN_DCACHE_BANKA |
1394f032 | 1060 | bool "Enable only 16k BankA DCACHE - BankB is SRAM" |
3bebca2d | 1061 | depends on BFIN_DCACHE && !BF531 |
1394f032 | 1062 | default n |
41ba653f JZ |
1063 | config BFIN_EXTMEM_DCACHEABLE |
1064 | bool "Enable DCACHE for external memory" | |
3bebca2d | 1065 | depends on BFIN_DCACHE |
41ba653f JZ |
1066 | default y |
1067 | choice | |
1068 | prompt "External memory DCACHE policy" | |
1069 | depends on BFIN_EXTMEM_DCACHEABLE | |
1070 | default BFIN_EXTMEM_WRITEBACK if !SMP | |
1071 | default BFIN_EXTMEM_WRITETHROUGH if SMP | |
1072 | config BFIN_EXTMEM_WRITEBACK | |
1394f032 | 1073 | bool "Write back" |
46fa5eec | 1074 | depends on !SMP |
1394f032 BW |
1075 | help |
1076 | Write Back Policy: | |
1077 | Cached data will be written back to SDRAM only when needed. | |
1078 | This can give a nice increase in performance, but beware of | |
1079 | broken drivers that do not properly invalidate/flush their | |
1080 | cache. | |
1081 | ||
1082 | Write Through Policy: | |
1083 | Cached data will always be written back to SDRAM when the | |
1084 | cache is updated. This is a completely safe setting, but | |
1085 | performance is worse than Write Back. | |
1086 | ||
1087 | If you are unsure of the options and you want to be safe, | |
1088 | then go with Write Through. | |
1089 | ||
41ba653f | 1090 | config BFIN_EXTMEM_WRITETHROUGH |
1394f032 BW |
1091 | bool "Write through" |
1092 | help | |
1093 | Write Back Policy: | |
1094 | Cached data will be written back to SDRAM only when needed. | |
1095 | This can give a nice increase in performance, but beware of | |
1096 | broken drivers that do not properly invalidate/flush their | |
1097 | cache. | |
1098 | ||
1099 | Write Through Policy: | |
1100 | Cached data will always be written back to SDRAM when the | |
1101 | cache is updated. This is a completely safe setting, but | |
1102 | performance is worse than Write Back. | |
1103 | ||
1104 | If you are unsure of the options and you want to be safe, | |
1105 | then go with Write Through. | |
1106 | ||
1107 | endchoice | |
1108 | ||
41ba653f JZ |
1109 | config BFIN_L2_DCACHEABLE |
1110 | bool "Enable DCACHE for L2 SRAM" | |
1111 | depends on BFIN_DCACHE | |
b5affb01 | 1112 | depends on (BF54x || BF561 || BF60x) && !SMP |
41ba653f | 1113 | default n |
5ba76675 | 1114 | choice |
41ba653f JZ |
1115 | prompt "L2 SRAM DCACHE policy" |
1116 | depends on BFIN_L2_DCACHEABLE | |
1117 | default BFIN_L2_WRITEBACK | |
1118 | config BFIN_L2_WRITEBACK | |
5ba76675 | 1119 | bool "Write back" |
5ba76675 | 1120 | |
41ba653f | 1121 | config BFIN_L2_WRITETHROUGH |
5ba76675 | 1122 | bool "Write through" |
5ba76675 | 1123 | endchoice |
f099f39a | 1124 | |
41ba653f JZ |
1125 | |
1126 | comment "Memory Protection Unit" | |
b97b8a99 BS |
1127 | config MPU |
1128 | bool "Enable the memory protection unit (EXPERIMENTAL)" | |
1129 | default n | |
1130 | help | |
1131 | Use the processor's MPU to protect applications from accessing | |
1132 | memory they do not own. This comes at a performance penalty | |
1133 | and is recommended only for debugging. | |
1134 | ||
692105b8 | 1135 | comment "Asynchronous Memory Configuration" |
1394f032 | 1136 | |
ddf416b2 | 1137 | menu "EBIU_AMGCTL Global Control" |
b5affb01 | 1138 | depends on !BF60x |
1394f032 BW |
1139 | config C_AMCKEN |
1140 | bool "Enable CLKOUT" | |
1141 | default y | |
1142 | ||
1143 | config C_CDPRIO | |
1144 | bool "DMA has priority over core for ext. accesses" | |
1145 | default n | |
1146 | ||
1147 | config C_B0PEN | |
1148 | depends on BF561 | |
1149 | bool "Bank 0 16 bit packing enable" | |
1150 | default y | |
1151 | ||
1152 | config C_B1PEN | |
1153 | depends on BF561 | |
1154 | bool "Bank 1 16 bit packing enable" | |
1155 | default y | |
1156 | ||
1157 | config C_B2PEN | |
1158 | depends on BF561 | |
1159 | bool "Bank 2 16 bit packing enable" | |
1160 | default y | |
1161 | ||
1162 | config C_B3PEN | |
1163 | depends on BF561 | |
1164 | bool "Bank 3 16 bit packing enable" | |
1165 | default n | |
1166 | ||
1167 | choice | |
692105b8 | 1168 | prompt "Enable Asynchronous Memory Banks" |
1394f032 BW |
1169 | default C_AMBEN_ALL |
1170 | ||
1171 | config C_AMBEN | |
1172 | bool "Disable All Banks" | |
1173 | ||
1174 | config C_AMBEN_B0 | |
1175 | bool "Enable Bank 0" | |
1176 | ||
1177 | config C_AMBEN_B0_B1 | |
1178 | bool "Enable Bank 0 & 1" | |
1179 | ||
1180 | config C_AMBEN_B0_B1_B2 | |
1181 | bool "Enable Bank 0 & 1 & 2" | |
1182 | ||
1183 | config C_AMBEN_ALL | |
1184 | bool "Enable All Banks" | |
1185 | endchoice | |
1186 | endmenu | |
1187 | ||
1188 | menu "EBIU_AMBCTL Control" | |
b5affb01 | 1189 | depends on !BF60x |
1394f032 | 1190 | config BANK_0 |
c8342f87 | 1191 | hex "Bank 0 (AMBCTL0.L)" |
1394f032 | 1192 | default 0x7BB0 |
c8342f87 MF |
1193 | help |
1194 | These are the low 16 bits of the EBIU_AMBCTL0 MMR which are | |
1195 | used to control the Asynchronous Memory Bank 0 settings. | |
1394f032 BW |
1196 | |
1197 | config BANK_1 | |
c8342f87 | 1198 | hex "Bank 1 (AMBCTL0.H)" |
1394f032 | 1199 | default 0x7BB0 |
197fba56 | 1200 | default 0x5558 if BF54x |
c8342f87 MF |
1201 | help |
1202 | These are the high 16 bits of the EBIU_AMBCTL0 MMR which are | |
1203 | used to control the Asynchronous Memory Bank 1 settings. | |
1394f032 BW |
1204 | |
1205 | config BANK_2 | |
c8342f87 | 1206 | hex "Bank 2 (AMBCTL1.L)" |
1394f032 | 1207 | default 0x7BB0 |
c8342f87 MF |
1208 | help |
1209 | These are the low 16 bits of the EBIU_AMBCTL1 MMR which are | |
1210 | used to control the Asynchronous Memory Bank 2 settings. | |
1394f032 BW |
1211 | |
1212 | config BANK_3 | |
c8342f87 | 1213 | hex "Bank 3 (AMBCTL1.H)" |
1394f032 | 1214 | default 0x99B3 |
c8342f87 MF |
1215 | help |
1216 | These are the high 16 bits of the EBIU_AMBCTL1 MMR which are | |
1217 | used to control the Asynchronous Memory Bank 3 settings. | |
1218 | ||
1394f032 BW |
1219 | endmenu |
1220 | ||
e40540b3 SZ |
1221 | config EBIU_MBSCTLVAL |
1222 | hex "EBIU Bank Select Control Register" | |
1223 | depends on BF54x | |
1224 | default 0 | |
1225 | ||
1226 | config EBIU_MODEVAL | |
1227 | hex "Flash Memory Mode Control Register" | |
1228 | depends on BF54x | |
1229 | default 1 | |
1230 | ||
1231 | config EBIU_FCTLVAL | |
1232 | hex "Flash Memory Bank Control Register" | |
1233 | depends on BF54x | |
1234 | default 6 | |
1394f032 BW |
1235 | endmenu |
1236 | ||
1237 | ############################################################################# | |
1238 | menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" | |
1239 | ||
1240 | config PCI | |
1241 | bool "PCI support" | |
a95ca3b2 | 1242 | depends on BROKEN |
1394f032 BW |
1243 | help |
1244 | Support for PCI bus. | |
1245 | ||
1246 | source "drivers/pci/Kconfig" | |
1247 | ||
1394f032 BW |
1248 | source "drivers/pcmcia/Kconfig" |
1249 | ||
1250 | source "drivers/pci/hotplug/Kconfig" | |
1251 | ||
1252 | endmenu | |
1253 | ||
1254 | menu "Executable file formats" | |
1255 | ||
1256 | source "fs/Kconfig.binfmt" | |
1257 | ||
1258 | endmenu | |
1259 | ||
1260 | menu "Power management options" | |
ad46163a | 1261 | |
1394f032 BW |
1262 | source "kernel/power/Kconfig" |
1263 | ||
f4cb5700 JB |
1264 | config ARCH_SUSPEND_POSSIBLE |
1265 | def_bool y | |
f4cb5700 | 1266 | |
1394f032 | 1267 | choice |
1efc80b5 | 1268 | prompt "Standby Power Saving Mode" |
0fbd88ca | 1269 | depends on PM && !BF60x |
cfefe3c6 MH |
1270 | default PM_BFIN_SLEEP_DEEPER |
1271 | config PM_BFIN_SLEEP_DEEPER | |
1272 | bool "Sleep Deeper" | |
1273 | help | |
1274 | Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic | |
1275 | power dissipation by disabling the clock to the processor core (CCLK). | |
1276 | Furthermore, Standby sets the internal power supply voltage (VDDINT) | |
1277 | to 0.85 V to provide the greatest power savings, while preserving the | |
1278 | processor state. | |
1279 | The PLL and system clock (SCLK) continue to operate at a very low | |
1280 | frequency of about 3.3 MHz. To preserve data integrity in the SDRAM, | |
1281 | the SDRAM is put into Self Refresh Mode. Typically an external event | |
1282 | such as GPIO interrupt or RTC activity wakes up the processor. | |
1283 | Various Peripherals such as UART, SPORT, PPI may not function as | |
1284 | normal during Sleep Deeper, due to the reduced SCLK frequency. | |
1285 | When in the sleep mode, system DMA access to L1 memory is not supported. | |
1286 | ||
1efc80b5 MH |
1287 | If unsure, select "Sleep Deeper". |
1288 | ||
cfefe3c6 MH |
1289 | config PM_BFIN_SLEEP |
1290 | bool "Sleep" | |
1291 | help | |
1292 | Sleep Mode (High Power Savings) - The sleep mode reduces power | |
1293 | dissipation by disabling the clock to the processor core (CCLK). | |
1294 | The PLL and system clock (SCLK), however, continue to operate in | |
1295 | this mode. Typically an external event or RTC activity will wake | |
1efc80b5 MH |
1296 | up the processor. When in the sleep mode, system DMA access to L1 |
1297 | memory is not supported. | |
1298 | ||
1299 | If unsure, select "Sleep Deeper". | |
cfefe3c6 | 1300 | endchoice |
1394f032 | 1301 | |
1efc80b5 MH |
1302 | comment "Possible Suspend Mem / Hibernate Wake-Up Sources" |
1303 | depends on PM | |
1304 | ||
1efc80b5 MH |
1305 | config PM_BFIN_WAKE_PH6 |
1306 | bool "Allow Wake-Up from on-chip PHY or PH6 GP" | |
2f6f4bcd | 1307 | depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537) |
1efc80b5 MH |
1308 | default n |
1309 | help | |
1310 | Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up) | |
1311 | ||
1efc80b5 MH |
1312 | config PM_BFIN_WAKE_GP |
1313 | bool "Allow Wake-Up from GPIOs" | |
1314 | depends on PM && BF54x | |
1315 | default n | |
1316 | help | |
1317 | Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) | |
19986289 MH |
1318 | (all processors, except ADSP-BF549). This option sets |
1319 | the general-purpose wake-up enable (GPWE) control bit to enable | |
1320 | wake-up upon detection of an active low signal on the /GPW (PH7) pin. | |
59bf8964 | 1321 | On ADSP-BF549 this option enables the same functionality on the |
19986289 MH |
1322 | /MRXON pin also PH7. |
1323 | ||
0fbd88ca SM |
1324 | config PM_BFIN_WAKE_PA15 |
1325 | bool "Allow Wake-Up from PA15" | |
1326 | depends on PM && BF60x | |
1327 | default n | |
1328 | help | |
1329 | Enable PA15 Wake-Up | |
1330 | ||
1331 | config PM_BFIN_WAKE_PA15_POL | |
1332 | int "Wake-up priority" | |
1333 | depends on PM_BFIN_WAKE_PA15 | |
1334 | default 0 | |
1335 | help | |
1336 | Wake-Up priority 0(low) 1(high) | |
1337 | ||
1338 | config PM_BFIN_WAKE_PB15 | |
1339 | bool "Allow Wake-Up from PB15" | |
1340 | depends on PM && BF60x | |
1341 | default n | |
1342 | help | |
1343 | Enable PB15 Wake-Up | |
1344 | ||
1345 | config PM_BFIN_WAKE_PB15_POL | |
1346 | int "Wake-up priority" | |
1347 | depends on PM_BFIN_WAKE_PB15 | |
1348 | default 0 | |
1349 | help | |
1350 | Wake-Up priority 0(low) 1(high) | |
1351 | ||
1352 | config PM_BFIN_WAKE_PC15 | |
1353 | bool "Allow Wake-Up from PC15" | |
1354 | depends on PM && BF60x | |
1355 | default n | |
1356 | help | |
1357 | Enable PC15 Wake-Up | |
1358 | ||
1359 | config PM_BFIN_WAKE_PC15_POL | |
1360 | int "Wake-up priority" | |
1361 | depends on PM_BFIN_WAKE_PC15 | |
1362 | default 0 | |
1363 | help | |
1364 | Wake-Up priority 0(low) 1(high) | |
1365 | ||
1366 | config PM_BFIN_WAKE_PD06 | |
1367 | bool "Allow Wake-Up from PD06(ETH0_PHYINT)" | |
1368 | depends on PM && BF60x | |
1369 | default n | |
1370 | help | |
1371 | Enable PD06(ETH0_PHYINT) Wake-up | |
1372 | ||
1373 | config PM_BFIN_WAKE_PD06_POL | |
1374 | int "Wake-up priority" | |
1375 | depends on PM_BFIN_WAKE_PD06 | |
1376 | default 0 | |
1377 | help | |
1378 | Wake-Up priority 0(low) 1(high) | |
1379 | ||
1380 | config PM_BFIN_WAKE_PE12 | |
1381 | bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)" | |
1382 | depends on PM && BF60x | |
1383 | default n | |
1384 | help | |
1385 | Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up | |
1386 | ||
1387 | config PM_BFIN_WAKE_PE12_POL | |
1388 | int "Wake-up priority" | |
1389 | depends on PM_BFIN_WAKE_PE12 | |
1390 | default 0 | |
1391 | help | |
1392 | Wake-Up priority 0(low) 1(high) | |
1393 | ||
1394 | config PM_BFIN_WAKE_PG04 | |
1395 | bool "Allow Wake-Up from PG04(CAN0_RX)" | |
1396 | depends on PM && BF60x | |
1397 | default n | |
1398 | help | |
1399 | Enable PG04(CAN0_RX) Wake-up | |
1400 | ||
1401 | config PM_BFIN_WAKE_PG04_POL | |
1402 | int "Wake-up priority" | |
1403 | depends on PM_BFIN_WAKE_PG04 | |
1404 | default 0 | |
1405 | help | |
1406 | Wake-Up priority 0(low) 1(high) | |
1407 | ||
1408 | config PM_BFIN_WAKE_PG13 | |
1409 | bool "Allow Wake-Up from PG13" | |
1410 | depends on PM && BF60x | |
1411 | default n | |
1412 | help | |
1413 | Enable PG13 Wake-Up | |
1414 | ||
1415 | config PM_BFIN_WAKE_PG13_POL | |
1416 | int "Wake-up priority" | |
1417 | depends on PM_BFIN_WAKE_PG13 | |
1418 | default 0 | |
1419 | help | |
1420 | Wake-Up priority 0(low) 1(high) | |
1421 | ||
1422 | config PM_BFIN_WAKE_USB | |
1423 | bool "Allow Wake-Up from (USB)" | |
1424 | depends on PM && BF60x | |
1425 | default n | |
1426 | help | |
1427 | Enable (USB) Wake-up | |
1428 | ||
1429 | config PM_BFIN_WAKE_USB_POL | |
1430 | int "Wake-up priority" | |
1431 | depends on PM_BFIN_WAKE_USB | |
1432 | default 0 | |
1433 | help | |
1434 | Wake-Up priority 0(low) 1(high) | |
1435 | ||
1394f032 BW |
1436 | endmenu |
1437 | ||
1394f032 BW |
1438 | menu "CPU Frequency scaling" |
1439 | ||
1440 | source "drivers/cpufreq/Kconfig" | |
1441 | ||
5ad2ca5f MH |
1442 | config BFIN_CPU_FREQ |
1443 | bool | |
1444 | depends on CPU_FREQ | |
1445 | select CPU_FREQ_TABLE | |
1446 | default y | |
1447 | ||
14b03204 MH |
1448 | config CPU_VOLTAGE |
1449 | bool "CPU Voltage scaling" | |
73feb5c0 | 1450 | depends on EXPERIMENTAL |
14b03204 MH |
1451 | depends on CPU_FREQ |
1452 | default n | |
1453 | help | |
1454 | Say Y here if you want CPU voltage scaling according to the CPU frequency. | |
1455 | This option violates the PLL BYPASS recommendation in the Blackfin Processor | |
73feb5c0 | 1456 | manuals. There is a theoretical risk that during VDDINT transitions |
14b03204 MH |
1457 | the PLL may unlock. |
1458 | ||
1394f032 BW |
1459 | endmenu |
1460 | ||
1394f032 BW |
1461 | source "net/Kconfig" |
1462 | ||
1463 | source "drivers/Kconfig" | |
1464 | ||
872d024b MF |
1465 | source "drivers/firmware/Kconfig" |
1466 | ||
1394f032 BW |
1467 | source "fs/Kconfig" |
1468 | ||
74ce8322 | 1469 | source "arch/blackfin/Kconfig.debug" |
1394f032 BW |
1470 | |
1471 | source "security/Kconfig" | |
1472 | ||
1473 | source "crypto/Kconfig" | |
1474 | ||
1475 | source "lib/Kconfig" |