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5f97f7f9 HS |
1 | /* |
2 | * Copyright (C) 2005-2006 Atmel Corporation | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | #include <linux/init.h> | |
9 | #include <linux/sysdev.h> | |
10 | #include <linux/seq_file.h> | |
11 | #include <linux/cpu.h> | |
4ffabefb | 12 | #include <linux/module.h> |
5f97f7f9 HS |
13 | #include <linux/percpu.h> |
14 | #include <linux/param.h> | |
15 | #include <linux/errno.h> | |
281ef58c | 16 | #include <linux/clk.h> |
5f97f7f9 HS |
17 | |
18 | #include <asm/setup.h> | |
19 | #include <asm/sysreg.h> | |
20 | ||
21 | static DEFINE_PER_CPU(struct cpu, cpu_devices); | |
22 | ||
23 | #ifdef CONFIG_PERFORMANCE_COUNTERS | |
24 | ||
25 | /* | |
26 | * XXX: If/when a SMP-capable implementation of AVR32 will ever be | |
27 | * made, we must make sure that the code executes on the correct CPU. | |
28 | */ | |
29 | static ssize_t show_pc0event(struct sys_device *dev, char *buf) | |
30 | { | |
31 | unsigned long pccr; | |
32 | ||
33 | pccr = sysreg_read(PCCR); | |
34 | return sprintf(buf, "0x%lx\n", (pccr >> 12) & 0x3f); | |
35 | } | |
36 | static ssize_t store_pc0event(struct sys_device *dev, const char *buf, | |
37 | size_t count) | |
38 | { | |
39 | unsigned long val; | |
40 | char *endp; | |
41 | ||
42 | val = simple_strtoul(buf, &endp, 0); | |
43 | if (endp == buf || val > 0x3f) | |
44 | return -EINVAL; | |
45 | val = (val << 12) | (sysreg_read(PCCR) & 0xfffc0fff); | |
46 | sysreg_write(PCCR, val); | |
47 | return count; | |
48 | } | |
49 | static ssize_t show_pc0count(struct sys_device *dev, char *buf) | |
50 | { | |
51 | unsigned long pcnt0; | |
52 | ||
53 | pcnt0 = sysreg_read(PCNT0); | |
54 | return sprintf(buf, "%lu\n", pcnt0); | |
55 | } | |
56 | static ssize_t store_pc0count(struct sys_device *dev, const char *buf, | |
57 | size_t count) | |
58 | { | |
59 | unsigned long val; | |
60 | char *endp; | |
61 | ||
62 | val = simple_strtoul(buf, &endp, 0); | |
63 | if (endp == buf) | |
64 | return -EINVAL; | |
65 | sysreg_write(PCNT0, val); | |
66 | ||
67 | return count; | |
68 | } | |
69 | ||
70 | static ssize_t show_pc1event(struct sys_device *dev, char *buf) | |
71 | { | |
72 | unsigned long pccr; | |
73 | ||
74 | pccr = sysreg_read(PCCR); | |
75 | return sprintf(buf, "0x%lx\n", (pccr >> 18) & 0x3f); | |
76 | } | |
77 | static ssize_t store_pc1event(struct sys_device *dev, const char *buf, | |
78 | size_t count) | |
79 | { | |
80 | unsigned long val; | |
81 | char *endp; | |
82 | ||
83 | val = simple_strtoul(buf, &endp, 0); | |
84 | if (endp == buf || val > 0x3f) | |
85 | return -EINVAL; | |
86 | val = (val << 18) | (sysreg_read(PCCR) & 0xff03ffff); | |
87 | sysreg_write(PCCR, val); | |
88 | return count; | |
89 | } | |
90 | static ssize_t show_pc1count(struct sys_device *dev, char *buf) | |
91 | { | |
92 | unsigned long pcnt1; | |
93 | ||
94 | pcnt1 = sysreg_read(PCNT1); | |
95 | return sprintf(buf, "%lu\n", pcnt1); | |
96 | } | |
97 | static ssize_t store_pc1count(struct sys_device *dev, const char *buf, | |
98 | size_t count) | |
99 | { | |
100 | unsigned long val; | |
101 | char *endp; | |
102 | ||
103 | val = simple_strtoul(buf, &endp, 0); | |
104 | if (endp == buf) | |
105 | return -EINVAL; | |
106 | sysreg_write(PCNT1, val); | |
107 | ||
108 | return count; | |
109 | } | |
110 | ||
111 | static ssize_t show_pccycles(struct sys_device *dev, char *buf) | |
112 | { | |
113 | unsigned long pccnt; | |
114 | ||
115 | pccnt = sysreg_read(PCCNT); | |
116 | return sprintf(buf, "%lu\n", pccnt); | |
117 | } | |
118 | static ssize_t store_pccycles(struct sys_device *dev, const char *buf, | |
119 | size_t count) | |
120 | { | |
121 | unsigned long val; | |
122 | char *endp; | |
123 | ||
124 | val = simple_strtoul(buf, &endp, 0); | |
125 | if (endp == buf) | |
126 | return -EINVAL; | |
127 | sysreg_write(PCCNT, val); | |
128 | ||
129 | return count; | |
130 | } | |
131 | ||
132 | static ssize_t show_pcenable(struct sys_device *dev, char *buf) | |
133 | { | |
134 | unsigned long pccr; | |
135 | ||
136 | pccr = sysreg_read(PCCR); | |
137 | return sprintf(buf, "%c\n", (pccr & 1)?'1':'0'); | |
138 | } | |
139 | static ssize_t store_pcenable(struct sys_device *dev, const char *buf, | |
140 | size_t count) | |
141 | { | |
142 | unsigned long pccr, val; | |
143 | char *endp; | |
144 | ||
145 | val = simple_strtoul(buf, &endp, 0); | |
146 | if (endp == buf) | |
147 | return -EINVAL; | |
148 | if (val) | |
149 | val = 1; | |
150 | ||
151 | pccr = sysreg_read(PCCR); | |
152 | pccr = (pccr & ~1UL) | val; | |
153 | sysreg_write(PCCR, pccr); | |
154 | ||
155 | return count; | |
156 | } | |
157 | ||
158 | static SYSDEV_ATTR(pc0event, 0600, show_pc0event, store_pc0event); | |
159 | static SYSDEV_ATTR(pc0count, 0600, show_pc0count, store_pc0count); | |
160 | static SYSDEV_ATTR(pc1event, 0600, show_pc1event, store_pc1event); | |
161 | static SYSDEV_ATTR(pc1count, 0600, show_pc1count, store_pc1count); | |
162 | static SYSDEV_ATTR(pccycles, 0600, show_pccycles, store_pccycles); | |
163 | static SYSDEV_ATTR(pcenable, 0600, show_pcenable, store_pcenable); | |
164 | ||
165 | #endif /* CONFIG_PERFORMANCE_COUNTERS */ | |
166 | ||
167 | static int __init topology_init(void) | |
168 | { | |
169 | int cpu; | |
170 | ||
171 | for_each_possible_cpu(cpu) { | |
172 | struct cpu *c = &per_cpu(cpu_devices, cpu); | |
173 | ||
174 | register_cpu(c, cpu); | |
175 | ||
176 | #ifdef CONFIG_PERFORMANCE_COUNTERS | |
177 | sysdev_create_file(&c->sysdev, &attr_pc0event); | |
178 | sysdev_create_file(&c->sysdev, &attr_pc0count); | |
179 | sysdev_create_file(&c->sysdev, &attr_pc1event); | |
180 | sysdev_create_file(&c->sysdev, &attr_pc1count); | |
181 | sysdev_create_file(&c->sysdev, &attr_pccycles); | |
182 | sysdev_create_file(&c->sysdev, &attr_pcenable); | |
183 | #endif | |
184 | } | |
185 | ||
186 | return 0; | |
187 | } | |
188 | ||
189 | subsys_initcall(topology_init); | |
190 | ||
281ef58c HS |
191 | struct chip_id_map { |
192 | u16 mid; | |
193 | u16 pn; | |
194 | const char *name; | |
195 | }; | |
196 | ||
197 | static const struct chip_id_map chip_names[] = { | |
198 | { .mid = 0x1f, .pn = 0x1e82, .name = "AT32AP700x" }, | |
199 | }; | |
200 | #define NR_CHIP_NAMES ARRAY_SIZE(chip_names) | |
201 | ||
5f97f7f9 HS |
202 | static const char *cpu_names[] = { |
203 | "Morgan", | |
281ef58c | 204 | "AP7", |
5f97f7f9 HS |
205 | }; |
206 | #define NR_CPU_NAMES ARRAY_SIZE(cpu_names) | |
207 | ||
208 | static const char *arch_names[] = { | |
209 | "AVR32A", | |
210 | "AVR32B", | |
211 | }; | |
212 | #define NR_ARCH_NAMES ARRAY_SIZE(arch_names) | |
213 | ||
214 | static const char *mmu_types[] = { | |
215 | "No MMU", | |
216 | "ITLB and DTLB", | |
217 | "Shared TLB", | |
218 | "MPU" | |
219 | }; | |
220 | ||
281ef58c HS |
221 | static const char *cpu_feature_flags[] = { |
222 | "rmw", "dsp", "simd", "ocd", "perfctr", "java", "fpu", | |
223 | }; | |
224 | ||
225 | static const char *get_chip_name(struct avr32_cpuinfo *cpu) | |
226 | { | |
227 | unsigned int i; | |
228 | unsigned int mid = avr32_get_manufacturer_id(cpu); | |
229 | unsigned int pn = avr32_get_product_number(cpu); | |
230 | ||
231 | for (i = 0; i < NR_CHIP_NAMES; i++) { | |
232 | if (chip_names[i].mid == mid && chip_names[i].pn == pn) | |
233 | return chip_names[i].name; | |
234 | } | |
235 | ||
236 | return "(unknown)"; | |
237 | } | |
238 | ||
5f97f7f9 HS |
239 | void __init setup_processor(void) |
240 | { | |
241 | unsigned long config0, config1; | |
3b328c98 | 242 | unsigned long features; |
5f97f7f9 | 243 | unsigned cpu_id, cpu_rev, arch_id, arch_rev, mmu_type; |
281ef58c | 244 | unsigned device_id; |
5f97f7f9 | 245 | unsigned tmp; |
281ef58c | 246 | unsigned i; |
5f97f7f9 | 247 | |
3b328c98 HS |
248 | config0 = sysreg_read(CONFIG0); |
249 | config1 = sysreg_read(CONFIG1); | |
250 | cpu_id = SYSREG_BFEXT(PROCESSORID, config0); | |
251 | cpu_rev = SYSREG_BFEXT(PROCESSORREVISION, config0); | |
252 | arch_id = SYSREG_BFEXT(AT, config0); | |
253 | arch_rev = SYSREG_BFEXT(AR, config0); | |
254 | mmu_type = SYSREG_BFEXT(MMUT, config0); | |
5f97f7f9 | 255 | |
281ef58c HS |
256 | device_id = ocd_read(DID); |
257 | ||
5f97f7f9 HS |
258 | boot_cpu_data.arch_type = arch_id; |
259 | boot_cpu_data.cpu_type = cpu_id; | |
260 | boot_cpu_data.arch_revision = arch_rev; | |
261 | boot_cpu_data.cpu_revision = cpu_rev; | |
262 | boot_cpu_data.tlb_config = mmu_type; | |
281ef58c | 263 | boot_cpu_data.device_id = device_id; |
5f97f7f9 | 264 | |
3b328c98 | 265 | tmp = SYSREG_BFEXT(ILSZ, config1); |
5f97f7f9 | 266 | if (tmp) { |
3b328c98 HS |
267 | boot_cpu_data.icache.ways = 1 << SYSREG_BFEXT(IASS, config1); |
268 | boot_cpu_data.icache.sets = 1 << SYSREG_BFEXT(ISET, config1); | |
5f97f7f9 HS |
269 | boot_cpu_data.icache.linesz = 1 << (tmp + 1); |
270 | } | |
3b328c98 | 271 | tmp = SYSREG_BFEXT(DLSZ, config1); |
5f97f7f9 | 272 | if (tmp) { |
3b328c98 HS |
273 | boot_cpu_data.dcache.ways = 1 << SYSREG_BFEXT(DASS, config1); |
274 | boot_cpu_data.dcache.sets = 1 << SYSREG_BFEXT(DSET, config1); | |
5f97f7f9 HS |
275 | boot_cpu_data.dcache.linesz = 1 << (tmp + 1); |
276 | } | |
277 | ||
278 | if ((cpu_id >= NR_CPU_NAMES) || (arch_id >= NR_ARCH_NAMES)) { | |
279 | printk ("Unknown CPU configuration (ID %02x, arch %02x), " | |
280 | "continuing anyway...\n", | |
281 | cpu_id, arch_id); | |
282 | return; | |
283 | } | |
284 | ||
281ef58c HS |
285 | printk ("CPU: %s chip revision %c\n", get_chip_name(&boot_cpu_data), |
286 | avr32_get_chip_revision(&boot_cpu_data) + 'A'); | |
287 | printk ("CPU: %s [%02x] core revision %d (%s arch revision %d)\n", | |
5f97f7f9 HS |
288 | cpu_names[cpu_id], cpu_id, cpu_rev, |
289 | arch_names[arch_id], arch_rev); | |
290 | printk ("CPU: MMU configuration: %s\n", mmu_types[mmu_type]); | |
3b328c98 | 291 | |
5f97f7f9 | 292 | printk ("CPU: features:"); |
3b328c98 | 293 | features = 0; |
281ef58c | 294 | if (config0 & SYSREG_BIT(CONFIG0_R)) |
3b328c98 | 295 | features |= AVR32_FEATURE_RMW; |
281ef58c | 296 | if (config0 & SYSREG_BIT(CONFIG0_D)) |
3b328c98 | 297 | features |= AVR32_FEATURE_DSP; |
281ef58c | 298 | if (config0 & SYSREG_BIT(CONFIG0_S)) |
3b328c98 | 299 | features |= AVR32_FEATURE_SIMD; |
281ef58c | 300 | if (config0 & SYSREG_BIT(CONFIG0_O)) |
3b328c98 | 301 | features |= AVR32_FEATURE_OCD; |
281ef58c | 302 | if (config0 & SYSREG_BIT(CONFIG0_P)) |
3b328c98 | 303 | features |= AVR32_FEATURE_PCTR; |
281ef58c | 304 | if (config0 & SYSREG_BIT(CONFIG0_J)) |
3b328c98 | 305 | features |= AVR32_FEATURE_JAVA; |
281ef58c | 306 | if (config0 & SYSREG_BIT(CONFIG0_F)) |
3b328c98 | 307 | features |= AVR32_FEATURE_FPU; |
281ef58c HS |
308 | |
309 | for (i = 0; i < ARRAY_SIZE(cpu_feature_flags); i++) | |
310 | if (features & (1 << i)) | |
311 | printk(" %s", cpu_feature_flags[i]); | |
312 | ||
5f97f7f9 | 313 | printk("\n"); |
3b328c98 | 314 | boot_cpu_data.features = features; |
5f97f7f9 HS |
315 | } |
316 | ||
317 | #ifdef CONFIG_PROC_FS | |
318 | static int c_show(struct seq_file *m, void *v) | |
319 | { | |
320 | unsigned int icache_size, dcache_size; | |
321 | unsigned int cpu = smp_processor_id(); | |
281ef58c HS |
322 | unsigned int freq; |
323 | unsigned int i; | |
5f97f7f9 HS |
324 | |
325 | icache_size = boot_cpu_data.icache.ways * | |
326 | boot_cpu_data.icache.sets * | |
327 | boot_cpu_data.icache.linesz; | |
328 | dcache_size = boot_cpu_data.dcache.ways * | |
329 | boot_cpu_data.dcache.sets * | |
330 | boot_cpu_data.dcache.linesz; | |
331 | ||
332 | seq_printf(m, "processor\t: %d\n", cpu); | |
333 | ||
281ef58c HS |
334 | seq_printf(m, "chip type\t: %s revision %c\n", |
335 | get_chip_name(&boot_cpu_data), | |
336 | avr32_get_chip_revision(&boot_cpu_data) + 'A'); | |
5f97f7f9 | 337 | if (boot_cpu_data.arch_type < NR_ARCH_NAMES) |
281ef58c | 338 | seq_printf(m, "cpu arch\t: %s revision %d\n", |
5f97f7f9 HS |
339 | arch_names[boot_cpu_data.arch_type], |
340 | boot_cpu_data.arch_revision); | |
341 | if (boot_cpu_data.cpu_type < NR_CPU_NAMES) | |
281ef58c | 342 | seq_printf(m, "cpu core\t: %s revision %d\n", |
5f97f7f9 HS |
343 | cpu_names[boot_cpu_data.cpu_type], |
344 | boot_cpu_data.cpu_revision); | |
345 | ||
281ef58c HS |
346 | freq = (clk_get_rate(boot_cpu_data.clk) + 500) / 1000; |
347 | seq_printf(m, "cpu MHz\t\t: %u.%03u\n", freq / 1000, freq % 1000); | |
348 | ||
5f97f7f9 HS |
349 | seq_printf(m, "i-cache\t\t: %dK (%u ways x %u sets x %u)\n", |
350 | icache_size >> 10, | |
351 | boot_cpu_data.icache.ways, | |
352 | boot_cpu_data.icache.sets, | |
353 | boot_cpu_data.icache.linesz); | |
354 | seq_printf(m, "d-cache\t\t: %dK (%u ways x %u sets x %u)\n", | |
355 | dcache_size >> 10, | |
356 | boot_cpu_data.dcache.ways, | |
357 | boot_cpu_data.dcache.sets, | |
358 | boot_cpu_data.dcache.linesz); | |
281ef58c HS |
359 | |
360 | seq_printf(m, "features\t:"); | |
361 | for (i = 0; i < ARRAY_SIZE(cpu_feature_flags); i++) | |
362 | if (boot_cpu_data.features & (1 << i)) | |
363 | seq_printf(m, " %s", cpu_feature_flags[i]); | |
364 | ||
365 | seq_printf(m, "\nbogomips\t: %lu.%02lu\n", | |
5f97f7f9 HS |
366 | boot_cpu_data.loops_per_jiffy / (500000/HZ), |
367 | (boot_cpu_data.loops_per_jiffy / (5000/HZ)) % 100); | |
368 | ||
369 | return 0; | |
370 | } | |
371 | ||
372 | static void *c_start(struct seq_file *m, loff_t *pos) | |
373 | { | |
374 | return *pos < 1 ? (void *)1 : NULL; | |
375 | } | |
376 | ||
377 | static void *c_next(struct seq_file *m, void *v, loff_t *pos) | |
378 | { | |
379 | ++*pos; | |
380 | return NULL; | |
381 | } | |
382 | ||
383 | static void c_stop(struct seq_file *m, void *v) | |
384 | { | |
385 | ||
386 | } | |
387 | ||
f6135d12 | 388 | const struct seq_operations cpuinfo_op = { |
5f97f7f9 HS |
389 | .start = c_start, |
390 | .next = c_next, | |
391 | .stop = c_stop, | |
392 | .show = c_show | |
393 | }; | |
394 | #endif /* CONFIG_PROC_FS */ |