[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm64 / mm / proc.S

/*
 * Based on arch/arm/mm/proc.S
 *
 * Copyright (C) 2001 Deep Blue Solutions Ltd.
 * Copyright (C) 2012 ARM Ltd.
 * Author: Catalin Marinas <catalin.marinas@arm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/init.h>
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>

#include "proc-macros.S"

#ifndef CONFIG_SMP
/* PTWs cacheable, inner/outer WBWA not shareable */
#define TCR_FLAGS	TCR_IRGN_WBWA | TCR_ORGN_WBWA
#else
/* PTWs cacheable, inner/outer WBWA shareable */
#define TCR_FLAGS	TCR_IRGN_WBWA | TCR_ORGN_WBWA | TCR_SHARED
#endif

#define MAIR(attr, mt)	((attr) << ((mt) * 8))

/*
 *	cpu_cache_off()
 *
 *	Turn the CPU D-cache off.
 */
ENTRY(cpu_cache_off)
	mrs	x0, sctlr_el1
	bic	x0, x0, #1 << 2			// clear SCTLR.C
	msr	sctlr_el1, x0
	isb
	ret
ENDPROC(cpu_cache_off)

/*
 *	cpu_reset(loc)
 *
 *	Perform a soft reset of the system.  Put the CPU into the same state
 *	as it would be if it had been reset, and branch to what would be the
 *	reset vector. It must be executed with the flat identity mapping.
 *
 *	- loc   - location to jump to for soft reset
 */
	.align	5
ENTRY(cpu_reset)
	mrs	x1, sctlr_el1
	bic	x1, x1, #1
	msr	sctlr_el1, x1			// disable the MMU
	isb
	ret	x0
ENDPROC(cpu_reset)

/*
 *	cpu_do_idle()
 *
 *	Idle the processor (wait for interrupt).
 */
ENTRY(cpu_do_idle)
	dsb	sy				// WFI may enter a low-power mode
	wfi
	ret
ENDPROC(cpu_do_idle)

#ifdef CONFIG_ARM64_CPU_SUSPEND
/**
 * cpu_do_suspend - save CPU registers context
 *
 * x0: virtual address of context pointer
 */
ENTRY(cpu_do_suspend)
	mrs	x2, tpidr_el0
	mrs	x3, tpidrro_el0
	mrs	x4, contextidr_el1
	mrs	x5, mair_el1
	mrs	x6, cpacr_el1
	mrs	x7, ttbr1_el1
	mrs	x8, tcr_el1
	mrs	x9, vbar_el1
	mrs	x10, mdscr_el1
	mrs	x11, oslsr_el1
	mrs	x12, sctlr_el1
        mrs     x13, elr_el1
        mrs     x14, spsr_el1
#if 0
        mrs     x15, S3_1_C15_C2_0      /* cpuactlr_el1 */
        mrs     x16, S3_1_C15_C2_1      /* cpuectlr_el1 */
#endif
	stp	x2, x3, [x0]
	stp	x4, x5, [x0, #16]
	stp	x6, x7, [x0, #32]
	stp	x8, x9, [x0, #48]
	stp	x10, x11, [x0, #64]
	stp	x12, x13, [x0, #80]
	stp	x14, x15, [x0, #96]
	str	x16, [x0, #112]
	ret
ENDPROC(cpu_do_suspend)

/**
 * cpu_do_resume - restore CPU register context
 *
 * x0: Physical address of context pointer
 * x1: ttbr0_el1 to be restored
 *
 * Returns:
 *	sctlr_el1 value in x0
 */
ENTRY(cpu_do_resume)
	/*
	 * Invalidate local tlb entries before turning on MMU
	 */
	tlbi	vmalle1
	ldp	x2, x3, [x0]
	ldp	x4, x5, [x0, #16]
	ldp	x6, x7, [x0, #32]
	ldp	x8, x9, [x0, #48]
	ldp	x10, x11, [x0, #64]
	ldp	x12, x13, [x0, #80]
	ldp	x14, x15, [x0, #96]
	ldr	x16, [x0, #112]
	msr	tpidr_el0, x2
	msr	tpidrro_el0, x3
	msr	contextidr_el1, x4
	msr	mair_el1, x5
	msr	cpacr_el1, x6
	msr	ttbr0_el1, x1
	msr	ttbr1_el1, x7
	msr	tcr_el1, x8
	msr	vbar_el1, x9
	msr	mdscr_el1, x10
        msr     elr_el1, x13
        msr     spsr_el1, x14
#if 0
        msr     S3_1_C15_C2_0, x15      /* cpuactlr */
        msr     S3_1_C15_C2_1, x16      /* cpuectlr */
#endif
	/*
	 * Restore oslsr_el1 by writing oslar_el1
	 */
	ubfx	x11, x11, #1, #1
	msr	oslar_el1, x11
	mov	x0, x12
	dsb	nsh		// Make sure local tlb invalidation completed
	isb
	ret
ENDPROC(cpu_do_resume)
#endif

/*
 *	cpu_do_switch_mm(pgd_phys, tsk)
 *
 *	Set the translation table base pointer to be pgd_phys.
 *
 *	- pgd_phys - physical address of new TTB
 */
ENTRY(cpu_do_switch_mm)
	mmid	w1, x1				// get mm->context.id
	bfi	x0, x1, #48, #16		// set the ASID
	msr	ttbr0_el1, x0			// set TTBR0
	isb
	ret
ENDPROC(cpu_do_switch_mm)

	.section ".text.init", #alloc, #execinstr

/*
 *	__cpu_setup
 *
 *	Initialise the processor for turning the MMU on.  Return in x0 the
 *	value of the SCTLR_EL1 register.
 */
ENTRY(__cpu_setup)
	/*
	 * Preserve the link register across the function call.
	 */
	mov	x28, lr
	bl	__flush_dcache_all
	mov	lr, x28
	ic	iallu				// I+BTB cache invalidate
	tlbi	vmalle1is			// invalidate I + D TLBs
	dsb	sy

	mov	x0, #3 << 20
	msr	cpacr_el1, x0			// Enable FP/ASIMD
	msr	mdscr_el1, xzr			// Reset mdscr_el1
	/*
	 * Memory region attributes for LPAE:
	 *
	 *   n = AttrIndx[2:0]
	 *			n	MAIR
	 *   DEVICE_nGnRnE	000	00000000
	 *   DEVICE_nGnRE	001	00000100
	 *   DEVICE_GRE		010	00001100
	 *   NORMAL_NC		011	01000100
	 *   NORMAL		100	11111111
	 */
	ldr	x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \
		     MAIR(0x04, MT_DEVICE_nGnRE) | \
		     MAIR(0x0c, MT_DEVICE_GRE) | \
		     MAIR(0x44, MT_NORMAL_NC) | \
		     MAIR(0xff, MT_NORMAL)
	msr	mair_el1, x5
	/*
	 * Prepare SCTLR
	 */
	adr	x5, crval
	ldp	w5, w6, [x5]
	mrs	x0, sctlr_el1
	bic	x0, x0, x5			// clear bits
	orr	x0, x0, x6			// set bits
	/*
	 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
	 * both user and kernel.
	 */
	ldr	x10, =TCR_TxSZ(VA_BITS) | TCR_FLAGS | TCR_IPS_40BIT | \
		      TCR_ASID16 | TCR_TBI0 | (1 << 31)
#ifdef CONFIG_ARM64_64K_PAGES
	orr	x10, x10, TCR_TG0_64K
	orr	x10, x10, TCR_TG1_64K
#endif
	msr	tcr_el1, x10
	ret					// return to head.S
ENDPROC(__cpu_setup)

#ifdef CONFIG_ARMV7_COMPAT
	/*
	 *                 n n            T
	 *       U E      WT T UD     US IHBS
	 *       CE0      XWHW CZ     ME TEEA S
	 * .... .IEE .... NEAI TE.I ..AD DEN0 ACAM
	 * 0011 0... 1101 ..0. ..0. 10.. .... .... < hardware reserved
	 * .... .100 .... 01.1 11.1 ..01 0011 1101 < software settings
	 */
	.type	crval, #object
crval:
	.word	0x030802e2			// clear
	.word	0x0405d03d			// set
#else
	/*
	 *                 n n            T
	 *       U E      WT T UD     US IHBS
	 *       CE0      XWHW CZ     ME TEEA S
	 * .... .IEE .... NEAI TE.I ..AD DEN0 ACAM
	 * 0011 0... 1101 ..0. ..0. 10.. .... .... < hardware reserved
	 * .... .100 .... 01.1 11.1 ..01 0001 1101 < software settings
	 */
	.type	crval, #object
crval:
	.word	0x030802e2			// clear
	.word	0x0405d11d			// set
#endif
Commit	Line	Data
9cce7a43 CM	1	/*
	2	* Based on arch/arm/mm/proc.S
	3	*
	4	* Copyright (C) 2001 Deep Blue Solutions Ltd.
	5	* Copyright (C) 2012 ARM Ltd.
	6	* Author: Catalin Marinas <catalin.marinas@arm.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
	21	#include <linux/init.h>
	22	#include <linux/linkage.h>
	23	#include <asm/assembler.h>
	24	#include <asm/asm-offsets.h>
	25	#include <asm/hwcap.h>
	26	#include <asm/pgtable-hwdef.h>
	27	#include <asm/pgtable.h>
	28
	29	#include "proc-macros.S"
	30
	31	#ifndef CONFIG_SMP
	32	/* PTWs cacheable, inner/outer WBWA not shareable */
	33	#define TCR_FLAGS TCR_IRGN_WBWA \| TCR_ORGN_WBWA
	34	#else
	35	/* PTWs cacheable, inner/outer WBWA shareable */
	36	#define TCR_FLAGS TCR_IRGN_WBWA \| TCR_ORGN_WBWA \| TCR_SHARED
	37	#endif
	38
	39	#define MAIR(attr, mt) ((attr) << ((mt) * 8))
	40
	41	/*
	42	* cpu_cache_off()
	43	*
	44	* Turn the CPU D-cache off.
	45	*/
	46	ENTRY(cpu_cache_off)
	47	mrs x0, sctlr_el1
	48	bic x0, x0, #1 << 2 // clear SCTLR.C
	49	msr sctlr_el1, x0
	50	isb
	51	ret
	52	ENDPROC(cpu_cache_off)
	53
	54	/*
	55	* cpu_reset(loc)
	56	*
	57	* Perform a soft reset of the system. Put the CPU into the same state
	58	* as it would be if it had been reset, and branch to what would be the
	59	* reset vector. It must be executed with the flat identity mapping.
	60	*
	61	* - loc - location to jump to for soft reset
	62	*/
	63	.align 5
	64	ENTRY(cpu_reset)
65	mrs x1, sctlr_el1
66	bic x1, x1, #1
67	msr sctlr_el1, x1 // disable the MMU
68	isb
69	ret x0
70	ENDPROC(cpu_reset)
71
72	/*
73	* cpu_do_idle()
74	*
75	* Idle the processor (wait for interrupt).
76	*/
77	ENTRY(cpu_do_idle)
78	dsb sy // WFI may enter a low-power mode
79	wfi
80	ret
81	ENDPROC(cpu_do_idle)
82
6fa3eb70 S	83	#ifdef CONFIG_ARM64_CPU_SUSPEND
	84	/**
	85	* cpu_do_suspend - save CPU registers context
	86	*
	87	* x0: virtual address of context pointer
	88	*/
	89	ENTRY(cpu_do_suspend)
	90	mrs x2, tpidr_el0
	91	mrs x3, tpidrro_el0
	92	mrs x4, contextidr_el1
	93	mrs x5, mair_el1
	94	mrs x6, cpacr_el1
	95	mrs x7, ttbr1_el1
	96	mrs x8, tcr_el1
	97	mrs x9, vbar_el1
	98	mrs x10, mdscr_el1
	99	mrs x11, oslsr_el1
	100	mrs x12, sctlr_el1
	101	mrs x13, elr_el1
	102	mrs x14, spsr_el1
	103	#if 0
	104	mrs x15, S3_1_C15_C2_0 /* cpuactlr_el1 */
	105	mrs x16, S3_1_C15_C2_1 /* cpuectlr_el1 */
	106	#endif
	107	stp x2, x3, [x0]
	108	stp x4, x5, [x0, #16]
	109	stp x6, x7, [x0, #32]
	110	stp x8, x9, [x0, #48]
	111	stp x10, x11, [x0, #64]
	112	stp x12, x13, [x0, #80]
	113	stp x14, x15, [x0, #96]
	114	str x16, [x0, #112]
	115	ret
	116	ENDPROC(cpu_do_suspend)
	117
	118	/**
	119	* cpu_do_resume - restore CPU register context
	120	*
	121	* x0: Physical address of context pointer
	122	* x1: ttbr0_el1 to be restored
	123	*
	124	* Returns:
	125	* sctlr_el1 value in x0
	126	*/
	127	ENTRY(cpu_do_resume)
	128	/*
	129	* Invalidate local tlb entries before turning on MMU
	130	*/
	131	tlbi vmalle1
	132	ldp x2, x3, [x0]
	133	ldp x4, x5, [x0, #16]
	134	ldp x6, x7, [x0, #32]
	135	ldp x8, x9, [x0, #48]
	136	ldp x10, x11, [x0, #64]
	137	ldp x12, x13, [x0, #80]
	138	ldp x14, x15, [x0, #96]
	139	ldr x16, [x0, #112]
	140	msr tpidr_el0, x2
	141	msr tpidrro_el0, x3
	142	msr contextidr_el1, x4
	143	msr mair_el1, x5
	144	msr cpacr_el1, x6
	145	msr ttbr0_el1, x1
	146	msr ttbr1_el1, x7
147	msr tcr_el1, x8
148	msr vbar_el1, x9
149	msr mdscr_el1, x10
150	msr elr_el1, x13
151	msr spsr_el1, x14
152	#if 0
153	msr S3_1_C15_C2_0, x15 /* cpuactlr */
154	msr S3_1_C15_C2_1, x16 /* cpuectlr */
155	#endif
156	/*
157	* Restore oslsr_el1 by writing oslar_el1
158	*/
159	ubfx x11, x11, #1, #1
160	msr oslar_el1, x11
161	mov x0, x12
162	dsb nsh // Make sure local tlb invalidation completed
163	isb
164	ret
165	ENDPROC(cpu_do_resume)
166	#endif
167
9cce7a43	168	/*
6fa3eb70	169	* cpu_do_switch_mm(pgd_phys, tsk)
9cce7a43 CM	170	*
	171	* Set the translation table base pointer to be pgd_phys.
	172	*
	173	* - pgd_phys - physical address of new TTB
	174	*/
	175	ENTRY(cpu_do_switch_mm)
	176	mmid w1, x1 // get mm->context.id
	177	bfi x0, x1, #48, #16 // set the ASID
	178	msr ttbr0_el1, x0 // set TTBR0
	179	isb
	180	ret
	181	ENDPROC(cpu_do_switch_mm)
	182
9cce7a43 CM	183	.section ".text.init", #alloc, #execinstr
	184
	185	/*
	186	* __cpu_setup
	187	*
	188	* Initialise the processor for turning the MMU on. Return in x0 the
	189	* value of the SCTLR_EL1 register.
	190	*/
	191	ENTRY(__cpu_setup)
9cce7a43 CM	192	/*
	193	* Preserve the link register across the function call.
	194	*/
	195	mov x28, lr
	196	bl __flush_dcache_all
	197	mov lr, x28
	198	ic iallu // I+BTB cache invalidate
6fa3eb70	199	tlbi vmalle1is // invalidate I + D TLBs
9cce7a43 CM	200	dsb sy
	201
	202	mov x0, #3 << 20
	203	msr cpacr_el1, x0 // Enable FP/ASIMD
9c413e25	204	msr mdscr_el1, xzr // Reset mdscr_el1
9cce7a43 CM	205	/*
	206	* Memory region attributes for LPAE:
	207	*
	208	* n = AttrIndx[2:0]
	209	* n MAIR
	210	* DEVICE_nGnRnE 000 00000000
	211	* DEVICE_nGnRE 001 00000100
	212	* DEVICE_GRE 010 00001100
	213	* NORMAL_NC 011 01000100
	214	* NORMAL 100 11111111
	215	*/
	216	ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) \| \
	217	MAIR(0x04, MT_DEVICE_nGnRE) \| \
	218	MAIR(0x0c, MT_DEVICE_GRE) \| \
	219	MAIR(0x44, MT_NORMAL_NC) \| \
	220	MAIR(0xff, MT_NORMAL)
	221	msr mair_el1, x5
	222	/*
	223	* Prepare SCTLR
	224	*/
	225	adr x5, crval
	226	ldp w5, w6, [x5]
	227	mrs x0, sctlr_el1
	228	bic x0, x0, x5 // clear bits
	229	orr x0, x0, x6 // set bits
	230	/*
	231	* Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
	232	* both user and kernel.
	233	*/
	234	ldr x10, =TCR_TxSZ(VA_BITS) \| TCR_FLAGS \| TCR_IPS_40BIT \| \
6fa3eb70	235	TCR_ASID16 \| TCR_TBI0 \| (1 << 31)
9cce7a43 CM	236	#ifdef CONFIG_ARM64_64K_PAGES
	237	orr x10, x10, TCR_TG0_64K
	238	orr x10, x10, TCR_TG1_64K
	239	#endif
	240	msr tcr_el1, x10
	241	ret // return to head.S
	242	ENDPROC(__cpu_setup)
	243
6fa3eb70 S	244	#ifdef CONFIG_ARMV7_COMPAT
	245	/*
	246	* n n T
	247	* U E WT T UD US IHBS
	248	* CE0 XWHW CZ ME TEEA S
	249	* .... .IEE .... NEAI TE.I ..AD DEN0 ACAM
	250	* 0011 0... 1101 ..0. ..0. 10.. .... .... < hardware reserved
	251	* .... .100 .... 01.1 11.1 ..01 0011 1101 < software settings
	252	*/
	253	.type crval, #object
	254	crval:
	255	.word 0x030802e2 // clear
	256	.word 0x0405d03d // set
	257	#else
9cce7a43 CM	258	/*
	259	* n n T
	260	* U E WT T UD US IHBS
	261	* CE0 XWHW CZ ME TEEA S
	262	* .... .IEE .... NEAI TE.I ..AD DEN0 ACAM
	263	* 0011 0... 1101 ..0. ..0. 10.. .... .... < hardware reserved
	264	* .... .100 .... 01.1 11.1 ..01 0001 1101 < software settings
	265	*/
	266	.type crval, #object
	267	crval:
	268	.word 0x030802e2 // clear
	269	.word 0x0405d11d // set
6fa3eb70	270	#endif