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60ffc30d CM |
1 | /* |
2 | * Low-level exception handling code | |
3 | * | |
4 | * Copyright (C) 2012 ARM Ltd. | |
5 | * Authors: Catalin Marinas <catalin.marinas@arm.com> | |
6 | * Will Deacon <will.deacon@arm.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
21 | #include <linux/init.h> | |
22 | #include <linux/linkage.h> | |
23 | ||
8d883b23 | 24 | #include <asm/alternative.h> |
60ffc30d CM |
25 | #include <asm/assembler.h> |
26 | #include <asm/asm-offsets.h> | |
905e8c5d | 27 | #include <asm/cpufeature.h> |
60ffc30d | 28 | #include <asm/errno.h> |
5c1ce6f7 | 29 | #include <asm/esr.h> |
d8c228e9 | 30 | #include <asm/irq.h> |
4caec816 | 31 | #include <asm/memory.h> |
6fdb633b | 32 | #include <asm/mmu.h> |
02ef7a8c | 33 | #include <asm/ptrace.h> |
60ffc30d | 34 | #include <asm/thread_info.h> |
02ef7a8c | 35 | #include <asm/uaccess.h> |
3ccf6956 | 36 | #include <asm/asm-uaccess.h> |
60ffc30d CM |
37 | #include <asm/unistd.h> |
38 | ||
6c81fe79 LB |
39 | /* |
40 | * Context tracking subsystem. Used to instrument transitions | |
41 | * between user and kernel mode. | |
42 | */ | |
43 | .macro ct_user_exit, syscall = 0 | |
44 | #ifdef CONFIG_CONTEXT_TRACKING | |
45 | bl context_tracking_user_exit | |
46 | .if \syscall == 1 | |
47 | /* | |
48 | * Save/restore needed during syscalls. Restore syscall arguments from | |
49 | * the values already saved on stack during kernel_entry. | |
50 | */ | |
51 | ldp x0, x1, [sp] | |
52 | ldp x2, x3, [sp, #S_X2] | |
53 | ldp x4, x5, [sp, #S_X4] | |
54 | ldp x6, x7, [sp, #S_X6] | |
55 | .endif | |
56 | #endif | |
57 | .endm | |
58 | ||
59 | .macro ct_user_enter | |
60 | #ifdef CONFIG_CONTEXT_TRACKING | |
61 | bl context_tracking_user_enter | |
62 | #endif | |
63 | .endm | |
64 | ||
60ffc30d CM |
65 | /* |
66 | * Bad Abort numbers | |
67 | *----------------- | |
68 | */ | |
69 | #define BAD_SYNC 0 | |
70 | #define BAD_IRQ 1 | |
71 | #define BAD_FIQ 2 | |
72 | #define BAD_ERROR 3 | |
73 | ||
3dcb8467 | 74 | .macro kernel_ventry, el, label, regsize = 64 |
7f436e6b | 75 | .align 7 |
75f5a2df | 76 | #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 |
472e9506 | 77 | alternative_if ARM64_UNMAP_KERNEL_AT_EL0 |
75f5a2df WD |
78 | .if \el == 0 |
79 | .if \regsize == 64 | |
80 | mrs x30, tpidrro_el0 | |
81 | msr tpidrro_el0, xzr | |
82 | .else | |
83 | mov x30, xzr | |
84 | .endif | |
85 | .endif | |
472e9506 | 86 | alternative_else_nop_endif |
75f5a2df WD |
87 | #endif |
88 | ||
63648dd2 | 89 | sub sp, sp, #S_FRAME_SIZE |
3dcb8467 | 90 | b el\()\el\()_\label |
7f436e6b MR |
91 | .endm |
92 | ||
75f5a2df WD |
93 | .macro tramp_alias, dst, sym |
94 | mov_q \dst, TRAMP_VALIAS | |
95 | add \dst, \dst, #(\sym - .entry.tramp.text) | |
96 | .endm | |
97 | ||
7f436e6b | 98 | .macro kernel_entry, el, regsize = 64 |
60ffc30d CM |
99 | .if \regsize == 32 |
100 | mov w0, w0 // zero upper 32 bits of x0 | |
101 | .endif | |
63648dd2 WD |
102 | stp x0, x1, [sp, #16 * 0] |
103 | stp x2, x3, [sp, #16 * 1] | |
104 | stp x4, x5, [sp, #16 * 2] | |
105 | stp x6, x7, [sp, #16 * 3] | |
106 | stp x8, x9, [sp, #16 * 4] | |
107 | stp x10, x11, [sp, #16 * 5] | |
108 | stp x12, x13, [sp, #16 * 6] | |
109 | stp x14, x15, [sp, #16 * 7] | |
110 | stp x16, x17, [sp, #16 * 8] | |
111 | stp x18, x19, [sp, #16 * 9] | |
112 | stp x20, x21, [sp, #16 * 10] | |
113 | stp x22, x23, [sp, #16 * 11] | |
114 | stp x24, x25, [sp, #16 * 12] | |
115 | stp x26, x27, [sp, #16 * 13] | |
116 | stp x28, x29, [sp, #16 * 14] | |
117 | ||
60ffc30d CM |
118 | .if \el == 0 |
119 | mrs x21, sp_el0 | |
4ca3c2cf MR |
120 | #ifdef CONFIG_THREAD_INFO_IN_TASK |
121 | ldr_this_cpu tsk, __entry_task, x20 // Ensure MDSCR_EL1.SS is clear, | |
122 | ldr x19, [tsk, #TSK_TI_FLAGS] // since we can unmask debug | |
123 | #else | |
b7547d55 JL |
124 | mov tsk, sp |
125 | and tsk, tsk, #~(THREAD_SIZE - 1) // Ensure MDSCR_EL1.SS is clear, | |
2a283070 | 126 | ldr x19, [tsk, #TI_FLAGS] // since we can unmask debug |
4ca3c2cf | 127 | #endif |
2a283070 | 128 | disable_step_tsk x19, x20 // exceptions when scheduling. |
6674ba57 JM |
129 | |
130 | mov x29, xzr // fp pointed to user-space | |
60ffc30d CM |
131 | .else |
132 | add x21, sp, #S_FRAME_SIZE | |
4caec816 JM |
133 | get_thread_info tsk |
134 | /* Save the task's original addr_limit and set USER_DS (TASK_SIZE_64) */ | |
4ca3c2cf MR |
135 | #ifdef CONFIG_THREAD_INFO_IN_TASK |
136 | ldr x20, [tsk, #TSK_TI_ADDR_LIMIT] | |
137 | #else | |
4caec816 | 138 | ldr x20, [tsk, #TI_ADDR_LIMIT] |
4ca3c2cf | 139 | #endif |
4caec816 JM |
140 | str x20, [sp, #S_ORIG_ADDR_LIMIT] |
141 | mov x20, #TASK_SIZE_64 | |
4ca3c2cf MR |
142 | #ifdef CONFIG_THREAD_INFO_IN_TASK |
143 | str x20, [tsk, #TSK_TI_ADDR_LIMIT] | |
144 | #else | |
4caec816 | 145 | str x20, [tsk, #TI_ADDR_LIMIT] |
4ca3c2cf | 146 | #endif |
4caec816 JM |
147 | ALTERNATIVE(nop, SET_PSTATE_UAO(0), ARM64_HAS_UAO, CONFIG_ARM64_UAO) |
148 | .endif /* \el == 0 */ | |
60ffc30d CM |
149 | mrs x22, elr_el1 |
150 | mrs x23, spsr_el1 | |
151 | stp lr, x21, [sp, #S_LR] | |
02ef7a8c CM |
152 | |
153 | #ifdef CONFIG_ARM64_SW_TTBR0_PAN | |
154 | /* | |
155 | * Set the TTBR0 PAN bit in SPSR. When the exception is taken from | |
156 | * EL0, there is no need to check the state of TTBR0_EL1 since | |
157 | * accesses are always enabled. | |
158 | * Note that the meaning of this bit differs from the ARMv8.1 PAN | |
159 | * feature as all TTBR0_EL1 accesses are disabled, not just those to | |
160 | * user mappings. | |
161 | */ | |
162 | alternative_if ARM64_HAS_PAN | |
163 | b 1f // skip TTBR0 PAN | |
164 | alternative_else_nop_endif | |
165 | ||
166 | .if \el != 0 | |
d99c809e | 167 | mrs x21, ttbr1_el1 |
c62a3d7a | 168 | tst x21, #TTBR_ASID_MASK // Check for the reserved ASID |
02ef7a8c CM |
169 | orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR |
170 | b.eq 1f // TTBR0 access already disabled | |
171 | and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR | |
172 | .endif | |
173 | ||
174 | __uaccess_ttbr0_disable x21 | |
175 | 1: | |
176 | #endif | |
177 | ||
60ffc30d CM |
178 | stp x22, x23, [sp, #S_PC] |
179 | ||
180 | /* | |
181 | * Set syscallno to -1 by default (overridden later if real syscall). | |
182 | */ | |
183 | .if \el == 0 | |
184 | mvn x21, xzr | |
185 | str x21, [sp, #S_SYSCALLNO] | |
186 | .endif | |
187 | ||
b7547d55 JL |
188 | /* |
189 | * Set sp_el0 to current thread_info. | |
190 | */ | |
191 | .if \el == 0 | |
192 | msr sp_el0, tsk | |
193 | .endif | |
194 | ||
60ffc30d CM |
195 | /* |
196 | * Registers that may be useful after this macro is invoked: | |
197 | * | |
198 | * x21 - aborted SP | |
199 | * x22 - aborted PC | |
200 | * x23 - aborted PSTATE | |
201 | */ | |
202 | .endm | |
203 | ||
412fcb6c | 204 | .macro kernel_exit, el |
4caec816 JM |
205 | .if \el != 0 |
206 | /* Restore the task's original addr_limit. */ | |
207 | ldr x20, [sp, #S_ORIG_ADDR_LIMIT] | |
4ca3c2cf MR |
208 | #ifdef CONFIG_THREAD_INFO_IN_TASK |
209 | str x20, [tsk, #TSK_TI_ADDR_LIMIT] | |
210 | #else | |
4caec816 | 211 | str x20, [tsk, #TI_ADDR_LIMIT] |
4ca3c2cf | 212 | #endif |
4caec816 JM |
213 | |
214 | /* No need to restore UAO, it will be restored from SPSR_EL1 */ | |
215 | .endif | |
216 | ||
60ffc30d CM |
217 | ldp x21, x22, [sp, #S_PC] // load ELR, SPSR |
218 | .if \el == 0 | |
6c81fe79 | 219 | ct_user_enter |
02ef7a8c CM |
220 | .endif |
221 | ||
222 | #ifdef CONFIG_ARM64_SW_TTBR0_PAN | |
223 | /* | |
224 | * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR | |
225 | * PAN bit checking. | |
226 | */ | |
227 | alternative_if ARM64_HAS_PAN | |
228 | b 2f // skip TTBR0 PAN | |
229 | alternative_else_nop_endif | |
230 | ||
231 | .if \el != 0 | |
232 | tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set | |
233 | .endif | |
234 | ||
d99c809e | 235 | __uaccess_ttbr0_enable x0, x1 |
02ef7a8c CM |
236 | |
237 | .if \el == 0 | |
238 | /* | |
239 | * Enable errata workarounds only if returning to user. The only | |
240 | * workaround currently required for TTBR0_EL1 changes are for the | |
241 | * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache | |
242 | * corruption). | |
243 | */ | |
244 | post_ttbr0_update_workaround | |
245 | .endif | |
246 | 1: | |
247 | .if \el != 0 | |
248 | and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit | |
249 | .endif | |
250 | 2: | |
251 | #endif | |
252 | ||
253 | .if \el == 0 | |
60ffc30d | 254 | ldr x23, [sp, #S_SP] // load return stack pointer |
63648dd2 | 255 | msr sp_el0, x23 |
75f5a2df WD |
256 | tst x22, #PSR_MODE32_BIT // native task? |
257 | b.eq 3f | |
258 | ||
905e8c5d | 259 | #ifdef CONFIG_ARM64_ERRATUM_845719 |
75f5a2df | 260 | alternative_if ARM64_WORKAROUND_845719 |
e28cabf1 DT |
261 | #ifdef CONFIG_PID_IN_CONTEXTIDR |
262 | mrs x29, contextidr_el1 | |
263 | msr contextidr_el1, x29 | |
905e8c5d | 264 | #else |
e28cabf1 | 265 | msr contextidr_el1, xzr |
905e8c5d | 266 | #endif |
75f5a2df | 267 | alternative_else_nop_endif |
905e8c5d | 268 | #endif |
75f5a2df | 269 | 3: |
60ffc30d | 270 | .endif |
02ef7a8c | 271 | |
63648dd2 WD |
272 | msr elr_el1, x21 // set up the return data |
273 | msr spsr_el1, x22 | |
63648dd2 | 274 | ldp x0, x1, [sp, #16 * 0] |
63648dd2 WD |
275 | ldp x2, x3, [sp, #16 * 1] |
276 | ldp x4, x5, [sp, #16 * 2] | |
277 | ldp x6, x7, [sp, #16 * 3] | |
278 | ldp x8, x9, [sp, #16 * 4] | |
279 | ldp x10, x11, [sp, #16 * 5] | |
280 | ldp x12, x13, [sp, #16 * 6] | |
281 | ldp x14, x15, [sp, #16 * 7] | |
282 | ldp x16, x17, [sp, #16 * 8] | |
283 | ldp x18, x19, [sp, #16 * 9] | |
284 | ldp x20, x21, [sp, #16 * 10] | |
285 | ldp x22, x23, [sp, #16 * 11] | |
286 | ldp x24, x25, [sp, #16 * 12] | |
287 | ldp x26, x27, [sp, #16 * 13] | |
288 | ldp x28, x29, [sp, #16 * 14] | |
289 | ldr lr, [sp, #S_LR] | |
290 | add sp, sp, #S_FRAME_SIZE // restore sp | |
75f5a2df | 291 | |
75f5a2df | 292 | .if \el == 0 |
472e9506 WD |
293 | alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0 |
294 | #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 | |
75f5a2df WD |
295 | bne 4f |
296 | msr far_el1, x30 | |
297 | tramp_alias x30, tramp_exit_native | |
298 | br x30 | |
299 | 4: | |
300 | tramp_alias x30, tramp_exit_compat | |
301 | br x30 | |
472e9506 | 302 | #endif |
75f5a2df WD |
303 | .else |
304 | eret | |
305 | .endif | |
60ffc30d CM |
306 | .endm |
307 | ||
41b7e19e | 308 | .macro irq_stack_entry |
d8c228e9 JM |
309 | mov x19, sp // preserve the original sp |
310 | ||
d8c228e9 | 311 | /* |
4ca3c2cf MR |
312 | * Compare sp with the base of the task stack. |
313 | * If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack, | |
314 | * and should switch to the irq stack. | |
d8c228e9 | 315 | */ |
4ca3c2cf MR |
316 | #ifdef CONFIG_THREAD_INFO_IN_TASK |
317 | ldr x25, [tsk, TSK_STACK] | |
318 | eor x25, x25, x19 | |
319 | and x25, x25, #~(THREAD_SIZE - 1) | |
320 | cbnz x25, 9998f | |
321 | #else | |
0c6cdfec JM |
322 | and x25, x19, #~(THREAD_SIZE - 1) |
323 | cmp x25, tsk | |
324 | b.ne 9998f | |
4ca3c2cf | 325 | #endif |
d8c228e9 | 326 | |
1cdfc007 | 327 | adr_this_cpu x25, irq_stack, x26 |
d8c228e9 JM |
328 | mov x26, #IRQ_STACK_START_SP |
329 | add x26, x25, x26 | |
0c6cdfec JM |
330 | |
331 | /* switch to the irq stack */ | |
d8c228e9 JM |
332 | mov sp, x26 |
333 | ||
41b7e19e JM |
334 | /* |
335 | * Add a dummy stack frame, this non-standard format is fixed up | |
336 | * by unwind_frame() | |
337 | */ | |
338 | stp x29, x19, [sp, #-16]! | |
d8c228e9 | 339 | mov x29, sp |
d8c228e9 JM |
340 | |
341 | 9998: | |
342 | .endm | |
343 | ||
344 | /* | |
345 | * x19 should be preserved between irq_stack_entry and | |
346 | * irq_stack_exit. | |
347 | */ | |
348 | .macro irq_stack_exit | |
349 | mov sp, x19 | |
350 | .endm | |
351 | ||
60ffc30d CM |
352 | /* |
353 | * These are the registers used in the syscall handler, and allow us to | |
354 | * have in theory up to 7 arguments to a function - x0 to x6. | |
355 | * | |
356 | * x7 is reserved for the system call number in 32-bit mode. | |
357 | */ | |
358 | sc_nr .req x25 // number of system calls | |
359 | scno .req x26 // syscall number | |
360 | stbl .req x27 // syscall table pointer | |
361 | tsk .req x28 // current thread_info | |
362 | ||
363 | /* | |
364 | * Interrupt handling. | |
365 | */ | |
366 | .macro irq_handler | |
d8c228e9 | 367 | ldr_l x1, handle_arch_irq |
60ffc30d | 368 | mov x0, sp |
41b7e19e | 369 | irq_stack_entry |
60ffc30d | 370 | blr x1 |
d8c228e9 | 371 | irq_stack_exit |
60ffc30d CM |
372 | .endm |
373 | ||
374 | .text | |
375 | ||
376 | /* | |
377 | * Exception vectors. | |
378 | */ | |
60ffc30d CM |
379 | |
380 | .align 11 | |
381 | ENTRY(vectors) | |
3dcb8467 WD |
382 | kernel_ventry 1, sync_invalid // Synchronous EL1t |
383 | kernel_ventry 1, irq_invalid // IRQ EL1t | |
384 | kernel_ventry 1, fiq_invalid // FIQ EL1t | |
385 | kernel_ventry 1, error_invalid // Error EL1t | |
60ffc30d | 386 | |
3dcb8467 WD |
387 | kernel_ventry 1, sync // Synchronous EL1h |
388 | kernel_ventry 1, irq // IRQ EL1h | |
389 | kernel_ventry 1, fiq_invalid // FIQ EL1h | |
390 | kernel_ventry 1, error_invalid // Error EL1h | |
60ffc30d | 391 | |
3dcb8467 WD |
392 | kernel_ventry 0, sync // Synchronous 64-bit EL0 |
393 | kernel_ventry 0, irq // IRQ 64-bit EL0 | |
394 | kernel_ventry 0, fiq_invalid // FIQ 64-bit EL0 | |
395 | kernel_ventry 0, error_invalid // Error 64-bit EL0 | |
60ffc30d CM |
396 | |
397 | #ifdef CONFIG_COMPAT | |
3dcb8467 WD |
398 | kernel_ventry 0, sync_compat, 32 // Synchronous 32-bit EL0 |
399 | kernel_ventry 0, irq_compat, 32 // IRQ 32-bit EL0 | |
400 | kernel_ventry 0, fiq_invalid_compat, 32 // FIQ 32-bit EL0 | |
401 | kernel_ventry 0, error_invalid_compat, 32 // Error 32-bit EL0 | |
60ffc30d | 402 | #else |
3dcb8467 WD |
403 | kernel_ventry 0, sync_invalid, 32 // Synchronous 32-bit EL0 |
404 | kernel_ventry 0, irq_invalid, 32 // IRQ 32-bit EL0 | |
405 | kernel_ventry 0, fiq_invalid, 32 // FIQ 32-bit EL0 | |
406 | kernel_ventry 0, error_invalid, 32 // Error 32-bit EL0 | |
60ffc30d CM |
407 | #endif |
408 | END(vectors) | |
409 | ||
410 | /* | |
411 | * Invalid mode handlers | |
412 | */ | |
413 | .macro inv_entry, el, reason, regsize = 64 | |
b4ad81e8 | 414 | kernel_entry \el, \regsize |
60ffc30d CM |
415 | mov x0, sp |
416 | mov x1, #\reason | |
417 | mrs x2, esr_el1 | |
418 | b bad_mode | |
419 | .endm | |
420 | ||
421 | el0_sync_invalid: | |
422 | inv_entry 0, BAD_SYNC | |
423 | ENDPROC(el0_sync_invalid) | |
424 | ||
425 | el0_irq_invalid: | |
426 | inv_entry 0, BAD_IRQ | |
427 | ENDPROC(el0_irq_invalid) | |
428 | ||
429 | el0_fiq_invalid: | |
430 | inv_entry 0, BAD_FIQ | |
431 | ENDPROC(el0_fiq_invalid) | |
432 | ||
433 | el0_error_invalid: | |
434 | inv_entry 0, BAD_ERROR | |
435 | ENDPROC(el0_error_invalid) | |
436 | ||
437 | #ifdef CONFIG_COMPAT | |
438 | el0_fiq_invalid_compat: | |
439 | inv_entry 0, BAD_FIQ, 32 | |
440 | ENDPROC(el0_fiq_invalid_compat) | |
441 | ||
442 | el0_error_invalid_compat: | |
443 | inv_entry 0, BAD_ERROR, 32 | |
444 | ENDPROC(el0_error_invalid_compat) | |
445 | #endif | |
446 | ||
447 | el1_sync_invalid: | |
448 | inv_entry 1, BAD_SYNC | |
449 | ENDPROC(el1_sync_invalid) | |
450 | ||
451 | el1_irq_invalid: | |
452 | inv_entry 1, BAD_IRQ | |
453 | ENDPROC(el1_irq_invalid) | |
454 | ||
455 | el1_fiq_invalid: | |
456 | inv_entry 1, BAD_FIQ | |
457 | ENDPROC(el1_fiq_invalid) | |
458 | ||
459 | el1_error_invalid: | |
460 | inv_entry 1, BAD_ERROR | |
461 | ENDPROC(el1_error_invalid) | |
462 | ||
463 | /* | |
464 | * EL1 mode handlers. | |
465 | */ | |
466 | .align 6 | |
467 | el1_sync: | |
468 | kernel_entry 1 | |
469 | mrs x1, esr_el1 // read the syndrome register | |
aed40e01 MR |
470 | lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class |
471 | cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1 | |
60ffc30d | 472 | b.eq el1_da |
d907eb25 LA |
473 | cmp x24, #ESR_ELx_EC_IABT_CUR // instruction abort in EL1 |
474 | b.eq el1_ia | |
aed40e01 | 475 | cmp x24, #ESR_ELx_EC_SYS64 // configurable trap |
60ffc30d | 476 | b.eq el1_undef |
aed40e01 | 477 | cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception |
60ffc30d | 478 | b.eq el1_sp_pc |
aed40e01 | 479 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
60ffc30d | 480 | b.eq el1_sp_pc |
aed40e01 | 481 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL1 |
60ffc30d | 482 | b.eq el1_undef |
aed40e01 | 483 | cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1 |
60ffc30d CM |
484 | b.ge el1_dbg |
485 | b el1_inv | |
d907eb25 LA |
486 | |
487 | el1_ia: | |
488 | /* | |
489 | * Fall through to the Data abort case | |
490 | */ | |
60ffc30d CM |
491 | el1_da: |
492 | /* | |
493 | * Data abort handling | |
494 | */ | |
3ccf6956 | 495 | mrs x3, far_el1 |
2a283070 | 496 | enable_dbg |
60ffc30d CM |
497 | // re-enable interrupts if they were enabled in the aborted context |
498 | tbnz x23, #7, 1f // PSR_I_BIT | |
499 | enable_irq | |
500 | 1: | |
3ccf6956 | 501 | clear_address_tag x0, x3 |
60ffc30d CM |
502 | mov x2, sp // struct pt_regs |
503 | bl do_mem_abort | |
504 | ||
505 | // disable interrupts before pulling preserved data off the stack | |
506 | disable_irq | |
507 | kernel_exit 1 | |
508 | el1_sp_pc: | |
509 | /* | |
510 | * Stack or PC alignment exception handling | |
511 | */ | |
512 | mrs x0, far_el1 | |
2a283070 | 513 | enable_dbg |
60ffc30d CM |
514 | mov x2, sp |
515 | b do_sp_pc_abort | |
516 | el1_undef: | |
517 | /* | |
518 | * Undefined instruction | |
519 | */ | |
2a283070 | 520 | enable_dbg |
60ffc30d CM |
521 | mov x0, sp |
522 | b do_undefinstr | |
523 | el1_dbg: | |
524 | /* | |
525 | * Debug exception handling | |
526 | */ | |
aed40e01 | 527 | cmp x24, #ESR_ELx_EC_BRK64 // if BRK64 |
ee6214ce | 528 | cinc x24, x24, eq // set bit '0' |
60ffc30d CM |
529 | tbz x24, #0, el1_inv // EL1 only |
530 | mrs x0, far_el1 | |
531 | mov x2, sp // struct pt_regs | |
532 | bl do_debug_exception | |
60ffc30d CM |
533 | kernel_exit 1 |
534 | el1_inv: | |
535 | // TODO: add support for undefined instructions in kernel mode | |
2a283070 | 536 | enable_dbg |
60ffc30d | 537 | mov x0, sp |
1b42804d | 538 | mov x2, x1 |
60ffc30d | 539 | mov x1, #BAD_SYNC |
60ffc30d CM |
540 | b bad_mode |
541 | ENDPROC(el1_sync) | |
542 | ||
543 | .align 6 | |
544 | el1_irq: | |
545 | kernel_entry 1 | |
2a283070 | 546 | enable_dbg |
60ffc30d CM |
547 | #ifdef CONFIG_TRACE_IRQFLAGS |
548 | bl trace_hardirqs_off | |
549 | #endif | |
64681787 | 550 | |
60ffc30d | 551 | irq_handler |
64681787 | 552 | |
60ffc30d | 553 | #ifdef CONFIG_PREEMPT |
4ca3c2cf MR |
554 | #ifdef CONFIG_THREAD_INFO_IN_TASK |
555 | ldr w24, [tsk, #TSK_TI_PREEMPT] // get preempt count | |
556 | #else | |
883c0573 | 557 | ldr w24, [tsk, #TI_PREEMPT] // get preempt count |
4ca3c2cf | 558 | #endif |
717321fc | 559 | cbnz w24, 1f // preempt count != 0 |
4ca3c2cf MR |
560 | #ifdef CONFIG_THREAD_INFO_IN_TASK |
561 | ldr x0, [tsk, #TSK_TI_FLAGS] // get flags | |
562 | #else | |
60ffc30d | 563 | ldr x0, [tsk, #TI_FLAGS] // get flags |
4ca3c2cf | 564 | #endif |
60ffc30d CM |
565 | tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling? |
566 | bl el1_preempt | |
567 | 1: | |
568 | #endif | |
569 | #ifdef CONFIG_TRACE_IRQFLAGS | |
570 | bl trace_hardirqs_on | |
571 | #endif | |
572 | kernel_exit 1 | |
573 | ENDPROC(el1_irq) | |
574 | ||
575 | #ifdef CONFIG_PREEMPT | |
576 | el1_preempt: | |
577 | mov x24, lr | |
2a283070 | 578 | 1: bl preempt_schedule_irq // irq en/disable is done inside |
4ca3c2cf MR |
579 | #ifdef CONFIG_THREAD_INFO_IN_TASK |
580 | ldr x0, [tsk, #TSK_TI_FLAGS] // get new tasks TI_FLAGS | |
581 | #else | |
60ffc30d | 582 | ldr x0, [tsk, #TI_FLAGS] // get new tasks TI_FLAGS |
4ca3c2cf | 583 | #endif |
60ffc30d CM |
584 | tbnz x0, #TIF_NEED_RESCHED, 1b // needs rescheduling? |
585 | ret x24 | |
586 | #endif | |
587 | ||
588 | /* | |
589 | * EL0 mode handlers. | |
590 | */ | |
591 | .align 6 | |
592 | el0_sync: | |
593 | kernel_entry 0 | |
594 | mrs x25, esr_el1 // read the syndrome register | |
aed40e01 MR |
595 | lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class |
596 | cmp x24, #ESR_ELx_EC_SVC64 // SVC in 64-bit state | |
60ffc30d | 597 | b.eq el0_svc |
aed40e01 | 598 | cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0 |
60ffc30d | 599 | b.eq el0_da |
aed40e01 | 600 | cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0 |
60ffc30d | 601 | b.eq el0_ia |
aed40e01 | 602 | cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access |
60ffc30d | 603 | b.eq el0_fpsimd_acc |
aed40e01 | 604 | cmp x24, #ESR_ELx_EC_FP_EXC64 // FP/ASIMD exception |
60ffc30d | 605 | b.eq el0_fpsimd_exc |
aed40e01 | 606 | cmp x24, #ESR_ELx_EC_SYS64 // configurable trap |
60ffc30d | 607 | b.eq el0_undef |
aed40e01 | 608 | cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception |
60ffc30d | 609 | b.eq el0_sp_pc |
aed40e01 | 610 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
60ffc30d | 611 | b.eq el0_sp_pc |
aed40e01 | 612 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0 |
60ffc30d | 613 | b.eq el0_undef |
aed40e01 | 614 | cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0 |
60ffc30d CM |
615 | b.ge el0_dbg |
616 | b el0_inv | |
617 | ||
618 | #ifdef CONFIG_COMPAT | |
619 | .align 6 | |
620 | el0_sync_compat: | |
621 | kernel_entry 0, 32 | |
622 | mrs x25, esr_el1 // read the syndrome register | |
aed40e01 MR |
623 | lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class |
624 | cmp x24, #ESR_ELx_EC_SVC32 // SVC in 32-bit state | |
60ffc30d | 625 | b.eq el0_svc_compat |
aed40e01 | 626 | cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0 |
60ffc30d | 627 | b.eq el0_da |
aed40e01 | 628 | cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0 |
60ffc30d | 629 | b.eq el0_ia |
aed40e01 | 630 | cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access |
60ffc30d | 631 | b.eq el0_fpsimd_acc |
aed40e01 | 632 | cmp x24, #ESR_ELx_EC_FP_EXC32 // FP/ASIMD exception |
60ffc30d | 633 | b.eq el0_fpsimd_exc |
77f3228f MS |
634 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
635 | b.eq el0_sp_pc | |
aed40e01 | 636 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0 |
60ffc30d | 637 | b.eq el0_undef |
aed40e01 | 638 | cmp x24, #ESR_ELx_EC_CP15_32 // CP15 MRC/MCR trap |
381cc2b9 | 639 | b.eq el0_undef |
aed40e01 | 640 | cmp x24, #ESR_ELx_EC_CP15_64 // CP15 MRRC/MCRR trap |
381cc2b9 | 641 | b.eq el0_undef |
aed40e01 | 642 | cmp x24, #ESR_ELx_EC_CP14_MR // CP14 MRC/MCR trap |
381cc2b9 | 643 | b.eq el0_undef |
aed40e01 | 644 | cmp x24, #ESR_ELx_EC_CP14_LS // CP14 LDC/STC trap |
381cc2b9 | 645 | b.eq el0_undef |
aed40e01 | 646 | cmp x24, #ESR_ELx_EC_CP14_64 // CP14 MRRC/MCRR trap |
381cc2b9 | 647 | b.eq el0_undef |
aed40e01 | 648 | cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0 |
60ffc30d CM |
649 | b.ge el0_dbg |
650 | b el0_inv | |
651 | el0_svc_compat: | |
652 | /* | |
653 | * AArch32 syscall handling | |
654 | */ | |
0156411b | 655 | adrp stbl, compat_sys_call_table // load compat syscall table pointer |
60ffc30d CM |
656 | uxtw scno, w7 // syscall number in w7 (r7) |
657 | mov sc_nr, #__NR_compat_syscalls | |
658 | b el0_svc_naked | |
659 | ||
660 | .align 6 | |
661 | el0_irq_compat: | |
662 | kernel_entry 0, 32 | |
663 | b el0_irq_naked | |
664 | #endif | |
665 | ||
666 | el0_da: | |
667 | /* | |
668 | * Data abort handling | |
669 | */ | |
6ab6463a | 670 | mrs x26, far_el1 |
60ffc30d | 671 | // enable interrupts before calling the main handler |
2a283070 | 672 | enable_dbg_and_irq |
6c81fe79 | 673 | ct_user_exit |
3ccf6956 | 674 | clear_address_tag x0, x26 |
60ffc30d CM |
675 | mov x1, x25 |
676 | mov x2, sp | |
d54e81f9 WD |
677 | bl do_mem_abort |
678 | b ret_to_user | |
60ffc30d CM |
679 | el0_ia: |
680 | /* | |
681 | * Instruction abort handling | |
682 | */ | |
6ab6463a | 683 | mrs x26, far_el1 |
60ffc30d | 684 | // enable interrupts before calling the main handler |
2a283070 | 685 | enable_dbg_and_irq |
6c81fe79 | 686 | ct_user_exit |
6ab6463a | 687 | mov x0, x26 |
b8f39d90 | 688 | mov x1, x25 |
60ffc30d | 689 | mov x2, sp |
d54e81f9 WD |
690 | bl do_mem_abort |
691 | b ret_to_user | |
60ffc30d CM |
692 | el0_fpsimd_acc: |
693 | /* | |
694 | * Floating Point or Advanced SIMD access | |
695 | */ | |
2a283070 | 696 | enable_dbg |
6c81fe79 | 697 | ct_user_exit |
60ffc30d CM |
698 | mov x0, x25 |
699 | mov x1, sp | |
d54e81f9 WD |
700 | bl do_fpsimd_acc |
701 | b ret_to_user | |
60ffc30d CM |
702 | el0_fpsimd_exc: |
703 | /* | |
704 | * Floating Point or Advanced SIMD exception | |
705 | */ | |
2a283070 | 706 | enable_dbg |
6c81fe79 | 707 | ct_user_exit |
60ffc30d CM |
708 | mov x0, x25 |
709 | mov x1, sp | |
d54e81f9 WD |
710 | bl do_fpsimd_exc |
711 | b ret_to_user | |
60ffc30d CM |
712 | el0_sp_pc: |
713 | /* | |
714 | * Stack or PC alignment exception handling | |
715 | */ | |
6ab6463a | 716 | mrs x26, far_el1 |
60ffc30d | 717 | // enable interrupts before calling the main handler |
2a283070 | 718 | enable_dbg_and_irq |
46b0567c | 719 | ct_user_exit |
6ab6463a | 720 | mov x0, x26 |
60ffc30d CM |
721 | mov x1, x25 |
722 | mov x2, sp | |
d54e81f9 WD |
723 | bl do_sp_pc_abort |
724 | b ret_to_user | |
60ffc30d CM |
725 | el0_undef: |
726 | /* | |
727 | * Undefined instruction | |
728 | */ | |
2600e130 | 729 | // enable interrupts before calling the main handler |
2a283070 | 730 | enable_dbg_and_irq |
6c81fe79 | 731 | ct_user_exit |
2a283070 | 732 | mov x0, sp |
d54e81f9 WD |
733 | bl do_undefinstr |
734 | b ret_to_user | |
60ffc30d CM |
735 | el0_dbg: |
736 | /* | |
737 | * Debug exception handling | |
738 | */ | |
739 | tbnz x24, #0, el0_inv // EL0 only | |
740 | mrs x0, far_el1 | |
60ffc30d CM |
741 | mov x1, x25 |
742 | mov x2, sp | |
2a283070 WD |
743 | bl do_debug_exception |
744 | enable_dbg | |
6c81fe79 | 745 | ct_user_exit |
2a283070 | 746 | b ret_to_user |
60ffc30d | 747 | el0_inv: |
2a283070 | 748 | enable_dbg |
6c81fe79 | 749 | ct_user_exit |
60ffc30d CM |
750 | mov x0, sp |
751 | mov x1, #BAD_SYNC | |
1b42804d | 752 | mov x2, x25 |
8323d055 | 753 | bl bad_el0_sync |
d54e81f9 | 754 | b ret_to_user |
60ffc30d CM |
755 | ENDPROC(el0_sync) |
756 | ||
757 | .align 6 | |
758 | el0_irq: | |
759 | kernel_entry 0 | |
760 | el0_irq_naked: | |
60ffc30d CM |
761 | enable_dbg |
762 | #ifdef CONFIG_TRACE_IRQFLAGS | |
763 | bl trace_hardirqs_off | |
764 | #endif | |
64681787 | 765 | |
6c81fe79 | 766 | ct_user_exit |
60ffc30d | 767 | irq_handler |
64681787 | 768 | |
60ffc30d CM |
769 | #ifdef CONFIG_TRACE_IRQFLAGS |
770 | bl trace_hardirqs_on | |
771 | #endif | |
772 | b ret_to_user | |
773 | ENDPROC(el0_irq) | |
774 | ||
60ffc30d CM |
775 | /* |
776 | * Register switch for AArch64. The callee-saved registers need to be saved | |
777 | * and restored. On entry: | |
778 | * x0 = previous task_struct (must be preserved across the switch) | |
779 | * x1 = next task_struct | |
780 | * Previous and next are guaranteed not to be the same. | |
781 | * | |
782 | */ | |
783 | ENTRY(cpu_switch_to) | |
c0d3fce5 WD |
784 | mov x10, #THREAD_CPU_CONTEXT |
785 | add x8, x0, x10 | |
60ffc30d CM |
786 | mov x9, sp |
787 | stp x19, x20, [x8], #16 // store callee-saved registers | |
788 | stp x21, x22, [x8], #16 | |
789 | stp x23, x24, [x8], #16 | |
790 | stp x25, x26, [x8], #16 | |
791 | stp x27, x28, [x8], #16 | |
792 | stp x29, x9, [x8], #16 | |
793 | str lr, [x8] | |
c0d3fce5 | 794 | add x8, x1, x10 |
60ffc30d CM |
795 | ldp x19, x20, [x8], #16 // restore callee-saved registers |
796 | ldp x21, x22, [x8], #16 | |
797 | ldp x23, x24, [x8], #16 | |
798 | ldp x25, x26, [x8], #16 | |
799 | ldp x27, x28, [x8], #16 | |
800 | ldp x29, x9, [x8], #16 | |
801 | ldr lr, [x8] | |
802 | mov sp, x9 | |
4ca3c2cf MR |
803 | #ifdef CONFIG_THREAD_INFO_IN_TASK |
804 | msr sp_el0, x1 | |
805 | #else | |
b7547d55 JL |
806 | and x9, x9, #~(THREAD_SIZE - 1) |
807 | msr sp_el0, x9 | |
4ca3c2cf | 808 | #endif |
60ffc30d CM |
809 | ret |
810 | ENDPROC(cpu_switch_to) | |
811 | ||
812 | /* | |
813 | * This is the fast syscall return path. We do as little as possible here, | |
814 | * and this includes saving x0 back into the kernel stack. | |
815 | */ | |
816 | ret_fast_syscall: | |
817 | disable_irq // disable interrupts | |
412fcb6c | 818 | str x0, [sp, #S_X0] // returned x0 |
4ca3c2cf MR |
819 | #ifdef CONFIG_THREAD_INFO_IN_TASK |
820 | ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for syscall tracing | |
821 | #else | |
04d7e098 | 822 | ldr x1, [tsk, #TI_FLAGS] // re-check for syscall tracing |
4ca3c2cf | 823 | #endif |
04d7e098 JS |
824 | and x2, x1, #_TIF_SYSCALL_WORK |
825 | cbnz x2, ret_fast_syscall_trace | |
60ffc30d | 826 | and x2, x1, #_TIF_WORK_MASK |
412fcb6c | 827 | cbnz x2, work_pending |
2a283070 | 828 | enable_step_tsk x1, x2 |
412fcb6c | 829 | kernel_exit 0 |
04d7e098 JS |
830 | ret_fast_syscall_trace: |
831 | enable_irq // enable interrupts | |
412fcb6c | 832 | b __sys_trace_return_skipped // we already saved x0 |
60ffc30d CM |
833 | |
834 | /* | |
835 | * Ok, we need to do extra processing, enter the slow path. | |
836 | */ | |
60ffc30d CM |
837 | work_pending: |
838 | tbnz x1, #TIF_NEED_RESCHED, work_resched | |
005f78cd | 839 | /* TIF_SIGPENDING, TIF_NOTIFY_RESUME or TIF_FOREIGN_FPSTATE case */ |
60ffc30d | 840 | mov x0, sp // 'regs' |
6916fd08 | 841 | enable_irq // enable interrupts for do_notify_resume() |
60ffc30d CM |
842 | bl do_notify_resume |
843 | b ret_to_user | |
844 | work_resched: | |
611a16d0 CM |
845 | #ifdef CONFIG_TRACE_IRQFLAGS |
846 | bl trace_hardirqs_off // the IRQs are off here, inform the tracing code | |
847 | #endif | |
60ffc30d CM |
848 | bl schedule |
849 | ||
850 | /* | |
851 | * "slow" syscall return path. | |
852 | */ | |
59dc67b0 | 853 | ret_to_user: |
60ffc30d | 854 | disable_irq // disable interrupts |
4ca3c2cf MR |
855 | #ifdef CONFIG_THREAD_INFO_IN_TASK |
856 | ldr x1, [tsk, #TSK_TI_FLAGS] | |
857 | #else | |
60ffc30d | 858 | ldr x1, [tsk, #TI_FLAGS] |
4ca3c2cf | 859 | #endif |
60ffc30d CM |
860 | and x2, x1, #_TIF_WORK_MASK |
861 | cbnz x2, work_pending | |
2a283070 | 862 | enable_step_tsk x1, x2 |
412fcb6c | 863 | kernel_exit 0 |
60ffc30d CM |
864 | ENDPROC(ret_to_user) |
865 | ||
866 | /* | |
867 | * This is how we return from a fork. | |
868 | */ | |
869 | ENTRY(ret_from_fork) | |
870 | bl schedule_tail | |
c34501d2 CM |
871 | cbz x19, 1f // not a kernel thread |
872 | mov x0, x20 | |
873 | blr x19 | |
874 | 1: get_thread_info tsk | |
60ffc30d CM |
875 | b ret_to_user |
876 | ENDPROC(ret_from_fork) | |
877 | ||
878 | /* | |
879 | * SVC handler. | |
880 | */ | |
881 | .align 6 | |
882 | el0_svc: | |
883 | adrp stbl, sys_call_table // load syscall table pointer | |
884 | uxtw scno, w8 // syscall number in w8 | |
885 | mov sc_nr, #__NR_syscalls | |
886 | el0_svc_naked: // compat entry point | |
887 | stp x0, scno, [sp, #S_ORIG_X0] // save the original x0 and syscall number | |
2a283070 | 888 | enable_dbg_and_irq |
6c81fe79 | 889 | ct_user_exit 1 |
60ffc30d | 890 | |
4ca3c2cf MR |
891 | #ifdef CONFIG_THREAD_INFO_IN_TASK |
892 | ldr x16, [tsk, #TSK_TI_FLAGS] // check for syscall hooks | |
893 | #else | |
449f81a4 | 894 | ldr x16, [tsk, #TI_FLAGS] // check for syscall hooks |
4ca3c2cf | 895 | #endif |
449f81a4 AT |
896 | tst x16, #_TIF_SYSCALL_WORK |
897 | b.ne __sys_trace | |
60ffc30d CM |
898 | cmp scno, sc_nr // check upper syscall limit |
899 | b.hs ni_sys | |
900 | ldr x16, [stbl, scno, lsl #3] // address in the syscall table | |
d54e81f9 WD |
901 | blr x16 // call sys_* routine |
902 | b ret_fast_syscall | |
60ffc30d CM |
903 | ni_sys: |
904 | mov x0, sp | |
d54e81f9 WD |
905 | bl do_ni_syscall |
906 | b ret_fast_syscall | |
60ffc30d CM |
907 | ENDPROC(el0_svc) |
908 | ||
909 | /* | |
910 | * This is the really slow path. We're going to be doing context | |
911 | * switches, and waiting for our parent to respond. | |
912 | */ | |
913 | __sys_trace: | |
1014c81d AT |
914 | mov w0, #-1 // set default errno for |
915 | cmp scno, x0 // user-issued syscall(-1) | |
916 | b.ne 1f | |
917 | mov x0, #-ENOSYS | |
918 | str x0, [sp, #S_X0] | |
919 | 1: mov x0, sp | |
3157858f | 920 | bl syscall_trace_enter |
1014c81d AT |
921 | cmp w0, #-1 // skip the syscall? |
922 | b.eq __sys_trace_return_skipped | |
60ffc30d CM |
923 | uxtw scno, w0 // syscall number (possibly new) |
924 | mov x1, sp // pointer to regs | |
925 | cmp scno, sc_nr // check upper syscall limit | |
d54e81f9 | 926 | b.hs __ni_sys_trace |
60ffc30d CM |
927 | ldp x0, x1, [sp] // restore the syscall args |
928 | ldp x2, x3, [sp, #S_X2] | |
929 | ldp x4, x5, [sp, #S_X4] | |
930 | ldp x6, x7, [sp, #S_X6] | |
931 | ldr x16, [stbl, scno, lsl #3] // address in the syscall table | |
d54e81f9 | 932 | blr x16 // call sys_* routine |
60ffc30d CM |
933 | |
934 | __sys_trace_return: | |
1014c81d AT |
935 | str x0, [sp, #S_X0] // save returned x0 |
936 | __sys_trace_return_skipped: | |
3157858f AT |
937 | mov x0, sp |
938 | bl syscall_trace_exit | |
60ffc30d CM |
939 | b ret_to_user |
940 | ||
d54e81f9 WD |
941 | __ni_sys_trace: |
942 | mov x0, sp | |
943 | bl do_ni_syscall | |
944 | b __sys_trace_return | |
945 | ||
6fdb633b WD |
946 | #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 |
947 | /* | |
948 | * Exception vectors trampoline. | |
949 | */ | |
950 | .pushsection ".entry.tramp.text", "ax" | |
951 | ||
952 | .macro tramp_map_kernel, tmp | |
953 | mrs \tmp, ttbr1_el1 | |
954 | sub \tmp, \tmp, #(SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE) | |
955 | bic \tmp, \tmp, #USER_ASID_FLAG | |
956 | msr ttbr1_el1, \tmp | |
c6e2ad95 WD |
957 | #ifdef CONFIG_ARCH_MSM8996 |
958 | /* ASID already in \tmp[63:48] */ | |
959 | movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12) | |
960 | movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12) | |
961 | /* 2MB boundary containing the vectors, so we nobble the walk cache */ | |
962 | movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12) | |
963 | isb | |
964 | tlbi vae1, \tmp | |
965 | dsb nsh | |
966 | #endif /* CONFIG_ARCH_MSM8996 */ | |
6fdb633b WD |
967 | .endm |
968 | ||
969 | .macro tramp_unmap_kernel, tmp | |
970 | mrs \tmp, ttbr1_el1 | |
971 | add \tmp, \tmp, #(SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE) | |
972 | orr \tmp, \tmp, #USER_ASID_FLAG | |
973 | msr ttbr1_el1, \tmp | |
974 | /* | |
975 | * We avoid running the post_ttbr_update_workaround here because the | |
976 | * user and kernel ASIDs don't have conflicting mappings, so any | |
977 | * "blessing" as described in: | |
978 | * | |
979 | * http://lkml.kernel.org/r/56BB848A.6060603@caviumnetworks.com | |
980 | * | |
981 | * will not hurt correctness. Whilst this may partially defeat the | |
982 | * point of using split ASIDs in the first place, it avoids | |
983 | * the hit of invalidating the entire I-cache on every return to | |
984 | * userspace. | |
985 | */ | |
986 | .endm | |
987 | ||
988 | .macro tramp_ventry, regsize = 64 | |
989 | .align 7 | |
990 | 1: | |
991 | .if \regsize == 64 | |
992 | msr tpidrro_el0, x30 // Restored in kernel_ventry | |
993 | .endif | |
994 | tramp_map_kernel x30 | |
8a345128 WD |
995 | #ifdef CONFIG_RANDOMIZE_BASE |
996 | adr x30, tramp_vectors + PAGE_SIZE | |
997 | #ifndef CONFIG_ARCH_MSM8996 | |
998 | isb | |
999 | #endif | |
1000 | ldr x30, [x30] | |
1001 | #else | |
6fdb633b | 1002 | ldr x30, =vectors |
8a345128 | 1003 | #endif |
6fdb633b WD |
1004 | prfm plil1strm, [x30, #(1b - tramp_vectors)] |
1005 | msr vbar_el1, x30 | |
1006 | add x30, x30, #(1b - tramp_vectors) | |
1007 | isb | |
1008 | br x30 | |
1009 | .endm | |
1010 | ||
1011 | .macro tramp_exit, regsize = 64 | |
1012 | adr x30, tramp_vectors | |
1013 | msr vbar_el1, x30 | |
1014 | tramp_unmap_kernel x30 | |
1015 | .if \regsize == 64 | |
1016 | mrs x30, far_el1 | |
1017 | .endif | |
1018 | eret | |
1019 | .endm | |
1020 | ||
1021 | .align 11 | |
1022 | ENTRY(tramp_vectors) | |
1023 | .space 0x400 | |
1024 | ||
1025 | tramp_ventry | |
1026 | tramp_ventry | |
1027 | tramp_ventry | |
1028 | tramp_ventry | |
1029 | ||
1030 | tramp_ventry 32 | |
1031 | tramp_ventry 32 | |
1032 | tramp_ventry 32 | |
1033 | tramp_ventry 32 | |
1034 | END(tramp_vectors) | |
1035 | ||
1036 | ENTRY(tramp_exit_native) | |
1037 | tramp_exit | |
1038 | END(tramp_exit_native) | |
1039 | ||
1040 | ENTRY(tramp_exit_compat) | |
1041 | tramp_exit 32 | |
1042 | END(tramp_exit_compat) | |
1043 | ||
1044 | .ltorg | |
1045 | .popsection // .entry.tramp.text | |
8a345128 WD |
1046 | #ifdef CONFIG_RANDOMIZE_BASE |
1047 | .pushsection ".rodata", "a" | |
1048 | .align PAGE_SHIFT | |
1049 | .globl __entry_tramp_data_start | |
1050 | __entry_tramp_data_start: | |
1051 | .quad vectors | |
1052 | .popsection // .rodata | |
1053 | #endif /* CONFIG_RANDOMIZE_BASE */ | |
6fdb633b WD |
1054 | #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ |
1055 | ||
60ffc30d CM |
1056 | /* |
1057 | * Special system call wrappers. | |
1058 | */ | |
60ffc30d CM |
1059 | ENTRY(sys_rt_sigreturn_wrapper) |
1060 | mov x0, sp | |
1061 | b sys_rt_sigreturn | |
1062 | ENDPROC(sys_rt_sigreturn_wrapper) |