[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / arch / arm64 / boot / dts / marvell / armada-cp110-slave.dtsi

/*
 * Copyright (C) 2016 Marvell Technology Group Ltd.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPLv2 or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This library is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This library is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/*
 * Device Tree file for Marvell Armada CP110 Slave.
 */

/ {
	cp110-slave {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		interrupt-parent = <&gic>;
		ranges;

		config-space@f4000000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "simple-bus";
			interrupt-parent = <&gic>;
			ranges = <0x0 0x0 0xf4000000 0x2000000>;

			cps_rtc: rtc@284000 {
				compatible = "marvell,armada-8k-rtc";
				reg = <0x284000 0x20>, <0x284080 0x24>;
				reg-names = "rtc", "rtc-soc";
				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
			};

			cps_ethernet: ethernet@0 {
				compatible = "marvell,armada-7k-pp22";
				reg = <0x0 0x100000>, <0x129000 0xb000>;
				clocks = <&cps_syscon0 1 3>, <&cps_syscon0 1 9>, <&cps_syscon0 1 5>;
				clock-names = "pp_clk", "gop_clk", "mg_clk";
				status = "disabled";
				dma-coherent;

				cps_eth0: eth0 {
					interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
					port-id = <0>;
					gop-port-id = <0>;
					status = "disabled";
				};

				cps_eth1: eth1 {
					interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
					port-id = <1>;
					gop-port-id = <2>;
					status = "disabled";
				};

				cps_eth2: eth2 {
					interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
					port-id = <2>;
					gop-port-id = <3>;
					status = "disabled";
				};
			};

			cps_mdio: mdio@12a200 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "marvell,orion-mdio";
				reg = <0x12a200 0x10>;
			};

			cps_syscon0: system-controller@440000 {
				compatible = "marvell,cp110-system-controller0",
					     "syscon";
				reg = <0x440000 0x1000>;
				#clock-cells = <2>;
				core-clock-output-names =
					"cps-apll", "cps-ppv2-core", "cps-eip",
					"cps-core", "cps-nand-core";
				gate-clock-output-names =
					"cps-audio", "cps-communit", "cps-nand",
					"cps-ppv2", "cps-sdio", "cps-mg-domain",
					"cps-mg-core", "cps-xor1", "cps-xor0",
					"cps-gop-dp", "none", "cps-pcie_x10",
					"cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor",
					"cps-sata", "cps-sata-usb", "cps-main",
					"cps-sd-mmc-gop", "none", "none",
					"cps-slow-io", "cps-usb3h0", "cps-usb3h1",
					"cps-usb3dev", "cps-eip150", "cps-eip197";
			};

			cps_sata0: sata@540000 {
				compatible = "marvell,armada-8k-ahci",
					     "generic-ahci";
				reg = <0x540000 0x30000>;
				interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&cps_syscon0 1 15>;
				status = "disabled";
			};

			cps_usb3_0: usb3@500000 {
				compatible = "marvell,armada-8k-xhci",
					     "generic-xhci";
				reg = <0x500000 0x4000>;
				dma-coherent;
				interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&cps_syscon0 1 22>;
				status = "disabled";
			};

			cps_usb3_1: usb3@510000 {
				compatible = "marvell,armada-8k-xhci",
					     "generic-xhci";
				reg = <0x510000 0x4000>;
				dma-coherent;
				interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&cps_syscon0 1 23>;
				status = "disabled";
			};

			cps_xor0: xor@6a0000 {
				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
				reg = <0x6a0000 0x1000>,
				      <0x6b0000 0x1000>;
				dma-coherent;
				msi-parent = <&gic_v2m0>;
				clocks = <&cps_syscon0 1 8>;
			};

			cps_xor1: xor@6c0000 {
				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
				reg = <0x6c0000 0x1000>,
				      <0x6d0000 0x1000>;
				dma-coherent;
				msi-parent = <&gic_v2m0>;
				clocks = <&cps_syscon0 1 7>;
			};

			cps_spi0: spi@700600 {
				compatible = "marvell,armada-380-spi";
				reg = <0x700600 0x50>;
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				cell-index = <3>;
				clocks = <&cps_syscon0 1 21>;
				status = "disabled";
			};

			cps_spi1: spi@700680 {
				compatible = "marvell,armada-380-spi";
				reg = <0x700680 0x50>;
				#address-cells = <1>;
				#size-cells = <0>;
				cell-index = <4>;
				clocks = <&cps_syscon0 1 21>;
				status = "disabled";
			};

			cps_i2c0: i2c@701000 {
				compatible = "marvell,mv78230-i2c";
				reg = <0x701000 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&cps_syscon0 1 21>;
				status = "disabled";
			};

			cps_i2c1: i2c@701100 {
				compatible = "marvell,mv78230-i2c";
				reg = <0x701100 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&cps_syscon0 1 21>;
				status = "disabled";
			};

			cps_trng: trng@760000 {
				compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
				reg = <0x760000 0x7d>;
				interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&cps_syscon0 1 25>;
				status = "okay";
			};

			cps_crypto: crypto@800000 {
				compatible = "inside-secure,safexcel-eip197";
				reg = <0x800000 0x200000>;
				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "mem", "ring0", "ring1",
						  "ring2", "ring3", "eip";
				clocks = <&cps_syscon0 1 26>;
				status = "disabled";
			};
		};

		cps_pcie0: pcie@f4600000 {
			compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
			reg = <0 0xf4600000 0 0x10000>,
			      <0 0xfaf00000 0 0x80000>;
			reg-names = "ctrl", "config";
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;
			device_type = "pci";
			dma-coherent;
			msi-parent = <&gic_v2m0>;

			bus-range = <0 0xff>;
			ranges =
				/* downstream I/O */
				<0x81000000 0 0xfd000000 0  0xfd000000 0 0x10000
				/* non-prefetchable memory */
				0x82000000 0 0xfa000000 0  0xfa000000 0 0xf00000>;
			interrupt-map-mask = <0 0 0 0>;
			interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
			num-lanes = <1>;
			clocks = <&cps_syscon0 1 13>;
			status = "disabled";
		};

		cps_pcie1: pcie@f4620000 {
			compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
			reg = <0 0xf4620000 0 0x10000>,
			      <0 0xfbf00000 0 0x80000>;
			reg-names = "ctrl", "config";
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;
			device_type = "pci";
			dma-coherent;
			msi-parent = <&gic_v2m0>;

			bus-range = <0 0xff>;
			ranges =
				/* downstream I/O */
				<0x81000000 0 0xfd010000 0  0xfd010000 0 0x10000
				/* non-prefetchable memory */
				0x82000000 0 0xfb000000 0  0xfb000000 0 0xf00000>;
			interrupt-map-mask = <0 0 0 0>;
			interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
			interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;

			num-lanes = <1>;
			clocks = <&cps_syscon0 1 11>;
			status = "disabled";
		};

		cps_pcie2: pcie@f4640000 {
			compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
			reg = <0 0xf4640000 0 0x10000>,
			      <0 0xfcf00000 0 0x80000>;
			reg-names = "ctrl", "config";
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;
			device_type = "pci";
			dma-coherent;
			msi-parent = <&gic_v2m0>;

			bus-range = <0 0xff>;
			ranges =
				/* downstream I/O */
				<0x81000000 0 0xfd020000 0  0xfd020000 0 0x10000
				/* non-prefetchable memory */
				0x82000000 0 0xfc000000 0  0xfc000000 0 0xf00000>;
			interrupt-map-mask = <0 0 0 0>;
			interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
			interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;

			num-lanes = <1>;
			clocks = <&cps_syscon0 1 12>;
			status = "disabled";
		};
	};
};
Commit	Line	Data
4eef78a0 TP	1	/*
	2	* Copyright (C) 2016 Marvell Technology Group Ltd.
	3	*
	4	* This file is dual-licensed: you can use it either under the terms
	5	* of the GPLv2 or the X11 license, at your option. Note that this dual
	6	* licensing only applies to this file, and not this project as a
	7	* whole.
	8	*
	9	* a) This library is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of the
	12	* License, or (at your option) any later version.
	13	*
	14	* This library is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* Or, alternatively,
	20	*
	21	* b) Permission is hereby granted, free of charge, to any person
	22	* obtaining a copy of this software and associated documentation
	23	* files (the "Software"), to deal in the Software without
	24	* restriction, including without limitation the rights to use,
	25	* copy, modify, merge, publish, distribute, sublicense, and/or
	26	* sell copies of the Software, and to permit persons to whom the
	27	* Software is furnished to do so, subject to the following
	28	* conditions:
	29	*
	30	* The above copyright notice and this permission notice shall be
	31	* included in all copies or substantial portions of the Software.
	32	*
	33	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	34	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	35	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	36	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	37	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	38	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	39	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	40	* OTHER DEALINGS IN THE SOFTWARE.
	41	*/
	42
	43	/*
	44	* Device Tree file for Marvell Armada CP110 Slave.
	45	*/
	46
	47	/ {
	48	cp110-slave {
	49	#address-cells = <2>;
	50	#size-cells = <2>;
	51	compatible = "simple-bus";
	52	interrupt-parent = <&gic>;
	53	ranges;
	54
70347888	55	config-space@f4000000 {
4eef78a0 TP	56	#address-cells = <1>;
	57	#size-cells = <1>;
	58	compatible = "simple-bus";
	59	interrupt-parent = <&gic>;
	60	ranges = <0x0 0x0 0xf4000000 0x2000000>;
	61
bbedcf58 GC	62	cps_rtc: rtc@284000 {
	63	compatible = "marvell,armada-8k-rtc";
	64	reg = <0x284000 0x20>, <0x284080 0x24>;
	65	reg-names = "rtc", "rtc-soc";
	66	interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	67	};
	68
60894719 TP	69	cps_ethernet: ethernet@0 {
	70	compatible = "marvell,armada-7k-pp22";
	71	reg = <0x0 0x100000>, <0x129000 0xb000>;
	72	clocks = <&cps_syscon0 1 3>, <&cps_syscon0 1 9>, <&cps_syscon0 1 5>;
	73	clock-names = "pp_clk", "gop_clk", "mg_clk";
	74	status = "disabled";
	75	dma-coherent;
	76
	77	cps_eth0: eth0 {
	78	interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
	79	port-id = <0>;
	80	gop-port-id = <0>;
	81	status = "disabled";
	82	};
	83
	84	cps_eth1: eth1 {
	85	interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
	86	port-id = <1>;
	87	gop-port-id = <2>;
	88	status = "disabled";
	89	};
	90
	91	cps_eth2: eth2 {
	92	interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
	93	port-id = <2>;
	94	gop-port-id = <3>;
	95	status = "disabled";
	96	};
	97	};
	98
	99	cps_mdio: mdio@12a200 {
	100	#address-cells = <1>;
	101	#size-cells = <0>;
	102	compatible = "marvell,orion-mdio";
	103	reg = <0x12a200 0x10>;
	104	};
	105
4eef78a0 TP	106	cps_syscon0: system-controller@440000 {
	107	compatible = "marvell,cp110-system-controller0",
	108	"syscon";
	109	reg = <0x440000 0x1000>;
	110	#clock-cells = <2>;
	111	core-clock-output-names =
	112	"cps-apll", "cps-ppv2-core", "cps-eip",
	113	"cps-core", "cps-nand-core";
	114	gate-clock-output-names =
	115	"cps-audio", "cps-communit", "cps-nand",
	116	"cps-ppv2", "cps-sdio", "cps-mg-domain",
	117	"cps-mg-core", "cps-xor1", "cps-xor0",
	118	"cps-gop-dp", "none", "cps-pcie_x10",
	119	"cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor",
	120	"cps-sata", "cps-sata-usb", "cps-main",
d0979c07	121	"cps-sd-mmc-gop", "none", "none",
4eef78a0 TP	122	"cps-slow-io", "cps-usb3h0", "cps-usb3h1",
	123	"cps-usb3dev", "cps-eip150", "cps-eip197";
	124	};
	125
	126	cps_sata0: sata@540000 {
7292ff67 RK	127	compatible = "marvell,armada-8k-ahci",
7292ff67 RK	128	"generic-ahci";
4eef78a0 TP	129	reg = <0x540000 0x30000>;
	130	interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
	131	clocks = <&cps_syscon0 1 15>;
	132	status = "disabled";
	133	};
	134
	135	cps_usb3_0: usb3@500000 {
	136	compatible = "marvell,armada-8k-xhci",
	137	"generic-xhci";
	138	reg = <0x500000 0x4000>;
	139	dma-coherent;
	140	interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
	141	clocks = <&cps_syscon0 1 22>;
	142	status = "disabled";
	143	};
	144
	145	cps_usb3_1: usb3@510000 {
	146	compatible = "marvell,armada-8k-xhci",
	147	"generic-xhci";
	148	reg = <0x510000 0x4000>;
	149	dma-coherent;
	150	interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
	151	clocks = <&cps_syscon0 1 23>;
	152	status = "disabled";
	153	};
	154
	155	cps_xor0: xor@6a0000 {
	156	compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
	157	reg = <0x6a0000 0x1000>,
	158	<0x6b0000 0x1000>;
	159	dma-coherent;
	160	msi-parent = <&gic_v2m0>;
	161	clocks = <&cps_syscon0 1 8>;
	162	};
	163
	164	cps_xor1: xor@6c0000 {
	165	compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
	166	reg = <0x6c0000 0x1000>,
	167	<0x6d0000 0x1000>;
	168	dma-coherent;
	169	msi-parent = <&gic_v2m0>;
	170	clocks = <&cps_syscon0 1 7>;
	171	};
	172
	173	cps_spi0: spi@700600 {
	174	compatible = "marvell,armada-380-spi";
	175	reg = <0x700600 0x50>;
	176	#address-cells = <0x1>;
	177	#size-cells = <0x0>;
8d897006	178	cell-index = <3>;
2ec27be3	179	clocks = <&cps_syscon0 1 21>;
4eef78a0 TP	180	status = "disabled";
	181	};
	182
	183	cps_spi1: spi@700680 {
	184	compatible = "marvell,armada-380-spi";
	185	reg = <0x700680 0x50>;
	186	#address-cells = <1>;
	187	#size-cells = <0>;
8d897006	188	cell-index = <4>;
4eef78a0 TP	189	clocks = <&cps_syscon0 1 21>;
	190	status = "disabled";
	191	};
	192
	193	cps_i2c0: i2c@701000 {
	194	compatible = "marvell,mv78230-i2c";
	195	reg = <0x701000 0x20>;
	196	#address-cells = <1>;
	197	#size-cells = <0>;
	198	interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
	199	clocks = <&cps_syscon0 1 21>;
	200	status = "disabled";
	201	};
	202
	203	cps_i2c1: i2c@701100 {
	204	compatible = "marvell,mv78230-i2c";
	205	reg = <0x701100 0x20>;
	206	#address-cells = <1>;
	207	#size-cells = <0>;
	208	interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
	209	clocks = <&cps_syscon0 1 21>;
	210	status = "disabled";
	211	};
a0743c15 RP	212
	213	cps_trng: trng@760000 {
	214	compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
	215	reg = <0x760000 0x7d>;
	216	interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
	217	clocks = <&cps_syscon0 1 25>;
	218	status = "okay";
	219	};
973020fd AT	220
	221	cps_crypto: crypto@800000 {
	222	compatible = "inside-secure,safexcel-eip197";
	223	reg = <0x800000 0x200000>;
44f73dc4	224	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
973020fd AT	225	<GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
	226	<GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
	227	<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
	228	<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
	229	<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>;
	230	interrupt-names = "mem", "ring0", "ring1",
	231	"ring2", "ring3", "eip";
	232	clocks = <&cps_syscon0 1 26>;
	233	status = "disabled";
	234	};
4eef78a0 TP	235	};
	236
	237	cps_pcie0: pcie@f4600000 {
	238	compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
	239	reg = <0 0xf4600000 0 0x10000>,
	240	<0 0xfaf00000 0 0x80000>;
	241	reg-names = "ctrl", "config";
	242	#address-cells = <3>;
	243	#size-cells = <2>;
	244	#interrupt-cells = <1>;
	245	device_type = "pci";
	246	dma-coherent;
93970e67	247	msi-parent = <&gic_v2m0>;
4eef78a0 TP	248
	249	bus-range = <0 0xff>;
	250	ranges =
	251	/* downstream I/O */
	252	<0x81000000 0 0xfd000000 0 0xfd000000 0 0x10000
	253	/* non-prefetchable memory */
	254	0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>;
	255	interrupt-map-mask = <0 0 0 0>;
	256	interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
	257	interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
	258	num-lanes = <1>;
	259	clocks = <&cps_syscon0 1 13>;
	260	status = "disabled";
	261	};
	262
	263	cps_pcie1: pcie@f4620000 {
	264	compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
	265	reg = <0 0xf4620000 0 0x10000>,
	266	<0 0xfbf00000 0 0x80000>;
	267	reg-names = "ctrl", "config";
	268	#address-cells = <3>;
	269	#size-cells = <2>;
	270	#interrupt-cells = <1>;
	271	device_type = "pci";
	272	dma-coherent;
93970e67	273	msi-parent = <&gic_v2m0>;
4eef78a0 TP	274
	275	bus-range = <0 0xff>;
	276	ranges =
	277	/* downstream I/O */
	278	<0x81000000 0 0xfd010000 0 0xfd010000 0 0x10000
	279	/* non-prefetchable memory */
	280	0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>;
	281	interrupt-map-mask = <0 0 0 0>;
	282	interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
	283	interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
	284
	285	num-lanes = <1>;
	286	clocks = <&cps_syscon0 1 11>;
	287	status = "disabled";
	288	};
	289
	290	cps_pcie2: pcie@f4640000 {
	291	compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
	292	reg = <0 0xf4640000 0 0x10000>,
	293	<0 0xfcf00000 0 0x80000>;
	294	reg-names = "ctrl", "config";
	295	#address-cells = <3>;
	296	#size-cells = <2>;
	297	#interrupt-cells = <1>;
	298	device_type = "pci";
	299	dma-coherent;
93970e67	300	msi-parent = <&gic_v2m0>;
4eef78a0 TP	301
	302	bus-range = <0 0xff>;
	303	ranges =
	304	/* downstream I/O */
	305	<0x81000000 0 0xfd020000 0 0xfd020000 0 0x10000
	306	/* non-prefetchable memory */
	307	0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>;
	308	interrupt-map-mask = <0 0 0 0>;
	309	interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
	310	interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
	311
	312	num-lanes = <1>;
	313	clocks = <&cps_syscon0 1 12>;
	314	status = "disabled";
	315	};
	316	};
	317	};