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1 | /* linux/arch/arm/plat-s3c24xx/pm.c |
2 | * | |
3 | * Copyright (c) 2004,2006 Simtec Electronics | |
4 | * Ben Dooks <ben@simtec.co.uk> | |
5 | * | |
6 | * S3C24XX Power Manager (Suspend-To-RAM) support | |
7 | * | |
8 | * See Documentation/arm/Samsung-S3C24XX/Suspend.txt for more information | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
24 | * Parts based on arch/arm/mach-pxa/pm.c | |
25 | * | |
26 | * Thanks to Dimitry Andric for debugging | |
27 | */ | |
28 | ||
29 | #include <linux/init.h> | |
30 | #include <linux/suspend.h> | |
31 | #include <linux/errno.h> | |
32 | #include <linux/time.h> | |
33 | #include <linux/interrupt.h> | |
34 | #include <linux/crc32.h> | |
35 | #include <linux/ioport.h> | |
36 | #include <linux/delay.h> | |
37 | #include <linux/serial_core.h> | |
fced80c7 | 38 | #include <linux/io.h> |
a21765a7 BD |
39 | |
40 | #include <asm/cacheflush.h> | |
a09e64fb | 41 | #include <mach/hardware.h> |
a21765a7 | 42 | |
a2b7ba9c | 43 | #include <plat/regs-serial.h> |
a09e64fb RK |
44 | #include <mach/regs-clock.h> |
45 | #include <mach/regs-gpio.h> | |
46 | #include <mach/regs-mem.h> | |
47 | #include <mach/regs-irq.h> | |
a21765a7 BD |
48 | |
49 | #include <asm/mach/time.h> | |
50 | ||
a2b7ba9c | 51 | #include <plat/pm.h> |
a21765a7 BD |
52 | |
53 | /* for external use */ | |
54 | ||
55 | unsigned long s3c_pm_flags; | |
56 | ||
57 | #define PFX "s3c24xx-pm: " | |
58 | ||
59 | static struct sleep_save core_save[] = { | |
60 | SAVE_ITEM(S3C2410_LOCKTIME), | |
61 | SAVE_ITEM(S3C2410_CLKCON), | |
62 | ||
63 | /* we restore the timings here, with the proviso that the board | |
64 | * brings the system up in an slower, or equal frequency setting | |
65 | * to the original system. | |
66 | * | |
67 | * if we cannot guarantee this, then things are going to go very | |
68 | * wrong here, as we modify the refresh and both pll settings. | |
69 | */ | |
70 | ||
71 | SAVE_ITEM(S3C2410_BWSCON), | |
72 | SAVE_ITEM(S3C2410_BANKCON0), | |
73 | SAVE_ITEM(S3C2410_BANKCON1), | |
74 | SAVE_ITEM(S3C2410_BANKCON2), | |
75 | SAVE_ITEM(S3C2410_BANKCON3), | |
76 | SAVE_ITEM(S3C2410_BANKCON4), | |
77 | SAVE_ITEM(S3C2410_BANKCON5), | |
78 | ||
e425382e | 79 | #ifndef CONFIG_CPU_FREQ |
a21765a7 BD |
80 | SAVE_ITEM(S3C2410_CLKDIVN), |
81 | SAVE_ITEM(S3C2410_MPLLCON), | |
e425382e BD |
82 | SAVE_ITEM(S3C2410_REFRESH), |
83 | #endif | |
a21765a7 BD |
84 | SAVE_ITEM(S3C2410_UPLLCON), |
85 | SAVE_ITEM(S3C2410_CLKSLOW), | |
a21765a7 BD |
86 | }; |
87 | ||
62feee64 BD |
88 | static struct gpio_sleep { |
89 | void __iomem *base; | |
90 | unsigned int gpcon; | |
91 | unsigned int gpdat; | |
92 | unsigned int gpup; | |
93 | } gpio_save[] = { | |
94 | [0] = { | |
95 | .base = S3C2410_GPACON, | |
96 | }, | |
97 | [1] = { | |
98 | .base = S3C2410_GPBCON, | |
99 | }, | |
100 | [2] = { | |
101 | .base = S3C2410_GPCCON, | |
102 | }, | |
103 | [3] = { | |
104 | .base = S3C2410_GPDCON, | |
105 | }, | |
106 | [4] = { | |
107 | .base = S3C2410_GPECON, | |
108 | }, | |
109 | [5] = { | |
110 | .base = S3C2410_GPFCON, | |
111 | }, | |
112 | [6] = { | |
113 | .base = S3C2410_GPGCON, | |
114 | }, | |
115 | [7] = { | |
116 | .base = S3C2410_GPHCON, | |
117 | }, | |
118 | }; | |
a21765a7 | 119 | |
62feee64 | 120 | static struct sleep_save misc_save[] = { |
a21765a7 BD |
121 | SAVE_ITEM(S3C2410_DCLKCON), |
122 | }; | |
123 | ||
124 | #ifdef CONFIG_S3C2410_PM_DEBUG | |
125 | ||
126 | #define SAVE_UART(va) \ | |
127 | SAVE_ITEM((va) + S3C2410_ULCON), \ | |
128 | SAVE_ITEM((va) + S3C2410_UCON), \ | |
129 | SAVE_ITEM((va) + S3C2410_UFCON), \ | |
130 | SAVE_ITEM((va) + S3C2410_UMCON), \ | |
131 | SAVE_ITEM((va) + S3C2410_UBRDIV) | |
132 | ||
133 | static struct sleep_save uart_save[] = { | |
134 | SAVE_UART(S3C24XX_VA_UART0), | |
135 | SAVE_UART(S3C24XX_VA_UART1), | |
136 | #ifndef CONFIG_CPU_S3C2400 | |
137 | SAVE_UART(S3C24XX_VA_UART2), | |
138 | #endif | |
139 | }; | |
140 | ||
141 | /* debug | |
142 | * | |
143 | * we send the debug to printascii() to allow it to be seen if the | |
144 | * system never wakes up from the sleep | |
145 | */ | |
146 | ||
147 | extern void printascii(const char *); | |
148 | ||
149 | void pm_dbg(const char *fmt, ...) | |
150 | { | |
151 | va_list va; | |
152 | char buff[256]; | |
153 | ||
154 | va_start(va, fmt); | |
155 | vsprintf(buff, fmt, va); | |
156 | va_end(va); | |
157 | ||
158 | printascii(buff); | |
159 | } | |
160 | ||
161 | static void s3c2410_pm_debug_init(void) | |
162 | { | |
163 | unsigned long tmp = __raw_readl(S3C2410_CLKCON); | |
164 | ||
165 | /* re-start uart clocks */ | |
166 | tmp |= S3C2410_CLKCON_UART0; | |
167 | tmp |= S3C2410_CLKCON_UART1; | |
168 | tmp |= S3C2410_CLKCON_UART2; | |
169 | ||
170 | __raw_writel(tmp, S3C2410_CLKCON); | |
171 | udelay(10); | |
172 | } | |
173 | ||
174 | #define DBG(fmt...) pm_dbg(fmt) | |
175 | #else | |
176 | #define DBG(fmt...) printk(KERN_DEBUG fmt) | |
177 | ||
178 | #define s3c2410_pm_debug_init() do { } while(0) | |
179 | ||
180 | static struct sleep_save uart_save[] = {}; | |
181 | #endif | |
182 | ||
183 | #if defined(CONFIG_S3C2410_PM_CHECK) && CONFIG_S3C2410_PM_CHECK_CHUNKSIZE != 0 | |
184 | ||
185 | /* suspend checking code... | |
186 | * | |
187 | * this next area does a set of crc checks over all the installed | |
188 | * memory, so the system can verify if the resume was ok. | |
189 | * | |
190 | * CONFIG_S3C2410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC, | |
191 | * increasing it will mean that the area corrupted will be less easy to spot, | |
192 | * and reducing the size will cause the CRC save area to grow | |
193 | */ | |
194 | ||
195 | #define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024) | |
196 | ||
197 | static u32 crc_size; /* size needed for the crc block */ | |
198 | static u32 *crcs; /* allocated over suspend/resume */ | |
199 | ||
200 | typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg); | |
201 | ||
202 | /* s3c2410_pm_run_res | |
203 | * | |
204 | * go thorugh the given resource list, and look for system ram | |
205 | */ | |
206 | ||
207 | static void s3c2410_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg) | |
208 | { | |
209 | while (ptr != NULL) { | |
210 | if (ptr->child != NULL) | |
211 | s3c2410_pm_run_res(ptr->child, fn, arg); | |
212 | ||
213 | if ((ptr->flags & IORESOURCE_MEM) && | |
214 | strcmp(ptr->name, "System RAM") == 0) { | |
215 | DBG("Found system RAM at %08lx..%08lx\n", | |
216 | ptr->start, ptr->end); | |
217 | arg = (fn)(ptr, arg); | |
218 | } | |
219 | ||
220 | ptr = ptr->sibling; | |
221 | } | |
222 | } | |
223 | ||
224 | static void s3c2410_pm_run_sysram(run_fn_t fn, u32 *arg) | |
225 | { | |
226 | s3c2410_pm_run_res(&iomem_resource, fn, arg); | |
227 | } | |
228 | ||
229 | static u32 *s3c2410_pm_countram(struct resource *res, u32 *val) | |
230 | { | |
231 | u32 size = (u32)(res->end - res->start)+1; | |
232 | ||
233 | size += CHECK_CHUNKSIZE-1; | |
234 | size /= CHECK_CHUNKSIZE; | |
235 | ||
236 | DBG("Area %08lx..%08lx, %d blocks\n", res->start, res->end, size); | |
237 | ||
238 | *val += size * sizeof(u32); | |
239 | return val; | |
240 | } | |
241 | ||
242 | /* s3c2410_pm_prepare_check | |
243 | * | |
244 | * prepare the necessary information for creating the CRCs. This | |
245 | * must be done before the final save, as it will require memory | |
246 | * allocating, and thus touching bits of the kernel we do not | |
247 | * know about. | |
248 | */ | |
249 | ||
250 | static void s3c2410_pm_check_prepare(void) | |
251 | { | |
252 | crc_size = 0; | |
253 | ||
254 | s3c2410_pm_run_sysram(s3c2410_pm_countram, &crc_size); | |
255 | ||
256 | DBG("s3c2410_pm_prepare_check: %u checks needed\n", crc_size); | |
257 | ||
258 | crcs = kmalloc(crc_size+4, GFP_KERNEL); | |
259 | if (crcs == NULL) | |
260 | printk(KERN_ERR "Cannot allocated CRC save area\n"); | |
261 | } | |
262 | ||
263 | static u32 *s3c2410_pm_makecheck(struct resource *res, u32 *val) | |
264 | { | |
265 | unsigned long addr, left; | |
266 | ||
267 | for (addr = res->start; addr < res->end; | |
268 | addr += CHECK_CHUNKSIZE) { | |
269 | left = res->end - addr; | |
270 | ||
271 | if (left > CHECK_CHUNKSIZE) | |
272 | left = CHECK_CHUNKSIZE; | |
273 | ||
274 | *val = crc32_le(~0, phys_to_virt(addr), left); | |
275 | val++; | |
276 | } | |
277 | ||
278 | return val; | |
279 | } | |
280 | ||
281 | /* s3c2410_pm_check_store | |
282 | * | |
283 | * compute the CRC values for the memory blocks before the final | |
284 | * sleep. | |
285 | */ | |
286 | ||
287 | static void s3c2410_pm_check_store(void) | |
288 | { | |
289 | if (crcs != NULL) | |
290 | s3c2410_pm_run_sysram(s3c2410_pm_makecheck, crcs); | |
291 | } | |
292 | ||
293 | /* in_region | |
294 | * | |
295 | * return TRUE if the area defined by ptr..ptr+size contatins the | |
296 | * what..what+whatsz | |
297 | */ | |
298 | ||
299 | static inline int in_region(void *ptr, int size, void *what, size_t whatsz) | |
300 | { | |
301 | if ((what+whatsz) < ptr) | |
302 | return 0; | |
303 | ||
304 | if (what > (ptr+size)) | |
305 | return 0; | |
306 | ||
307 | return 1; | |
308 | } | |
309 | ||
310 | static u32 *s3c2410_pm_runcheck(struct resource *res, u32 *val) | |
311 | { | |
312 | void *save_at = phys_to_virt(s3c2410_sleep_save_phys); | |
313 | unsigned long addr; | |
314 | unsigned long left; | |
315 | void *ptr; | |
316 | u32 calc; | |
317 | ||
318 | for (addr = res->start; addr < res->end; | |
319 | addr += CHECK_CHUNKSIZE) { | |
320 | left = res->end - addr; | |
321 | ||
322 | if (left > CHECK_CHUNKSIZE) | |
323 | left = CHECK_CHUNKSIZE; | |
324 | ||
325 | ptr = phys_to_virt(addr); | |
326 | ||
327 | if (in_region(ptr, left, crcs, crc_size)) { | |
328 | DBG("skipping %08lx, has crc block in\n", addr); | |
329 | goto skip_check; | |
330 | } | |
331 | ||
332 | if (in_region(ptr, left, save_at, 32*4 )) { | |
333 | DBG("skipping %08lx, has save block in\n", addr); | |
334 | goto skip_check; | |
335 | } | |
336 | ||
337 | /* calculate and check the checksum */ | |
338 | ||
339 | calc = crc32_le(~0, ptr, left); | |
340 | if (calc != *val) { | |
341 | printk(KERN_ERR PFX "Restore CRC error at " | |
342 | "%08lx (%08x vs %08x)\n", addr, calc, *val); | |
343 | ||
344 | DBG("Restore CRC error at %08lx (%08x vs %08x)\n", | |
345 | addr, calc, *val); | |
346 | } | |
347 | ||
348 | skip_check: | |
349 | val++; | |
350 | } | |
351 | ||
352 | return val; | |
353 | } | |
354 | ||
355 | /* s3c2410_pm_check_restore | |
356 | * | |
357 | * check the CRCs after the restore event and free the memory used | |
358 | * to hold them | |
359 | */ | |
360 | ||
361 | static void s3c2410_pm_check_restore(void) | |
362 | { | |
363 | if (crcs != NULL) { | |
364 | s3c2410_pm_run_sysram(s3c2410_pm_runcheck, crcs); | |
365 | kfree(crcs); | |
366 | crcs = NULL; | |
367 | } | |
368 | } | |
369 | ||
370 | #else | |
371 | ||
372 | #define s3c2410_pm_check_prepare() do { } while(0) | |
373 | #define s3c2410_pm_check_restore() do { } while(0) | |
374 | #define s3c2410_pm_check_store() do { } while(0) | |
375 | #endif | |
376 | ||
377 | /* helper functions to save and restore register state */ | |
378 | ||
379 | void s3c2410_pm_do_save(struct sleep_save *ptr, int count) | |
380 | { | |
381 | for (; count > 0; count--, ptr++) { | |
382 | ptr->val = __raw_readl(ptr->reg); | |
383 | DBG("saved %p value %08lx\n", ptr->reg, ptr->val); | |
384 | } | |
385 | } | |
386 | ||
387 | /* s3c2410_pm_do_restore | |
388 | * | |
389 | * restore the system from the given list of saved registers | |
390 | * | |
391 | * Note, we do not use DBG() in here, as the system may not have | |
392 | * restore the UARTs state yet | |
393 | */ | |
394 | ||
395 | void s3c2410_pm_do_restore(struct sleep_save *ptr, int count) | |
396 | { | |
397 | for (; count > 0; count--, ptr++) { | |
398 | printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n", | |
399 | ptr->reg, ptr->val, __raw_readl(ptr->reg)); | |
400 | ||
401 | __raw_writel(ptr->val, ptr->reg); | |
402 | } | |
403 | } | |
404 | ||
405 | /* s3c2410_pm_do_restore_core | |
406 | * | |
407 | * similar to s3c2410_pm_do_restore_core | |
408 | * | |
409 | * WARNING: Do not put any debug in here that may effect memory or use | |
410 | * peripherals, as things may be changing! | |
411 | */ | |
412 | ||
413 | static void s3c2410_pm_do_restore_core(struct sleep_save *ptr, int count) | |
414 | { | |
415 | for (; count > 0; count--, ptr++) { | |
416 | __raw_writel(ptr->val, ptr->reg); | |
417 | } | |
418 | } | |
419 | ||
420 | /* s3c2410_pm_show_resume_irqs | |
421 | * | |
422 | * print any IRQs asserted at resume time (ie, we woke from) | |
423 | */ | |
424 | ||
425 | static void s3c2410_pm_show_resume_irqs(int start, unsigned long which, | |
426 | unsigned long mask) | |
427 | { | |
428 | int i; | |
429 | ||
430 | which &= ~mask; | |
431 | ||
432 | for (i = 0; i <= 31; i++) { | |
433 | if ((which) & (1L<<i)) { | |
434 | DBG("IRQ %d asserted at resume\n", start+i); | |
435 | } | |
436 | } | |
437 | } | |
438 | ||
439 | /* s3c2410_pm_check_resume_pin | |
440 | * | |
441 | * check to see if the pin is configured correctly for sleep mode, and | |
442 | * make any necessary adjustments if it is not | |
443 | */ | |
444 | ||
445 | static void s3c2410_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs) | |
446 | { | |
447 | unsigned long irqstate; | |
448 | unsigned long pinstate; | |
449 | int irq = s3c2410_gpio_getirq(pin); | |
450 | ||
451 | if (irqoffs < 4) | |
452 | irqstate = s3c_irqwake_intmask & (1L<<irqoffs); | |
453 | else | |
454 | irqstate = s3c_irqwake_eintmask & (1L<<irqoffs); | |
455 | ||
456 | pinstate = s3c2410_gpio_getcfg(pin); | |
457 | ||
458 | if (!irqstate) { | |
459 | if (pinstate == S3C2410_GPIO_IRQ) | |
460 | DBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin); | |
461 | } else { | |
462 | if (pinstate == S3C2410_GPIO_IRQ) { | |
463 | DBG("Disabling IRQ %d (pin %d)\n", irq, pin); | |
464 | s3c2410_gpio_cfgpin(pin, S3C2410_GPIO_INPUT); | |
465 | } | |
466 | } | |
467 | } | |
468 | ||
469 | /* s3c2410_pm_configure_extint | |
470 | * | |
471 | * configure all external interrupt pins | |
472 | */ | |
473 | ||
474 | static void s3c2410_pm_configure_extint(void) | |
475 | { | |
476 | int pin; | |
477 | ||
478 | /* for each of the external interrupts (EINT0..EINT15) we | |
479 | * need to check wether it is an external interrupt source, | |
480 | * and then configure it as an input if it is not | |
481 | */ | |
482 | ||
483 | for (pin = S3C2410_GPF0; pin <= S3C2410_GPF7; pin++) { | |
484 | s3c2410_pm_check_resume_pin(pin, pin - S3C2410_GPF0); | |
485 | } | |
486 | ||
487 | for (pin = S3C2410_GPG0; pin <= S3C2410_GPG7; pin++) { | |
488 | s3c2410_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8); | |
489 | } | |
490 | } | |
491 | ||
62feee64 BD |
492 | /* offsets for CON/DAT/UP registers */ |
493 | ||
494 | #define OFFS_CON (S3C2410_GPACON - S3C2410_GPACON) | |
495 | #define OFFS_DAT (S3C2410_GPADAT - S3C2410_GPACON) | |
496 | #define OFFS_UP (S3C2410_GPBUP - S3C2410_GPBCON) | |
497 | ||
498 | /* s3c2410_pm_save_gpios() | |
499 | * | |
500 | * Save the state of the GPIOs | |
501 | */ | |
502 | ||
503 | static void s3c2410_pm_save_gpios(void) | |
504 | { | |
505 | struct gpio_sleep *gps = gpio_save; | |
506 | unsigned int gpio; | |
507 | ||
508 | for (gpio = 0; gpio < ARRAY_SIZE(gpio_save); gpio++, gps++) { | |
509 | void __iomem *base = gps->base; | |
510 | ||
511 | gps->gpcon = __raw_readl(base + OFFS_CON); | |
512 | gps->gpdat = __raw_readl(base + OFFS_DAT); | |
513 | ||
514 | if (gpio > 0) | |
515 | gps->gpup = __raw_readl(base + OFFS_UP); | |
516 | ||
517 | } | |
518 | } | |
519 | ||
520 | /* Test whether the given masked+shifted bits of an GPIO configuration | |
521 | * are one of the SFN (special function) modes. */ | |
522 | ||
523 | static inline int is_sfn(unsigned long con) | |
524 | { | |
525 | return (con == 2 || con == 3); | |
526 | } | |
527 | ||
528 | /* Test if the given masked+shifted GPIO configuration is an input */ | |
529 | ||
530 | static inline int is_in(unsigned long con) | |
531 | { | |
532 | return con == 0; | |
533 | } | |
534 | ||
535 | /* Test if the given masked+shifted GPIO configuration is an output */ | |
536 | ||
537 | static inline int is_out(unsigned long con) | |
538 | { | |
539 | return con == 1; | |
540 | } | |
541 | ||
542 | /* s3c2410_pm_restore_gpio() | |
543 | * | |
544 | * Restore one of the GPIO banks that was saved during suspend. This is | |
545 | * not as simple as once thought, due to the possibility of glitches | |
546 | * from the order that the CON and DAT registers are set in. | |
547 | * | |
548 | * The three states the pin can be are {IN,OUT,SFN} which gives us 9 | |
549 | * combinations of changes to check. Three of these, if the pin stays | |
550 | * in the same configuration can be discounted. This leaves us with | |
551 | * the following: | |
552 | * | |
553 | * { IN => OUT } Change DAT first | |
554 | * { IN => SFN } Change CON first | |
555 | * { OUT => SFN } Change CON first, so new data will not glitch | |
556 | * { OUT => IN } Change CON first, so new data will not glitch | |
557 | * { SFN => IN } Change CON first | |
558 | * { SFN => OUT } Change DAT first, so new data will not glitch [1] | |
559 | * | |
560 | * We do not currently deal with the UP registers as these control | |
561 | * weak resistors, so a small delay in change should not need to bring | |
562 | * these into the calculations. | |
563 | * | |
564 | * [1] this assumes that writing to a pin DAT whilst in SFN will set the | |
565 | * state for when it is next output. | |
566 | */ | |
567 | ||
568 | static void s3c2410_pm_restore_gpio(int index, struct gpio_sleep *gps) | |
569 | { | |
570 | void __iomem *base = gps->base; | |
571 | unsigned long gps_gpcon = gps->gpcon; | |
572 | unsigned long gps_gpdat = gps->gpdat; | |
573 | unsigned long old_gpcon; | |
574 | unsigned long old_gpdat; | |
575 | unsigned long old_gpup = 0x0; | |
576 | unsigned long gpcon; | |
577 | int nr; | |
578 | ||
579 | old_gpcon = __raw_readl(base + OFFS_CON); | |
580 | old_gpdat = __raw_readl(base + OFFS_DAT); | |
581 | ||
582 | if (base == S3C2410_GPACON) { | |
583 | /* GPACON only has one bit per control / data and no PULLUPs. | |
584 | * GPACON[x] = 0 => Output, 1 => SFN */ | |
585 | ||
586 | /* first set all SFN bits to SFN */ | |
587 | ||
588 | gpcon = old_gpcon | gps->gpcon; | |
589 | __raw_writel(gpcon, base + OFFS_CON); | |
590 | ||
591 | /* now set all the other bits */ | |
592 | ||
593 | __raw_writel(gps_gpdat, base + OFFS_DAT); | |
594 | __raw_writel(gps_gpcon, base + OFFS_CON); | |
595 | } else { | |
596 | unsigned long old, new, mask; | |
597 | unsigned long change_mask = 0x0; | |
598 | ||
599 | old_gpup = __raw_readl(base + OFFS_UP); | |
600 | ||
601 | /* Create a change_mask of all the items that need to have | |
602 | * their CON value changed before their DAT value, so that | |
603 | * we minimise the work between the two settings. | |
604 | */ | |
605 | ||
606 | for (nr = 0, mask = 0x03; nr < 32; nr += 2, mask <<= 2) { | |
607 | old = (old_gpcon & mask) >> nr; | |
608 | new = (gps_gpcon & mask) >> nr; | |
609 | ||
610 | /* If there is no change, then skip */ | |
611 | ||
612 | if (old == new) | |
613 | continue; | |
614 | ||
615 | /* If both are special function, then skip */ | |
616 | ||
617 | if (is_sfn(old) && is_sfn(new)) | |
618 | continue; | |
619 | ||
620 | /* Change is IN => OUT, do not change now */ | |
621 | ||
622 | if (is_in(old) && is_out(new)) | |
623 | continue; | |
624 | ||
625 | /* Change is SFN => OUT, do not change now */ | |
626 | ||
627 | if (is_sfn(old) && is_out(new)) | |
628 | continue; | |
629 | ||
630 | /* We should now be at the case of IN=>SFN, | |
631 | * OUT=>SFN, OUT=>IN, SFN=>IN. */ | |
632 | ||
633 | change_mask |= mask; | |
634 | } | |
635 | ||
636 | /* Write the new CON settings */ | |
637 | ||
638 | gpcon = old_gpcon & ~change_mask; | |
639 | gpcon |= gps_gpcon & change_mask; | |
640 | ||
641 | __raw_writel(gpcon, base + OFFS_CON); | |
642 | ||
643 | /* Now change any items that require DAT,CON */ | |
644 | ||
645 | __raw_writel(gps_gpdat, base + OFFS_DAT); | |
646 | __raw_writel(gps_gpcon, base + OFFS_CON); | |
647 | __raw_writel(gps->gpup, base + OFFS_UP); | |
648 | } | |
649 | ||
650 | DBG("GPIO[%d] CON %08lx => %08lx, DAT %08lx => %08lx\n", | |
651 | index, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat); | |
652 | } | |
653 | ||
654 | ||
655 | /** s3c2410_pm_restore_gpios() | |
656 | * | |
657 | * Restore the state of the GPIOs | |
658 | */ | |
659 | ||
660 | static void s3c2410_pm_restore_gpios(void) | |
661 | { | |
662 | struct gpio_sleep *gps = gpio_save; | |
663 | int gpio; | |
664 | ||
665 | for (gpio = 0; gpio < ARRAY_SIZE(gpio_save); gpio++, gps++) { | |
666 | s3c2410_pm_restore_gpio(gpio, gps); | |
667 | } | |
668 | } | |
669 | ||
a21765a7 BD |
670 | void (*pm_cpu_prep)(void); |
671 | void (*pm_cpu_sleep)(void); | |
672 | ||
673 | #define any_allowed(mask, allow) (((mask) & (allow)) != (allow)) | |
674 | ||
675 | /* s3c2410_pm_enter | |
676 | * | |
677 | * central control for sleep/resume process | |
678 | */ | |
679 | ||
680 | static int s3c2410_pm_enter(suspend_state_t state) | |
681 | { | |
682 | unsigned long regs_save[16]; | |
683 | ||
684 | /* ensure the debug is initialised (if enabled) */ | |
685 | ||
686 | s3c2410_pm_debug_init(); | |
687 | ||
688 | DBG("s3c2410_pm_enter(%d)\n", state); | |
689 | ||
690 | if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) { | |
691 | printk(KERN_ERR PFX "error: no cpu sleep functions set\n"); | |
692 | return -EINVAL; | |
693 | } | |
694 | ||
a21765a7 BD |
695 | /* check if we have anything to wake-up with... bad things seem |
696 | * to happen if you suspend with no wakeup (system will often | |
697 | * require a full power-cycle) | |
698 | */ | |
699 | ||
700 | if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) && | |
701 | !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) { | |
702 | printk(KERN_ERR PFX "No sources enabled for wake-up!\n"); | |
703 | printk(KERN_ERR PFX "Aborting sleep\n"); | |
704 | return -EINVAL; | |
705 | } | |
706 | ||
707 | /* prepare check area if configured */ | |
708 | ||
709 | s3c2410_pm_check_prepare(); | |
710 | ||
711 | /* store the physical address of the register recovery block */ | |
712 | ||
713 | s3c2410_sleep_save_phys = virt_to_phys(regs_save); | |
714 | ||
715 | DBG("s3c2410_sleep_save_phys=0x%08lx\n", s3c2410_sleep_save_phys); | |
716 | ||
717 | /* save all necessary core registers not covered by the drivers */ | |
718 | ||
62feee64 BD |
719 | s3c2410_pm_save_gpios(); |
720 | s3c2410_pm_do_save(misc_save, ARRAY_SIZE(misc_save)); | |
a21765a7 BD |
721 | s3c2410_pm_do_save(core_save, ARRAY_SIZE(core_save)); |
722 | s3c2410_pm_do_save(uart_save, ARRAY_SIZE(uart_save)); | |
723 | ||
724 | /* set the irq configuration for wake */ | |
725 | ||
726 | s3c2410_pm_configure_extint(); | |
727 | ||
728 | DBG("sleep: irq wakeup masks: %08lx,%08lx\n", | |
729 | s3c_irqwake_intmask, s3c_irqwake_eintmask); | |
730 | ||
731 | __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK); | |
732 | __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK); | |
733 | ||
734 | /* ack any outstanding external interrupts before we go to sleep */ | |
735 | ||
736 | __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND); | |
737 | __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND); | |
738 | __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND); | |
739 | ||
6cbdc8c5 | 740 | /* call cpu specific preparation */ |
a21765a7 BD |
741 | |
742 | pm_cpu_prep(); | |
743 | ||
744 | /* flush cache back to ram */ | |
745 | ||
746 | flush_cache_all(); | |
747 | ||
748 | s3c2410_pm_check_store(); | |
749 | ||
750 | /* send the cpu to sleep... */ | |
751 | ||
752 | __raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */ | |
753 | ||
754 | /* s3c2410_cpu_save will also act as our return point from when | |
755 | * we resume as it saves its own register state, so use the return | |
756 | * code to differentiate return from save and return from sleep */ | |
757 | ||
758 | if (s3c2410_cpu_save(regs_save) == 0) { | |
759 | flush_cache_all(); | |
760 | pm_cpu_sleep(); | |
761 | } | |
762 | ||
763 | /* restore the cpu state */ | |
764 | ||
765 | cpu_init(); | |
766 | ||
767 | /* restore the system state */ | |
768 | ||
769 | s3c2410_pm_do_restore_core(core_save, ARRAY_SIZE(core_save)); | |
62feee64 | 770 | s3c2410_pm_do_restore(misc_save, ARRAY_SIZE(misc_save)); |
a21765a7 | 771 | s3c2410_pm_do_restore(uart_save, ARRAY_SIZE(uart_save)); |
62feee64 | 772 | s3c2410_pm_restore_gpios(); |
a21765a7 BD |
773 | |
774 | s3c2410_pm_debug_init(); | |
775 | ||
776 | /* check what irq (if any) restored the system */ | |
777 | ||
778 | DBG("post sleep: IRQs 0x%08x, 0x%08x\n", | |
779 | __raw_readl(S3C2410_SRCPND), | |
780 | __raw_readl(S3C2410_EINTPEND)); | |
781 | ||
782 | s3c2410_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND), | |
783 | s3c_irqwake_intmask); | |
784 | ||
785 | s3c2410_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND), | |
786 | s3c_irqwake_eintmask); | |
787 | ||
788 | DBG("post sleep, preparing to return\n"); | |
789 | ||
790 | s3c2410_pm_check_restore(); | |
791 | ||
792 | /* ok, let's return from sleep */ | |
793 | ||
794 | DBG("S3C2410 PM Resume (post-restore)\n"); | |
795 | return 0; | |
796 | } | |
797 | ||
26398a70 | 798 | static struct platform_suspend_ops s3c2410_pm_ops = { |
a21765a7 | 799 | .enter = s3c2410_pm_enter, |
26398a70 | 800 | .valid = suspend_valid_only_mem, |
a21765a7 BD |
801 | }; |
802 | ||
803 | /* s3c2410_pm_init | |
804 | * | |
805 | * Attach the power management functions. This should be called | |
806 | * from the board specific initialisation if the board supports | |
807 | * it. | |
808 | */ | |
809 | ||
810 | int __init s3c2410_pm_init(void) | |
811 | { | |
812 | printk("S3C2410 Power Management, (c) 2004 Simtec Electronics\n"); | |
813 | ||
26398a70 | 814 | suspend_set_ops(&s3c2410_pm_ops); |
a21765a7 BD |
815 | return 0; |
816 | } |