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a21765a7 BD |
1 | /* linux/arch/arm/plat-s3c24xx/dma.c |
2 | * | |
3 | * Copyright (c) 2003-2005,2006 Simtec Electronics | |
4 | * Ben Dooks <ben@simtec.co.uk> | |
5 | * | |
6 | * S3C2410 DMA core | |
7 | * | |
8 | * http://armlinux.simtec.co.uk/ | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | ||
16 | #ifdef CONFIG_S3C2410_DMA_DEBUG | |
17 | #define DEBUG | |
18 | #endif | |
19 | ||
20 | #include <linux/module.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/sched.h> | |
23 | #include <linux/spinlock.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/sysdev.h> | |
26 | #include <linux/slab.h> | |
27 | #include <linux/errno.h> | |
fced80c7 | 28 | #include <linux/io.h> |
a21765a7 BD |
29 | |
30 | #include <asm/system.h> | |
31 | #include <asm/irq.h> | |
a09e64fb | 32 | #include <mach/hardware.h> |
dcea83ad | 33 | #include <mach/dma.h> |
a21765a7 | 34 | |
a09e64fb | 35 | #include <mach/map.h> |
a21765a7 | 36 | |
d5120ae7 | 37 | #include <plat/dma.h> |
a21765a7 BD |
38 | |
39 | /* io map for dma */ | |
40 | static void __iomem *dma_base; | |
41 | static struct kmem_cache *dma_kmem; | |
42 | ||
48adbcf3 BD |
43 | static int dma_channels; |
44 | ||
a7717435 | 45 | static struct s3c24xx_dma_selection dma_sel; |
a21765a7 BD |
46 | |
47 | /* dma channel state information */ | |
48 | struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS]; | |
49 | ||
50 | /* debugging functions */ | |
51 | ||
52 | #define BUF_MAGIC (0xcafebabe) | |
53 | ||
54 | #define dmawarn(fmt...) printk(KERN_DEBUG fmt) | |
55 | ||
56 | #define dma_regaddr(chan, reg) ((chan)->regs + (reg)) | |
57 | ||
58 | #if 1 | |
59 | #define dma_wrreg(chan, reg, val) writel((val), (chan)->regs + (reg)) | |
60 | #else | |
61 | static inline void | |
62 | dma_wrreg(struct s3c2410_dma_chan *chan, int reg, unsigned long val) | |
63 | { | |
64 | pr_debug("writing %08x to register %08x\n",(unsigned int)val,reg); | |
65 | writel(val, dma_regaddr(chan, reg)); | |
66 | } | |
67 | #endif | |
68 | ||
69 | #define dma_rdreg(chan, reg) readl((chan)->regs + (reg)) | |
70 | ||
71 | /* captured register state for debug */ | |
72 | ||
73 | struct s3c2410_dma_regstate { | |
74 | unsigned long dcsrc; | |
75 | unsigned long disrc; | |
76 | unsigned long dstat; | |
77 | unsigned long dcon; | |
78 | unsigned long dmsktrig; | |
79 | }; | |
80 | ||
81 | #ifdef CONFIG_S3C2410_DMA_DEBUG | |
82 | ||
83 | /* dmadbg_showregs | |
84 | * | |
85 | * simple debug routine to print the current state of the dma registers | |
86 | */ | |
87 | ||
88 | static void | |
89 | dmadbg_capture(struct s3c2410_dma_chan *chan, struct s3c2410_dma_regstate *regs) | |
90 | { | |
91 | regs->dcsrc = dma_rdreg(chan, S3C2410_DMA_DCSRC); | |
92 | regs->disrc = dma_rdreg(chan, S3C2410_DMA_DISRC); | |
93 | regs->dstat = dma_rdreg(chan, S3C2410_DMA_DSTAT); | |
94 | regs->dcon = dma_rdreg(chan, S3C2410_DMA_DCON); | |
95 | regs->dmsktrig = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG); | |
96 | } | |
97 | ||
98 | static void | |
99 | dmadbg_dumpregs(const char *fname, int line, struct s3c2410_dma_chan *chan, | |
100 | struct s3c2410_dma_regstate *regs) | |
101 | { | |
102 | printk(KERN_DEBUG "dma%d: %s:%d: DCSRC=%08lx, DISRC=%08lx, DSTAT=%08lx DMT=%02lx, DCON=%08lx\n", | |
103 | chan->number, fname, line, | |
104 | regs->dcsrc, regs->disrc, regs->dstat, regs->dmsktrig, | |
105 | regs->dcon); | |
106 | } | |
107 | ||
108 | static void | |
109 | dmadbg_showchan(const char *fname, int line, struct s3c2410_dma_chan *chan) | |
110 | { | |
111 | struct s3c2410_dma_regstate state; | |
112 | ||
113 | dmadbg_capture(chan, &state); | |
114 | ||
115 | printk(KERN_DEBUG "dma%d: %s:%d: ls=%d, cur=%p, %p %p\n", | |
116 | chan->number, fname, line, chan->load_state, | |
117 | chan->curr, chan->next, chan->end); | |
118 | ||
119 | dmadbg_dumpregs(fname, line, chan, &state); | |
120 | } | |
121 | ||
122 | static void | |
123 | dmadbg_showregs(const char *fname, int line, struct s3c2410_dma_chan *chan) | |
124 | { | |
125 | struct s3c2410_dma_regstate state; | |
126 | ||
127 | dmadbg_capture(chan, &state); | |
128 | dmadbg_dumpregs(fname, line, chan, &state); | |
129 | } | |
130 | ||
8e86f427 HH |
131 | #define dbg_showregs(chan) dmadbg_showregs(__func__, __LINE__, (chan)) |
132 | #define dbg_showchan(chan) dmadbg_showchan(__func__, __LINE__, (chan)) | |
a21765a7 BD |
133 | #else |
134 | #define dbg_showregs(chan) do { } while(0) | |
135 | #define dbg_showchan(chan) do { } while(0) | |
136 | #endif /* CONFIG_S3C2410_DMA_DEBUG */ | |
137 | ||
138 | static struct s3c2410_dma_chan *dma_chan_map[DMACH_MAX]; | |
139 | ||
140 | /* lookup_dma_channel | |
141 | * | |
142 | * change the dma channel number given into a real dma channel id | |
143 | */ | |
144 | ||
145 | static struct s3c2410_dma_chan *lookup_dma_channel(unsigned int channel) | |
146 | { | |
147 | if (channel & DMACH_LOW_LEVEL) | |
148 | return &s3c2410_chans[channel & ~DMACH_LOW_LEVEL]; | |
149 | else | |
150 | return dma_chan_map[channel]; | |
151 | } | |
152 | ||
153 | /* s3c2410_dma_stats_timeout | |
154 | * | |
155 | * Update DMA stats from timeout info | |
156 | */ | |
157 | ||
158 | static void | |
159 | s3c2410_dma_stats_timeout(struct s3c2410_dma_stats *stats, int val) | |
160 | { | |
161 | if (stats == NULL) | |
162 | return; | |
163 | ||
164 | if (val > stats->timeout_longest) | |
165 | stats->timeout_longest = val; | |
166 | if (val < stats->timeout_shortest) | |
167 | stats->timeout_shortest = val; | |
168 | ||
169 | stats->timeout_avg += val; | |
170 | } | |
171 | ||
172 | /* s3c2410_dma_waitforload | |
173 | * | |
174 | * wait for the DMA engine to load a buffer, and update the state accordingly | |
175 | */ | |
176 | ||
177 | static int | |
178 | s3c2410_dma_waitforload(struct s3c2410_dma_chan *chan, int line) | |
179 | { | |
180 | int timeout = chan->load_timeout; | |
181 | int took; | |
182 | ||
183 | if (chan->load_state != S3C2410_DMALOAD_1LOADED) { | |
184 | printk(KERN_ERR "dma%d: s3c2410_dma_waitforload() called in loadstate %d from line %d\n", chan->number, chan->load_state, line); | |
185 | return 0; | |
186 | } | |
187 | ||
188 | if (chan->stats != NULL) | |
189 | chan->stats->loads++; | |
190 | ||
191 | while (--timeout > 0) { | |
192 | if ((dma_rdreg(chan, S3C2410_DMA_DSTAT) << (32-20)) != 0) { | |
193 | took = chan->load_timeout - timeout; | |
194 | ||
195 | s3c2410_dma_stats_timeout(chan->stats, took); | |
196 | ||
197 | switch (chan->load_state) { | |
198 | case S3C2410_DMALOAD_1LOADED: | |
199 | chan->load_state = S3C2410_DMALOAD_1RUNNING; | |
200 | break; | |
201 | ||
202 | default: | |
203 | printk(KERN_ERR "dma%d: unknown load_state in s3c2410_dma_waitforload() %d\n", chan->number, chan->load_state); | |
204 | } | |
205 | ||
206 | return 1; | |
207 | } | |
208 | } | |
209 | ||
210 | if (chan->stats != NULL) { | |
211 | chan->stats->timeout_failed++; | |
212 | } | |
213 | ||
214 | return 0; | |
215 | } | |
216 | ||
217 | ||
218 | ||
219 | /* s3c2410_dma_loadbuffer | |
220 | * | |
221 | * load a buffer, and update the channel state | |
222 | */ | |
223 | ||
224 | static inline int | |
225 | s3c2410_dma_loadbuffer(struct s3c2410_dma_chan *chan, | |
226 | struct s3c2410_dma_buf *buf) | |
227 | { | |
228 | unsigned long reload; | |
229 | ||
230 | pr_debug("s3c2410_chan_loadbuffer: loading buff %p (0x%08lx,0x%06x)\n", | |
231 | buf, (unsigned long)buf->data, buf->size); | |
232 | ||
233 | if (buf == NULL) { | |
234 | dmawarn("buffer is NULL\n"); | |
235 | return -EINVAL; | |
236 | } | |
237 | ||
238 | /* check the state of the channel before we do anything */ | |
239 | ||
240 | if (chan->load_state == S3C2410_DMALOAD_1LOADED) { | |
241 | dmawarn("load_state is S3C2410_DMALOAD_1LOADED\n"); | |
242 | } | |
243 | ||
244 | if (chan->load_state == S3C2410_DMALOAD_1LOADED_1RUNNING) { | |
245 | dmawarn("state is S3C2410_DMALOAD_1LOADED_1RUNNING\n"); | |
246 | } | |
247 | ||
248 | /* it would seem sensible if we are the last buffer to not bother | |
249 | * with the auto-reload bit, so that the DMA engine will not try | |
250 | * and load another transfer after this one has finished... | |
251 | */ | |
252 | if (chan->load_state == S3C2410_DMALOAD_NONE) { | |
253 | pr_debug("load_state is none, checking for noreload (next=%p)\n", | |
254 | buf->next); | |
255 | reload = (buf->next == NULL) ? S3C2410_DCON_NORELOAD : 0; | |
256 | } else { | |
257 | //pr_debug("load_state is %d => autoreload\n", chan->load_state); | |
258 | reload = S3C2410_DCON_AUTORELOAD; | |
259 | } | |
260 | ||
261 | if ((buf->data & 0xf0000000) != 0x30000000) { | |
262 | dmawarn("dmaload: buffer is %p\n", (void *)buf->data); | |
263 | } | |
264 | ||
265 | writel(buf->data, chan->addr_reg); | |
266 | ||
267 | dma_wrreg(chan, S3C2410_DMA_DCON, | |
268 | chan->dcon | reload | (buf->size/chan->xfer_unit)); | |
269 | ||
270 | chan->next = buf->next; | |
271 | ||
272 | /* update the state of the channel */ | |
273 | ||
274 | switch (chan->load_state) { | |
275 | case S3C2410_DMALOAD_NONE: | |
276 | chan->load_state = S3C2410_DMALOAD_1LOADED; | |
277 | break; | |
278 | ||
279 | case S3C2410_DMALOAD_1RUNNING: | |
280 | chan->load_state = S3C2410_DMALOAD_1LOADED_1RUNNING; | |
281 | break; | |
282 | ||
283 | default: | |
284 | dmawarn("dmaload: unknown state %d in loadbuffer\n", | |
285 | chan->load_state); | |
286 | break; | |
287 | } | |
288 | ||
289 | return 0; | |
290 | } | |
291 | ||
292 | /* s3c2410_dma_call_op | |
293 | * | |
294 | * small routine to call the op routine with the given op if it has been | |
295 | * registered | |
296 | */ | |
297 | ||
298 | static void | |
299 | s3c2410_dma_call_op(struct s3c2410_dma_chan *chan, enum s3c2410_chan_op op) | |
300 | { | |
301 | if (chan->op_fn != NULL) { | |
302 | (chan->op_fn)(chan, op); | |
303 | } | |
304 | } | |
305 | ||
306 | /* s3c2410_dma_buffdone | |
307 | * | |
308 | * small wrapper to check if callback routine needs to be called, and | |
309 | * if so, call it | |
310 | */ | |
311 | ||
312 | static inline void | |
313 | s3c2410_dma_buffdone(struct s3c2410_dma_chan *chan, struct s3c2410_dma_buf *buf, | |
314 | enum s3c2410_dma_buffresult result) | |
315 | { | |
316 | #if 0 | |
317 | pr_debug("callback_fn=%p, buf=%p, id=%p, size=%d, result=%d\n", | |
318 | chan->callback_fn, buf, buf->id, buf->size, result); | |
319 | #endif | |
320 | ||
321 | if (chan->callback_fn != NULL) { | |
322 | (chan->callback_fn)(chan, buf->id, buf->size, result); | |
323 | } | |
324 | } | |
325 | ||
326 | /* s3c2410_dma_start | |
327 | * | |
328 | * start a dma channel going | |
329 | */ | |
330 | ||
331 | static int s3c2410_dma_start(struct s3c2410_dma_chan *chan) | |
332 | { | |
333 | unsigned long tmp; | |
334 | unsigned long flags; | |
335 | ||
336 | pr_debug("s3c2410_start_dma: channel=%d\n", chan->number); | |
337 | ||
338 | local_irq_save(flags); | |
339 | ||
340 | if (chan->state == S3C2410_DMA_RUNNING) { | |
341 | pr_debug("s3c2410_start_dma: already running (%d)\n", chan->state); | |
342 | local_irq_restore(flags); | |
343 | return 0; | |
344 | } | |
345 | ||
346 | chan->state = S3C2410_DMA_RUNNING; | |
347 | ||
348 | /* check wether there is anything to load, and if not, see | |
349 | * if we can find anything to load | |
350 | */ | |
351 | ||
352 | if (chan->load_state == S3C2410_DMALOAD_NONE) { | |
353 | if (chan->next == NULL) { | |
354 | printk(KERN_ERR "dma%d: channel has nothing loaded\n", | |
355 | chan->number); | |
356 | chan->state = S3C2410_DMA_IDLE; | |
357 | local_irq_restore(flags); | |
358 | return -EINVAL; | |
359 | } | |
360 | ||
361 | s3c2410_dma_loadbuffer(chan, chan->next); | |
362 | } | |
363 | ||
364 | dbg_showchan(chan); | |
365 | ||
366 | /* enable the channel */ | |
367 | ||
368 | if (!chan->irq_enabled) { | |
369 | enable_irq(chan->irq); | |
370 | chan->irq_enabled = 1; | |
371 | } | |
372 | ||
373 | /* start the channel going */ | |
374 | ||
375 | tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG); | |
376 | tmp &= ~S3C2410_DMASKTRIG_STOP; | |
377 | tmp |= S3C2410_DMASKTRIG_ON; | |
378 | dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp); | |
379 | ||
380 | pr_debug("dma%d: %08lx to DMASKTRIG\n", chan->number, tmp); | |
381 | ||
382 | #if 0 | |
383 | /* the dma buffer loads should take care of clearing the AUTO | |
384 | * reloading feature */ | |
385 | tmp = dma_rdreg(chan, S3C2410_DMA_DCON); | |
386 | tmp &= ~S3C2410_DCON_NORELOAD; | |
387 | dma_wrreg(chan, S3C2410_DMA_DCON, tmp); | |
388 | #endif | |
389 | ||
390 | s3c2410_dma_call_op(chan, S3C2410_DMAOP_START); | |
391 | ||
392 | dbg_showchan(chan); | |
393 | ||
394 | /* if we've only loaded one buffer onto the channel, then chec | |
395 | * to see if we have another, and if so, try and load it so when | |
396 | * the first buffer is finished, the new one will be loaded onto | |
397 | * the channel */ | |
398 | ||
399 | if (chan->next != NULL) { | |
400 | if (chan->load_state == S3C2410_DMALOAD_1LOADED) { | |
401 | ||
402 | if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { | |
403 | pr_debug("%s: buff not yet loaded, no more todo\n", | |
8e86f427 | 404 | __func__); |
a21765a7 BD |
405 | } else { |
406 | chan->load_state = S3C2410_DMALOAD_1RUNNING; | |
407 | s3c2410_dma_loadbuffer(chan, chan->next); | |
408 | } | |
409 | ||
410 | } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) { | |
411 | s3c2410_dma_loadbuffer(chan, chan->next); | |
412 | } | |
413 | } | |
414 | ||
415 | ||
416 | local_irq_restore(flags); | |
417 | ||
418 | return 0; | |
419 | } | |
420 | ||
421 | /* s3c2410_dma_canload | |
422 | * | |
423 | * work out if we can queue another buffer into the DMA engine | |
424 | */ | |
425 | ||
426 | static int | |
427 | s3c2410_dma_canload(struct s3c2410_dma_chan *chan) | |
428 | { | |
429 | if (chan->load_state == S3C2410_DMALOAD_NONE || | |
430 | chan->load_state == S3C2410_DMALOAD_1RUNNING) | |
431 | return 1; | |
432 | ||
433 | return 0; | |
434 | } | |
435 | ||
436 | /* s3c2410_dma_enqueue | |
437 | * | |
438 | * queue an given buffer for dma transfer. | |
439 | * | |
440 | * id the device driver's id information for this buffer | |
441 | * data the physical address of the buffer data | |
442 | * size the size of the buffer in bytes | |
443 | * | |
444 | * If the channel is not running, then the flag S3C2410_DMAF_AUTOSTART | |
445 | * is checked, and if set, the channel is started. If this flag isn't set, | |
446 | * then an error will be returned. | |
447 | * | |
448 | * It is possible to queue more than one DMA buffer onto a channel at | |
449 | * once, and the code will deal with the re-loading of the next buffer | |
450 | * when necessary. | |
451 | */ | |
452 | ||
453 | int s3c2410_dma_enqueue(unsigned int channel, void *id, | |
454 | dma_addr_t data, int size) | |
455 | { | |
456 | struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); | |
457 | struct s3c2410_dma_buf *buf; | |
458 | unsigned long flags; | |
459 | ||
460 | if (chan == NULL) | |
461 | return -EINVAL; | |
462 | ||
463 | pr_debug("%s: id=%p, data=%08x, size=%d\n", | |
8e86f427 | 464 | __func__, id, (unsigned int)data, size); |
a21765a7 BD |
465 | |
466 | buf = kmem_cache_alloc(dma_kmem, GFP_ATOMIC); | |
467 | if (buf == NULL) { | |
468 | pr_debug("%s: out of memory (%ld alloc)\n", | |
8e86f427 | 469 | __func__, (long)sizeof(*buf)); |
a21765a7 BD |
470 | return -ENOMEM; |
471 | } | |
472 | ||
8e86f427 | 473 | //pr_debug("%s: new buffer %p\n", __func__, buf); |
a21765a7 BD |
474 | //dbg_showchan(chan); |
475 | ||
476 | buf->next = NULL; | |
477 | buf->data = buf->ptr = data; | |
478 | buf->size = size; | |
479 | buf->id = id; | |
480 | buf->magic = BUF_MAGIC; | |
481 | ||
482 | local_irq_save(flags); | |
483 | ||
484 | if (chan->curr == NULL) { | |
485 | /* we've got nothing loaded... */ | |
486 | pr_debug("%s: buffer %p queued onto empty channel\n", | |
8e86f427 | 487 | __func__, buf); |
a21765a7 BD |
488 | |
489 | chan->curr = buf; | |
490 | chan->end = buf; | |
491 | chan->next = NULL; | |
492 | } else { | |
493 | pr_debug("dma%d: %s: buffer %p queued onto non-empty channel\n", | |
8e86f427 | 494 | chan->number, __func__, buf); |
a21765a7 BD |
495 | |
496 | if (chan->end == NULL) | |
497 | pr_debug("dma%d: %s: %p not empty, and chan->end==NULL?\n", | |
8e86f427 | 498 | chan->number, __func__, chan); |
a21765a7 BD |
499 | |
500 | chan->end->next = buf; | |
501 | chan->end = buf; | |
502 | } | |
503 | ||
504 | /* if necessary, update the next buffer field */ | |
505 | if (chan->next == NULL) | |
506 | chan->next = buf; | |
507 | ||
508 | /* check to see if we can load a buffer */ | |
509 | if (chan->state == S3C2410_DMA_RUNNING) { | |
510 | if (chan->load_state == S3C2410_DMALOAD_1LOADED && 1) { | |
511 | if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { | |
512 | printk(KERN_ERR "dma%d: loadbuffer:" | |
513 | "timeout loading buffer\n", | |
514 | chan->number); | |
515 | dbg_showchan(chan); | |
516 | local_irq_restore(flags); | |
517 | return -EINVAL; | |
518 | } | |
519 | } | |
520 | ||
521 | while (s3c2410_dma_canload(chan) && chan->next != NULL) { | |
522 | s3c2410_dma_loadbuffer(chan, chan->next); | |
523 | } | |
524 | } else if (chan->state == S3C2410_DMA_IDLE) { | |
525 | if (chan->flags & S3C2410_DMAF_AUTOSTART) { | |
046c9d32 BD |
526 | s3c2410_dma_ctrl(chan->number | DMACH_LOW_LEVEL, |
527 | S3C2410_DMAOP_START); | |
a21765a7 BD |
528 | } |
529 | } | |
530 | ||
531 | local_irq_restore(flags); | |
532 | return 0; | |
533 | } | |
534 | ||
535 | EXPORT_SYMBOL(s3c2410_dma_enqueue); | |
536 | ||
537 | static inline void | |
538 | s3c2410_dma_freebuf(struct s3c2410_dma_buf *buf) | |
539 | { | |
540 | int magicok = (buf->magic == BUF_MAGIC); | |
541 | ||
542 | buf->magic = -1; | |
543 | ||
544 | if (magicok) { | |
545 | kmem_cache_free(dma_kmem, buf); | |
546 | } else { | |
547 | printk("s3c2410_dma_freebuf: buff %p with bad magic\n", buf); | |
548 | } | |
549 | } | |
550 | ||
551 | /* s3c2410_dma_lastxfer | |
552 | * | |
553 | * called when the system is out of buffers, to ensure that the channel | |
554 | * is prepared for shutdown. | |
555 | */ | |
556 | ||
557 | static inline void | |
558 | s3c2410_dma_lastxfer(struct s3c2410_dma_chan *chan) | |
559 | { | |
560 | #if 0 | |
561 | pr_debug("dma%d: s3c2410_dma_lastxfer: load_state %d\n", | |
562 | chan->number, chan->load_state); | |
563 | #endif | |
564 | ||
565 | switch (chan->load_state) { | |
566 | case S3C2410_DMALOAD_NONE: | |
567 | break; | |
568 | ||
569 | case S3C2410_DMALOAD_1LOADED: | |
570 | if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { | |
571 | /* flag error? */ | |
572 | printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n", | |
8e86f427 | 573 | chan->number, __func__); |
a21765a7 BD |
574 | return; |
575 | } | |
576 | break; | |
577 | ||
578 | case S3C2410_DMALOAD_1LOADED_1RUNNING: | |
579 | /* I belive in this case we do not have anything to do | |
580 | * until the next buffer comes along, and we turn off the | |
581 | * reload */ | |
582 | return; | |
583 | ||
584 | default: | |
585 | pr_debug("dma%d: lastxfer: unhandled load_state %d with no next\n", | |
586 | chan->number, chan->load_state); | |
587 | return; | |
588 | ||
589 | } | |
590 | ||
591 | /* hopefully this'll shut the damned thing up after the transfer... */ | |
592 | dma_wrreg(chan, S3C2410_DMA_DCON, chan->dcon | S3C2410_DCON_NORELOAD); | |
593 | } | |
594 | ||
595 | ||
596 | #define dmadbg2(x...) | |
597 | ||
598 | static irqreturn_t | |
599 | s3c2410_dma_irq(int irq, void *devpw) | |
600 | { | |
601 | struct s3c2410_dma_chan *chan = (struct s3c2410_dma_chan *)devpw; | |
602 | struct s3c2410_dma_buf *buf; | |
603 | ||
604 | buf = chan->curr; | |
605 | ||
606 | dbg_showchan(chan); | |
607 | ||
608 | /* modify the channel state */ | |
609 | ||
610 | switch (chan->load_state) { | |
611 | case S3C2410_DMALOAD_1RUNNING: | |
612 | /* TODO - if we are running only one buffer, we probably | |
613 | * want to reload here, and then worry about the buffer | |
614 | * callback */ | |
615 | ||
616 | chan->load_state = S3C2410_DMALOAD_NONE; | |
617 | break; | |
618 | ||
619 | case S3C2410_DMALOAD_1LOADED: | |
620 | /* iirc, we should go back to NONE loaded here, we | |
621 | * had a buffer, and it was never verified as being | |
622 | * loaded. | |
623 | */ | |
624 | ||
625 | chan->load_state = S3C2410_DMALOAD_NONE; | |
626 | break; | |
627 | ||
628 | case S3C2410_DMALOAD_1LOADED_1RUNNING: | |
629 | /* we'll worry about checking to see if another buffer is | |
630 | * ready after we've called back the owner. This should | |
631 | * ensure we do not wait around too long for the DMA | |
632 | * engine to start the next transfer | |
633 | */ | |
634 | ||
635 | chan->load_state = S3C2410_DMALOAD_1LOADED; | |
636 | break; | |
637 | ||
638 | case S3C2410_DMALOAD_NONE: | |
639 | printk(KERN_ERR "dma%d: IRQ with no loaded buffer?\n", | |
640 | chan->number); | |
641 | break; | |
642 | ||
643 | default: | |
644 | printk(KERN_ERR "dma%d: IRQ in invalid load_state %d\n", | |
645 | chan->number, chan->load_state); | |
646 | break; | |
647 | } | |
648 | ||
649 | if (buf != NULL) { | |
650 | /* update the chain to make sure that if we load any more | |
651 | * buffers when we call the callback function, things should | |
652 | * work properly */ | |
653 | ||
654 | chan->curr = buf->next; | |
655 | buf->next = NULL; | |
656 | ||
657 | if (buf->magic != BUF_MAGIC) { | |
658 | printk(KERN_ERR "dma%d: %s: buf %p incorrect magic\n", | |
8e86f427 | 659 | chan->number, __func__, buf); |
a21765a7 BD |
660 | return IRQ_HANDLED; |
661 | } | |
662 | ||
663 | s3c2410_dma_buffdone(chan, buf, S3C2410_RES_OK); | |
664 | ||
665 | /* free resouces */ | |
666 | s3c2410_dma_freebuf(buf); | |
667 | } else { | |
668 | } | |
669 | ||
670 | /* only reload if the channel is still running... our buffer done | |
671 | * routine may have altered the state by requesting the dma channel | |
672 | * to stop or shutdown... */ | |
673 | ||
674 | /* todo: check that when the channel is shut-down from inside this | |
675 | * function, we cope with unsetting reload, etc */ | |
676 | ||
677 | if (chan->next != NULL && chan->state != S3C2410_DMA_IDLE) { | |
678 | unsigned long flags; | |
679 | ||
680 | switch (chan->load_state) { | |
681 | case S3C2410_DMALOAD_1RUNNING: | |
682 | /* don't need to do anything for this state */ | |
683 | break; | |
684 | ||
685 | case S3C2410_DMALOAD_NONE: | |
686 | /* can load buffer immediately */ | |
687 | break; | |
688 | ||
689 | case S3C2410_DMALOAD_1LOADED: | |
690 | if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { | |
691 | /* flag error? */ | |
692 | printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n", | |
8e86f427 | 693 | chan->number, __func__); |
a21765a7 BD |
694 | return IRQ_HANDLED; |
695 | } | |
696 | ||
697 | break; | |
698 | ||
699 | case S3C2410_DMALOAD_1LOADED_1RUNNING: | |
700 | goto no_load; | |
701 | ||
702 | default: | |
703 | printk(KERN_ERR "dma%d: unknown load_state in irq, %d\n", | |
704 | chan->number, chan->load_state); | |
705 | return IRQ_HANDLED; | |
706 | } | |
707 | ||
708 | local_irq_save(flags); | |
709 | s3c2410_dma_loadbuffer(chan, chan->next); | |
710 | local_irq_restore(flags); | |
711 | } else { | |
712 | s3c2410_dma_lastxfer(chan); | |
713 | ||
714 | /* see if we can stop this channel.. */ | |
715 | if (chan->load_state == S3C2410_DMALOAD_NONE) { | |
716 | pr_debug("dma%d: end of transfer, stopping channel (%ld)\n", | |
717 | chan->number, jiffies); | |
718 | s3c2410_dma_ctrl(chan->number | DMACH_LOW_LEVEL, | |
719 | S3C2410_DMAOP_STOP); | |
720 | } | |
721 | } | |
722 | ||
723 | no_load: | |
724 | return IRQ_HANDLED; | |
725 | } | |
726 | ||
727 | static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel); | |
728 | ||
729 | /* s3c2410_request_dma | |
730 | * | |
731 | * get control of an dma channel | |
732 | */ | |
733 | ||
734 | int s3c2410_dma_request(unsigned int channel, | |
735 | struct s3c2410_dma_client *client, | |
736 | void *dev) | |
737 | { | |
738 | struct s3c2410_dma_chan *chan; | |
739 | unsigned long flags; | |
740 | int err; | |
741 | ||
742 | pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n", | |
743 | channel, client->name, dev); | |
744 | ||
745 | local_irq_save(flags); | |
746 | ||
747 | chan = s3c2410_dma_map_channel(channel); | |
748 | if (chan == NULL) { | |
749 | local_irq_restore(flags); | |
750 | return -EBUSY; | |
751 | } | |
752 | ||
753 | dbg_showchan(chan); | |
754 | ||
755 | chan->client = client; | |
756 | chan->in_use = 1; | |
757 | ||
758 | if (!chan->irq_claimed) { | |
759 | pr_debug("dma%d: %s : requesting irq %d\n", | |
8e86f427 | 760 | channel, __func__, chan->irq); |
a21765a7 BD |
761 | |
762 | chan->irq_claimed = 1; | |
763 | local_irq_restore(flags); | |
764 | ||
765 | err = request_irq(chan->irq, s3c2410_dma_irq, IRQF_DISABLED, | |
766 | client->name, (void *)chan); | |
767 | ||
768 | local_irq_save(flags); | |
769 | ||
770 | if (err) { | |
771 | chan->in_use = 0; | |
772 | chan->irq_claimed = 0; | |
773 | local_irq_restore(flags); | |
774 | ||
775 | printk(KERN_ERR "%s: cannot get IRQ %d for DMA %d\n", | |
776 | client->name, chan->irq, chan->number); | |
777 | return err; | |
778 | } | |
779 | ||
780 | chan->irq_enabled = 1; | |
781 | } | |
782 | ||
783 | local_irq_restore(flags); | |
784 | ||
785 | /* need to setup */ | |
786 | ||
8e86f427 | 787 | pr_debug("%s: channel initialised, %p\n", __func__, chan); |
a21765a7 | 788 | |
a07c438f | 789 | return chan->number | DMACH_LOW_LEVEL; |
a21765a7 BD |
790 | } |
791 | ||
792 | EXPORT_SYMBOL(s3c2410_dma_request); | |
793 | ||
794 | /* s3c2410_dma_free | |
795 | * | |
796 | * release the given channel back to the system, will stop and flush | |
797 | * any outstanding transfers, and ensure the channel is ready for the | |
798 | * next claimant. | |
799 | * | |
800 | * Note, although a warning is currently printed if the freeing client | |
801 | * info is not the same as the registrant's client info, the free is still | |
802 | * allowed to go through. | |
803 | */ | |
804 | ||
dcea83ad | 805 | int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *client) |
a21765a7 BD |
806 | { |
807 | struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); | |
808 | unsigned long flags; | |
809 | ||
810 | if (chan == NULL) | |
811 | return -EINVAL; | |
812 | ||
813 | local_irq_save(flags); | |
814 | ||
815 | if (chan->client != client) { | |
816 | printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n", | |
817 | channel, chan->client, client); | |
818 | } | |
819 | ||
820 | /* sort out stopping and freeing the channel */ | |
821 | ||
822 | if (chan->state != S3C2410_DMA_IDLE) { | |
823 | pr_debug("%s: need to stop dma channel %p\n", | |
8e86f427 | 824 | __func__, chan); |
a21765a7 BD |
825 | |
826 | /* possibly flush the channel */ | |
827 | s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STOP); | |
828 | } | |
829 | ||
830 | chan->client = NULL; | |
831 | chan->in_use = 0; | |
832 | ||
833 | if (chan->irq_claimed) | |
834 | free_irq(chan->irq, (void *)chan); | |
835 | ||
836 | chan->irq_claimed = 0; | |
837 | ||
838 | if (!(channel & DMACH_LOW_LEVEL)) | |
839 | dma_chan_map[channel] = NULL; | |
840 | ||
841 | local_irq_restore(flags); | |
842 | ||
843 | return 0; | |
844 | } | |
845 | ||
846 | EXPORT_SYMBOL(s3c2410_dma_free); | |
847 | ||
848 | static int s3c2410_dma_dostop(struct s3c2410_dma_chan *chan) | |
849 | { | |
850 | unsigned long flags; | |
851 | unsigned long tmp; | |
852 | ||
8e86f427 | 853 | pr_debug("%s:\n", __func__); |
a21765a7 BD |
854 | |
855 | dbg_showchan(chan); | |
856 | ||
857 | local_irq_save(flags); | |
858 | ||
859 | s3c2410_dma_call_op(chan, S3C2410_DMAOP_STOP); | |
860 | ||
861 | tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG); | |
862 | tmp |= S3C2410_DMASKTRIG_STOP; | |
863 | //tmp &= ~S3C2410_DMASKTRIG_ON; | |
864 | dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp); | |
865 | ||
866 | #if 0 | |
867 | /* should also clear interrupts, according to WinCE BSP */ | |
868 | tmp = dma_rdreg(chan, S3C2410_DMA_DCON); | |
869 | tmp |= S3C2410_DCON_NORELOAD; | |
870 | dma_wrreg(chan, S3C2410_DMA_DCON, tmp); | |
871 | #endif | |
872 | ||
873 | /* should stop do this, or should we wait for flush? */ | |
874 | chan->state = S3C2410_DMA_IDLE; | |
875 | chan->load_state = S3C2410_DMALOAD_NONE; | |
876 | ||
877 | local_irq_restore(flags); | |
878 | ||
879 | return 0; | |
880 | } | |
881 | ||
a7717435 | 882 | static void s3c2410_dma_waitforstop(struct s3c2410_dma_chan *chan) |
a21765a7 BD |
883 | { |
884 | unsigned long tmp; | |
885 | unsigned int timeout = 0x10000; | |
886 | ||
887 | while (timeout-- > 0) { | |
888 | tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG); | |
889 | ||
890 | if (!(tmp & S3C2410_DMASKTRIG_ON)) | |
891 | return; | |
892 | } | |
893 | ||
894 | pr_debug("dma%d: failed to stop?\n", chan->number); | |
895 | } | |
896 | ||
897 | ||
898 | /* s3c2410_dma_flush | |
899 | * | |
900 | * stop the channel, and remove all current and pending transfers | |
901 | */ | |
902 | ||
903 | static int s3c2410_dma_flush(struct s3c2410_dma_chan *chan) | |
904 | { | |
905 | struct s3c2410_dma_buf *buf, *next; | |
906 | unsigned long flags; | |
907 | ||
8e86f427 | 908 | pr_debug("%s: chan %p (%d)\n", __func__, chan, chan->number); |
a21765a7 BD |
909 | |
910 | dbg_showchan(chan); | |
911 | ||
912 | local_irq_save(flags); | |
913 | ||
914 | if (chan->state != S3C2410_DMA_IDLE) { | |
8e86f427 | 915 | pr_debug("%s: stopping channel...\n", __func__ ); |
a21765a7 BD |
916 | s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_STOP); |
917 | } | |
918 | ||
919 | buf = chan->curr; | |
920 | if (buf == NULL) | |
921 | buf = chan->next; | |
922 | ||
923 | chan->curr = chan->next = chan->end = NULL; | |
924 | ||
925 | if (buf != NULL) { | |
926 | for ( ; buf != NULL; buf = next) { | |
927 | next = buf->next; | |
928 | ||
929 | pr_debug("%s: free buffer %p, next %p\n", | |
8e86f427 | 930 | __func__, buf, buf->next); |
a21765a7 BD |
931 | |
932 | s3c2410_dma_buffdone(chan, buf, S3C2410_RES_ABORT); | |
933 | s3c2410_dma_freebuf(buf); | |
934 | } | |
935 | } | |
936 | ||
937 | dbg_showregs(chan); | |
938 | ||
939 | s3c2410_dma_waitforstop(chan); | |
940 | ||
941 | #if 0 | |
942 | /* should also clear interrupts, according to WinCE BSP */ | |
943 | { | |
944 | unsigned long tmp; | |
945 | ||
946 | tmp = dma_rdreg(chan, S3C2410_DMA_DCON); | |
947 | tmp |= S3C2410_DCON_NORELOAD; | |
948 | dma_wrreg(chan, S3C2410_DMA_DCON, tmp); | |
949 | } | |
950 | #endif | |
951 | ||
952 | dbg_showregs(chan); | |
953 | ||
954 | local_irq_restore(flags); | |
955 | ||
956 | return 0; | |
957 | } | |
958 | ||
a7717435 | 959 | static int s3c2410_dma_started(struct s3c2410_dma_chan *chan) |
a21765a7 BD |
960 | { |
961 | unsigned long flags; | |
962 | ||
963 | local_irq_save(flags); | |
964 | ||
965 | dbg_showchan(chan); | |
966 | ||
967 | /* if we've only loaded one buffer onto the channel, then chec | |
968 | * to see if we have another, and if so, try and load it so when | |
969 | * the first buffer is finished, the new one will be loaded onto | |
970 | * the channel */ | |
971 | ||
972 | if (chan->next != NULL) { | |
973 | if (chan->load_state == S3C2410_DMALOAD_1LOADED) { | |
974 | ||
975 | if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { | |
976 | pr_debug("%s: buff not yet loaded, no more todo\n", | |
8e86f427 | 977 | __func__); |
a21765a7 BD |
978 | } else { |
979 | chan->load_state = S3C2410_DMALOAD_1RUNNING; | |
980 | s3c2410_dma_loadbuffer(chan, chan->next); | |
981 | } | |
982 | ||
983 | } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) { | |
984 | s3c2410_dma_loadbuffer(chan, chan->next); | |
985 | } | |
986 | } | |
987 | ||
988 | ||
989 | local_irq_restore(flags); | |
990 | ||
991 | return 0; | |
992 | ||
993 | } | |
994 | ||
995 | int | |
dcea83ad | 996 | s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op) |
a21765a7 BD |
997 | { |
998 | struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); | |
999 | ||
1000 | if (chan == NULL) | |
1001 | return -EINVAL; | |
1002 | ||
1003 | switch (op) { | |
1004 | case S3C2410_DMAOP_START: | |
1005 | return s3c2410_dma_start(chan); | |
1006 | ||
1007 | case S3C2410_DMAOP_STOP: | |
1008 | return s3c2410_dma_dostop(chan); | |
1009 | ||
1010 | case S3C2410_DMAOP_PAUSE: | |
1011 | case S3C2410_DMAOP_RESUME: | |
1012 | return -ENOENT; | |
1013 | ||
1014 | case S3C2410_DMAOP_FLUSH: | |
1015 | return s3c2410_dma_flush(chan); | |
1016 | ||
1017 | case S3C2410_DMAOP_STARTED: | |
1018 | return s3c2410_dma_started(chan); | |
1019 | ||
1020 | case S3C2410_DMAOP_TIMEOUT: | |
1021 | return 0; | |
1022 | ||
1023 | } | |
1024 | ||
1025 | return -ENOENT; /* unknown, don't bother */ | |
1026 | } | |
1027 | ||
1028 | EXPORT_SYMBOL(s3c2410_dma_ctrl); | |
1029 | ||
1030 | /* DMA configuration for each channel | |
1031 | * | |
1032 | * DISRCC -> source of the DMA (AHB,APB) | |
1033 | * DISRC -> source address of the DMA | |
1034 | * DIDSTC -> destination of the DMA (AHB,APD) | |
1035 | * DIDST -> destination address of the DMA | |
1036 | */ | |
1037 | ||
1038 | /* s3c2410_dma_config | |
1039 | * | |
1040 | * xfersize: size of unit in bytes (1,2,4) | |
1041 | * dcon: base value of the DCONx register | |
1042 | */ | |
1043 | ||
dcea83ad | 1044 | int s3c2410_dma_config(unsigned int channel, |
a21765a7 BD |
1045 | int xferunit, |
1046 | int dcon) | |
1047 | { | |
1048 | struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); | |
1049 | ||
1050 | pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n", | |
8e86f427 | 1051 | __func__, channel, xferunit, dcon); |
a21765a7 BD |
1052 | |
1053 | if (chan == NULL) | |
1054 | return -EINVAL; | |
1055 | ||
8e86f427 | 1056 | pr_debug("%s: Initial dcon is %08x\n", __func__, dcon); |
a21765a7 BD |
1057 | |
1058 | dcon |= chan->dcon & dma_sel.dcon_mask; | |
1059 | ||
8e86f427 | 1060 | pr_debug("%s: New dcon is %08x\n", __func__, dcon); |
a21765a7 BD |
1061 | |
1062 | switch (xferunit) { | |
1063 | case 1: | |
1064 | dcon |= S3C2410_DCON_BYTE; | |
1065 | break; | |
1066 | ||
1067 | case 2: | |
1068 | dcon |= S3C2410_DCON_HALFWORD; | |
1069 | break; | |
1070 | ||
1071 | case 4: | |
1072 | dcon |= S3C2410_DCON_WORD; | |
1073 | break; | |
1074 | ||
1075 | default: | |
8e86f427 | 1076 | pr_debug("%s: bad transfer size %d\n", __func__, xferunit); |
a21765a7 BD |
1077 | return -EINVAL; |
1078 | } | |
1079 | ||
1080 | dcon |= S3C2410_DCON_HWTRIG; | |
1081 | dcon |= S3C2410_DCON_INTREQ; | |
1082 | ||
8e86f427 | 1083 | pr_debug("%s: dcon now %08x\n", __func__, dcon); |
a21765a7 BD |
1084 | |
1085 | chan->dcon = dcon; | |
1086 | chan->xfer_unit = xferunit; | |
1087 | ||
1088 | return 0; | |
1089 | } | |
1090 | ||
1091 | EXPORT_SYMBOL(s3c2410_dma_config); | |
1092 | ||
dcea83ad | 1093 | int s3c2410_dma_setflags(unsigned int channel, unsigned int flags) |
a21765a7 BD |
1094 | { |
1095 | struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); | |
1096 | ||
1097 | if (chan == NULL) | |
1098 | return -EINVAL; | |
1099 | ||
8e86f427 | 1100 | pr_debug("%s: chan=%p, flags=%08x\n", __func__, chan, flags); |
a21765a7 BD |
1101 | |
1102 | chan->flags = flags; | |
1103 | ||
1104 | return 0; | |
1105 | } | |
1106 | ||
1107 | EXPORT_SYMBOL(s3c2410_dma_setflags); | |
1108 | ||
1109 | ||
1110 | /* do we need to protect the settings of the fields from | |
1111 | * irq? | |
1112 | */ | |
1113 | ||
dcea83ad | 1114 | int s3c2410_dma_set_opfn(unsigned int channel, s3c2410_dma_opfn_t rtn) |
a21765a7 BD |
1115 | { |
1116 | struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); | |
1117 | ||
1118 | if (chan == NULL) | |
1119 | return -EINVAL; | |
1120 | ||
8e86f427 | 1121 | pr_debug("%s: chan=%p, op rtn=%p\n", __func__, chan, rtn); |
a21765a7 BD |
1122 | |
1123 | chan->op_fn = rtn; | |
1124 | ||
1125 | return 0; | |
1126 | } | |
1127 | ||
1128 | EXPORT_SYMBOL(s3c2410_dma_set_opfn); | |
1129 | ||
dcea83ad | 1130 | int s3c2410_dma_set_buffdone_fn(unsigned int channel, s3c2410_dma_cbfn_t rtn) |
a21765a7 BD |
1131 | { |
1132 | struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); | |
1133 | ||
1134 | if (chan == NULL) | |
1135 | return -EINVAL; | |
1136 | ||
8e86f427 | 1137 | pr_debug("%s: chan=%p, callback rtn=%p\n", __func__, chan, rtn); |
a21765a7 BD |
1138 | |
1139 | chan->callback_fn = rtn; | |
1140 | ||
1141 | return 0; | |
1142 | } | |
1143 | ||
1144 | EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn); | |
1145 | ||
1146 | /* s3c2410_dma_devconfig | |
1147 | * | |
1148 | * configure the dma source/destination hardware type and address | |
1149 | * | |
1150 | * source: S3C2410_DMASRC_HW: source is hardware | |
1151 | * S3C2410_DMASRC_MEM: source is memory | |
1152 | * | |
1153 | * hwcfg: the value for xxxSTCn register, | |
1154 | * bit 0: 0=increment pointer, 1=leave pointer | |
6cbdc8c5 | 1155 | * bit 1: 0=source is AHB, 1=source is APB |
a21765a7 BD |
1156 | * |
1157 | * devaddr: physical address of the source | |
1158 | */ | |
1159 | ||
1160 | int s3c2410_dma_devconfig(int channel, | |
1161 | enum s3c2410_dmasrc source, | |
1162 | int hwcfg, | |
1163 | unsigned long devaddr) | |
1164 | { | |
1165 | struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); | |
1166 | ||
1167 | if (chan == NULL) | |
1168 | return -EINVAL; | |
1169 | ||
1170 | pr_debug("%s: source=%d, hwcfg=%08x, devaddr=%08lx\n", | |
8e86f427 | 1171 | __func__, (int)source, hwcfg, devaddr); |
a21765a7 BD |
1172 | |
1173 | chan->source = source; | |
1174 | chan->dev_addr = devaddr; | |
c58f7a1d | 1175 | chan->hw_cfg = hwcfg; |
a21765a7 BD |
1176 | |
1177 | switch (source) { | |
1178 | case S3C2410_DMASRC_HW: | |
1179 | /* source is hardware */ | |
1180 | pr_debug("%s: hw source, devaddr=%08lx, hwcfg=%d\n", | |
8e86f427 | 1181 | __func__, devaddr, hwcfg); |
a21765a7 BD |
1182 | dma_wrreg(chan, S3C2410_DMA_DISRCC, hwcfg & 3); |
1183 | dma_wrreg(chan, S3C2410_DMA_DISRC, devaddr); | |
1184 | dma_wrreg(chan, S3C2410_DMA_DIDSTC, (0<<1) | (0<<0)); | |
1185 | ||
1186 | chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DIDST); | |
c6709e8e | 1187 | break; |
a21765a7 BD |
1188 | |
1189 | case S3C2410_DMASRC_MEM: | |
1190 | /* source is memory */ | |
8e86f427 HH |
1191 | pr_debug("%s: mem source, devaddr=%08lx, hwcfg=%d\n", |
1192 | __func__, devaddr, hwcfg); | |
a21765a7 BD |
1193 | dma_wrreg(chan, S3C2410_DMA_DISRCC, (0<<1) | (0<<0)); |
1194 | dma_wrreg(chan, S3C2410_DMA_DIDST, devaddr); | |
1195 | dma_wrreg(chan, S3C2410_DMA_DIDSTC, hwcfg & 3); | |
1196 | ||
1197 | chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DISRC); | |
c6709e8e BD |
1198 | break; |
1199 | ||
1200 | default: | |
1201 | printk(KERN_ERR "dma%d: invalid source type (%d)\n", | |
1202 | channel, source); | |
1203 | ||
1204 | return -EINVAL; | |
a21765a7 BD |
1205 | } |
1206 | ||
c6709e8e BD |
1207 | if (dma_sel.direction != NULL) |
1208 | (dma_sel.direction)(chan, chan->map, source); | |
1209 | ||
1210 | return 0; | |
a21765a7 BD |
1211 | } |
1212 | ||
1213 | EXPORT_SYMBOL(s3c2410_dma_devconfig); | |
1214 | ||
1215 | /* s3c2410_dma_getposition | |
1216 | * | |
1217 | * returns the current transfer points for the dma source and destination | |
1218 | */ | |
1219 | ||
dcea83ad | 1220 | int s3c2410_dma_getposition(unsigned int channel, dma_addr_t *src, dma_addr_t *dst) |
a21765a7 BD |
1221 | { |
1222 | struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); | |
1223 | ||
1224 | if (chan == NULL) | |
1225 | return -EINVAL; | |
1226 | ||
1227 | if (src != NULL) | |
1228 | *src = dma_rdreg(chan, S3C2410_DMA_DCSRC); | |
1229 | ||
1230 | if (dst != NULL) | |
1231 | *dst = dma_rdreg(chan, S3C2410_DMA_DCDST); | |
1232 | ||
1233 | return 0; | |
1234 | } | |
1235 | ||
1236 | EXPORT_SYMBOL(s3c2410_dma_getposition); | |
1237 | ||
c58f7a1d BD |
1238 | static struct s3c2410_dma_chan *to_dma_chan(struct sys_device *dev) |
1239 | { | |
1240 | return container_of(dev, struct s3c2410_dma_chan, dev); | |
1241 | } | |
a21765a7 BD |
1242 | |
1243 | /* system device class */ | |
1244 | ||
1245 | #ifdef CONFIG_PM | |
1246 | ||
1247 | static int s3c2410_dma_suspend(struct sys_device *dev, pm_message_t state) | |
1248 | { | |
c58f7a1d | 1249 | struct s3c2410_dma_chan *cp = to_dma_chan(dev); |
a21765a7 BD |
1250 | |
1251 | printk(KERN_DEBUG "suspending dma channel %d\n", cp->number); | |
1252 | ||
1253 | if (dma_rdreg(cp, S3C2410_DMA_DMASKTRIG) & S3C2410_DMASKTRIG_ON) { | |
1254 | /* the dma channel is still working, which is probably | |
1255 | * a bad thing to do over suspend/resume. We stop the | |
1256 | * channel and assume that the client is either going to | |
1257 | * retry after resume, or that it is broken. | |
1258 | */ | |
1259 | ||
1260 | printk(KERN_INFO "dma: stopping channel %d due to suspend\n", | |
1261 | cp->number); | |
1262 | ||
1263 | s3c2410_dma_dostop(cp); | |
1264 | } | |
1265 | ||
1266 | return 0; | |
1267 | } | |
1268 | ||
1269 | static int s3c2410_dma_resume(struct sys_device *dev) | |
1270 | { | |
c58f7a1d BD |
1271 | struct s3c2410_dma_chan *cp = to_dma_chan(dev); |
1272 | unsigned int no = cp->number | DMACH_LOW_LEVEL; | |
1273 | ||
1274 | /* restore channel's hardware configuration */ | |
1275 | ||
1276 | if (!cp->in_use) | |
1277 | return 0; | |
1278 | ||
1279 | printk(KERN_INFO "dma%d: restoring configuration\n", cp->number); | |
1280 | ||
1281 | s3c2410_dma_config(no, cp->xfer_unit, cp->dcon); | |
1282 | s3c2410_dma_devconfig(no, cp->source, cp->hw_cfg, cp->dev_addr); | |
1283 | ||
1284 | /* re-select the dma source for this channel */ | |
1285 | ||
1286 | if (cp->map != NULL) | |
1287 | dma_sel.select(cp, cp->map); | |
1288 | ||
a21765a7 BD |
1289 | return 0; |
1290 | } | |
1291 | ||
1292 | #else | |
1293 | #define s3c2410_dma_suspend NULL | |
1294 | #define s3c2410_dma_resume NULL | |
1295 | #endif /* CONFIG_PM */ | |
1296 | ||
1297 | struct sysdev_class dma_sysclass = { | |
af5ca3f4 | 1298 | .name = "s3c24xx-dma", |
a21765a7 BD |
1299 | .suspend = s3c2410_dma_suspend, |
1300 | .resume = s3c2410_dma_resume, | |
1301 | }; | |
1302 | ||
1303 | /* kmem cache implementation */ | |
1304 | ||
51cc5068 | 1305 | static void s3c2410_dma_cache_ctor(void *p) |
a21765a7 BD |
1306 | { |
1307 | memset(p, 0, sizeof(struct s3c2410_dma_buf)); | |
1308 | } | |
1309 | ||
1310 | /* initialisation code */ | |
1311 | ||
a7717435 | 1312 | static int __init s3c24xx_dma_sysclass_init(void) |
48adbcf3 BD |
1313 | { |
1314 | int ret = sysdev_class_register(&dma_sysclass); | |
1315 | ||
1316 | if (ret != 0) | |
1317 | printk(KERN_ERR "dma sysclass registration failed\n"); | |
1318 | ||
1319 | return ret; | |
1320 | } | |
1321 | ||
1322 | core_initcall(s3c24xx_dma_sysclass_init); | |
1323 | ||
a7717435 | 1324 | static int __init s3c24xx_dma_sysdev_register(void) |
48adbcf3 BD |
1325 | { |
1326 | struct s3c2410_dma_chan *cp = s3c2410_chans; | |
1327 | int channel, ret; | |
1328 | ||
1329 | for (channel = 0; channel < dma_channels; cp++, channel++) { | |
1330 | cp->dev.cls = &dma_sysclass; | |
1331 | cp->dev.id = channel; | |
1332 | ret = sysdev_register(&cp->dev); | |
1333 | ||
1334 | if (ret) { | |
1335 | printk(KERN_ERR "error registering dev for dma %d\n", | |
1336 | channel); | |
1337 | return ret; | |
1338 | } | |
1339 | } | |
1340 | ||
1341 | return 0; | |
1342 | } | |
1343 | ||
1344 | late_initcall(s3c24xx_dma_sysdev_register); | |
1345 | ||
1346 | int __init s3c24xx_dma_init(unsigned int channels, unsigned int irq, | |
1347 | unsigned int stride) | |
a21765a7 BD |
1348 | { |
1349 | struct s3c2410_dma_chan *cp; | |
1350 | int channel; | |
1351 | int ret; | |
1352 | ||
1353 | printk("S3C24XX DMA Driver, (c) 2003-2004,2006 Simtec Electronics\n"); | |
1354 | ||
48adbcf3 BD |
1355 | dma_channels = channels; |
1356 | ||
1357 | dma_base = ioremap(S3C24XX_PA_DMA, stride * channels); | |
a21765a7 BD |
1358 | if (dma_base == NULL) { |
1359 | printk(KERN_ERR "dma failed to remap register block\n"); | |
1360 | return -ENOMEM; | |
1361 | } | |
1362 | ||
48adbcf3 BD |
1363 | dma_kmem = kmem_cache_create("dma_desc", |
1364 | sizeof(struct s3c2410_dma_buf), 0, | |
a21765a7 | 1365 | SLAB_HWCACHE_ALIGN, |
20c2df83 | 1366 | s3c2410_dma_cache_ctor); |
a21765a7 BD |
1367 | |
1368 | if (dma_kmem == NULL) { | |
1369 | printk(KERN_ERR "dma failed to make kmem cache\n"); | |
1370 | ret = -ENOMEM; | |
1371 | goto err; | |
1372 | } | |
1373 | ||
48adbcf3 | 1374 | for (channel = 0; channel < channels; channel++) { |
a21765a7 BD |
1375 | cp = &s3c2410_chans[channel]; |
1376 | ||
1377 | memset(cp, 0, sizeof(struct s3c2410_dma_chan)); | |
1378 | ||
1379 | /* dma channel irqs are in order.. */ | |
1380 | cp->number = channel; | |
48adbcf3 BD |
1381 | cp->irq = channel + irq; |
1382 | cp->regs = dma_base + (channel * stride); | |
a21765a7 BD |
1383 | |
1384 | /* point current stats somewhere */ | |
1385 | cp->stats = &cp->stats_store; | |
1386 | cp->stats_store.timeout_shortest = LONG_MAX; | |
1387 | ||
1388 | /* basic channel configuration */ | |
1389 | ||
1390 | cp->load_timeout = 1<<18; | |
1391 | ||
a21765a7 BD |
1392 | printk("DMA channel %d at %p, irq %d\n", |
1393 | cp->number, cp->regs, cp->irq); | |
1394 | } | |
1395 | ||
1396 | return 0; | |
1397 | ||
1398 | err: | |
1399 | kmem_cache_destroy(dma_kmem); | |
1400 | iounmap(dma_base); | |
1401 | dma_base = NULL; | |
1402 | return ret; | |
1403 | } | |
1404 | ||
f2c10d6c | 1405 | int __init s3c2410_dma_init(void) |
48adbcf3 BD |
1406 | { |
1407 | return s3c24xx_dma_init(4, IRQ_DMA0, 0x40); | |
1408 | } | |
a21765a7 BD |
1409 | |
1410 | static inline int is_channel_valid(unsigned int channel) | |
1411 | { | |
1412 | return (channel & DMA_CH_VALID); | |
1413 | } | |
1414 | ||
0c6022d4 BD |
1415 | static struct s3c24xx_dma_order *dma_order; |
1416 | ||
1417 | ||
a21765a7 BD |
1418 | /* s3c2410_dma_map_channel() |
1419 | * | |
1420 | * turn the virtual channel number into a real, and un-used hardware | |
1421 | * channel. | |
1422 | * | |
0c6022d4 BD |
1423 | * first, try the dma ordering given to us by either the relevant |
1424 | * dma code, or the board. Then just find the first usable free | |
1425 | * channel | |
a21765a7 BD |
1426 | */ |
1427 | ||
a7717435 | 1428 | static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel) |
a21765a7 | 1429 | { |
0c6022d4 | 1430 | struct s3c24xx_dma_order_ch *ord = NULL; |
a21765a7 BD |
1431 | struct s3c24xx_dma_map *ch_map; |
1432 | struct s3c2410_dma_chan *dmach; | |
1433 | int ch; | |
1434 | ||
1435 | if (dma_sel.map == NULL || channel > dma_sel.map_size) | |
1436 | return NULL; | |
1437 | ||
1438 | ch_map = dma_sel.map + channel; | |
1439 | ||
0c6022d4 BD |
1440 | /* first, try the board mapping */ |
1441 | ||
1442 | if (dma_order) { | |
1443 | ord = &dma_order->channels[channel]; | |
1444 | ||
48adbcf3 | 1445 | for (ch = 0; ch < dma_channels; ch++) { |
0c6022d4 BD |
1446 | if (!is_channel_valid(ord->list[ch])) |
1447 | continue; | |
1448 | ||
1449 | if (s3c2410_chans[ord->list[ch]].in_use == 0) { | |
1450 | ch = ord->list[ch] & ~DMA_CH_VALID; | |
1451 | goto found; | |
1452 | } | |
1453 | } | |
1454 | ||
1455 | if (ord->flags & DMA_CH_NEVER) | |
1456 | return NULL; | |
1457 | } | |
1458 | ||
1459 | /* second, search the channel map for first free */ | |
1460 | ||
48adbcf3 | 1461 | for (ch = 0; ch < dma_channels; ch++) { |
a21765a7 BD |
1462 | if (!is_channel_valid(ch_map->channels[ch])) |
1463 | continue; | |
1464 | ||
1465 | if (s3c2410_chans[ch].in_use == 0) { | |
1466 | printk("mapped channel %d to %d\n", channel, ch); | |
1467 | break; | |
1468 | } | |
1469 | } | |
1470 | ||
48adbcf3 | 1471 | if (ch >= dma_channels) |
a21765a7 BD |
1472 | return NULL; |
1473 | ||
1474 | /* update our channel mapping */ | |
1475 | ||
0c6022d4 | 1476 | found: |
a21765a7 | 1477 | dmach = &s3c2410_chans[ch]; |
c58f7a1d | 1478 | dmach->map = ch_map; |
a21765a7 BD |
1479 | dma_chan_map[channel] = dmach; |
1480 | ||
1481 | /* select the channel */ | |
1482 | ||
1483 | (dma_sel.select)(dmach, ch_map); | |
1484 | ||
1485 | return dmach; | |
1486 | } | |
1487 | ||
a21765a7 BD |
1488 | static int s3c24xx_dma_check_entry(struct s3c24xx_dma_map *map, int ch) |
1489 | { | |
a21765a7 BD |
1490 | return 0; |
1491 | } | |
1492 | ||
1493 | int __init s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel) | |
1494 | { | |
1495 | struct s3c24xx_dma_map *nmap; | |
1496 | size_t map_sz = sizeof(*nmap) * sel->map_size; | |
1497 | int ptr; | |
1498 | ||
1499 | nmap = kmalloc(map_sz, GFP_KERNEL); | |
1500 | if (nmap == NULL) | |
1501 | return -ENOMEM; | |
1502 | ||
1503 | memcpy(nmap, sel->map, map_sz); | |
1504 | memcpy(&dma_sel, sel, sizeof(*sel)); | |
1505 | ||
1506 | dma_sel.map = nmap; | |
1507 | ||
1508 | for (ptr = 0; ptr < sel->map_size; ptr++) | |
1509 | s3c24xx_dma_check_entry(nmap+ptr, ptr); | |
1510 | ||
1511 | return 0; | |
1512 | } | |
0c6022d4 BD |
1513 | |
1514 | int __init s3c24xx_dma_order_set(struct s3c24xx_dma_order *ord) | |
1515 | { | |
1516 | struct s3c24xx_dma_order *nord = dma_order; | |
1517 | ||
1518 | if (nord == NULL) | |
1519 | nord = kmalloc(sizeof(struct s3c24xx_dma_order), GFP_KERNEL); | |
1520 | ||
1521 | if (nord == NULL) { | |
1522 | printk(KERN_ERR "no memory to store dma channel order\n"); | |
1523 | return -ENOMEM; | |
1524 | } | |
1525 | ||
1526 | dma_order = nord; | |
1527 | memcpy(nord, ord, sizeof(struct s3c24xx_dma_order)); | |
1528 | return 0; | |
1529 | } |