Commit | Line | Data |
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a21765a7 | 1 | /* linux/arch/arm/plat-s3c24xx/cpu.c |
1da177e4 LT |
2 | * |
3 | * Copyright (c) 2004-2005 Simtec Electronics | |
4 | * http://www.simtec.co.uk/products/SWLINUX/ | |
5 | * Ben Dooks <ben@simtec.co.uk> | |
6 | * | |
7 | * S3C24XX CPU Support | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | ||
25 | #include <linux/init.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/ioport.h> | |
b6d1f542 | 29 | #include <linux/serial_core.h> |
d052d1be | 30 | #include <linux/platform_device.h> |
3c7d9c81 | 31 | #include <linux/delay.h> |
fced80c7 | 32 | #include <linux/io.h> |
1da177e4 | 33 | |
a09e64fb | 34 | #include <mach/hardware.h> |
1da177e4 | 35 | #include <asm/irq.h> |
3c7d9c81 | 36 | #include <asm/cacheflush.h> |
1da177e4 LT |
37 | |
38 | #include <asm/mach/arch.h> | |
39 | #include <asm/mach/map.h> | |
40 | ||
a09e64fb | 41 | #include <mach/system-reset.h> |
3c7d9c81 | 42 | |
a09e64fb | 43 | #include <mach/regs-gpio.h> |
a2b7ba9c | 44 | #include <plat/regs-serial.h> |
1da177e4 | 45 | |
a2b7ba9c BD |
46 | #include <plat/cpu.h> |
47 | #include <plat/devs.h> | |
d5120ae7 | 48 | #include <plat/clock.h> |
a2b7ba9c BD |
49 | #include <plat/s3c2400.h> |
50 | #include <plat/s3c2410.h> | |
d5120ae7 | 51 | #include <plat/s3c2412.h> |
96ce2385 | 52 | #include "s3c244x.h" |
a2b7ba9c BD |
53 | #include <plat/s3c2440.h> |
54 | #include <plat/s3c2442.h> | |
55 | #include <plat/s3c2443.h> | |
1da177e4 | 56 | |
1da177e4 LT |
57 | /* table of supported CPUs */ |
58 | ||
83f755f5 | 59 | static const char name_s3c2400[] = "S3C2400"; |
1da177e4 | 60 | static const char name_s3c2410[] = "S3C2410"; |
68d9ab39 | 61 | static const char name_s3c2412[] = "S3C2412"; |
1da177e4 | 62 | static const char name_s3c2440[] = "S3C2440"; |
96ce2385 | 63 | static const char name_s3c2442[] = "S3C2442"; |
e4d06e39 | 64 | static const char name_s3c2443[] = "S3C2443"; |
1da177e4 LT |
65 | static const char name_s3c2410a[] = "S3C2410A"; |
66 | static const char name_s3c2440a[] = "S3C2440A"; | |
67 | ||
68 | static struct cpu_table cpu_ids[] __initdata = { | |
69 | { | |
70 | .idcode = 0x32410000, | |
71 | .idmask = 0xffffffff, | |
72 | .map_io = s3c2410_map_io, | |
73 | .init_clocks = s3c2410_init_clocks, | |
74 | .init_uarts = s3c2410_init_uarts, | |
75 | .init = s3c2410_init, | |
76 | .name = name_s3c2410 | |
77 | }, | |
78 | { | |
79 | .idcode = 0x32410002, | |
80 | .idmask = 0xffffffff, | |
81 | .map_io = s3c2410_map_io, | |
82 | .init_clocks = s3c2410_init_clocks, | |
83 | .init_uarts = s3c2410_init_uarts, | |
84 | .init = s3c2410_init, | |
85 | .name = name_s3c2410a | |
86 | }, | |
87 | { | |
88 | .idcode = 0x32440000, | |
89 | .idmask = 0xffffffff, | |
96ce2385 BD |
90 | .map_io = s3c244x_map_io, |
91 | .init_clocks = s3c244x_init_clocks, | |
92 | .init_uarts = s3c244x_init_uarts, | |
1da177e4 LT |
93 | .init = s3c2440_init, |
94 | .name = name_s3c2440 | |
95 | }, | |
96 | { | |
97 | .idcode = 0x32440001, | |
98 | .idmask = 0xffffffff, | |
96ce2385 BD |
99 | .map_io = s3c244x_map_io, |
100 | .init_clocks = s3c244x_init_clocks, | |
101 | .init_uarts = s3c244x_init_uarts, | |
1da177e4 LT |
102 | .init = s3c2440_init, |
103 | .name = name_s3c2440a | |
83f755f5 | 104 | }, |
96ce2385 BD |
105 | { |
106 | .idcode = 0x32440aaa, | |
107 | .idmask = 0xffffffff, | |
108 | .map_io = s3c244x_map_io, | |
109 | .init_clocks = s3c244x_init_clocks, | |
110 | .init_uarts = s3c244x_init_uarts, | |
111 | .init = s3c2442_init, | |
112 | .name = name_s3c2442 | |
113 | }, | |
68d9ab39 BD |
114 | { |
115 | .idcode = 0x32412001, | |
116 | .idmask = 0xffffffff, | |
117 | .map_io = s3c2412_map_io, | |
118 | .init_clocks = s3c2412_init_clocks, | |
119 | .init_uarts = s3c2412_init_uarts, | |
120 | .init = s3c2412_init, | |
121 | .name = name_s3c2412, | |
122 | }, | |
d9bc55fa BD |
123 | { /* a newer version of the s3c2412 */ |
124 | .idcode = 0x32412003, | |
125 | .idmask = 0xffffffff, | |
126 | .map_io = s3c2412_map_io, | |
127 | .init_clocks = s3c2412_init_clocks, | |
128 | .init_uarts = s3c2412_init_uarts, | |
129 | .init = s3c2412_init, | |
130 | .name = name_s3c2412, | |
131 | }, | |
e4d06e39 BD |
132 | { |
133 | .idcode = 0x32443001, | |
134 | .idmask = 0xffffffff, | |
135 | .map_io = s3c2443_map_io, | |
136 | .init_clocks = s3c2443_init_clocks, | |
137 | .init_uarts = s3c2443_init_uarts, | |
138 | .init = s3c2443_init, | |
139 | .name = name_s3c2443, | |
140 | }, | |
83f755f5 LCVR |
141 | { |
142 | .idcode = 0x0, /* S3C2400 doesn't have an idcode */ | |
143 | .idmask = 0xffffffff, | |
144 | .map_io = s3c2400_map_io, | |
145 | .init_clocks = s3c2400_init_clocks, | |
146 | .init_uarts = s3c2400_init_uarts, | |
147 | .init = s3c2400_init, | |
148 | .name = name_s3c2400 | |
149 | }, | |
1da177e4 LT |
150 | }; |
151 | ||
152 | /* minimal IO mapping */ | |
153 | ||
154 | static struct map_desc s3c_iodesc[] __initdata = { | |
155 | IODESC_ENT(GPIO), | |
156 | IODESC_ENT(IRQ), | |
157 | IODESC_ENT(MEMCTRL), | |
158 | IODESC_ENT(UART) | |
159 | }; | |
160 | ||
74b265d4 | 161 | /* read cpu identificaiton code */ |
1da177e4 | 162 | |
68d9ab39 BD |
163 | static unsigned long s3c24xx_read_idcode_v5(void) |
164 | { | |
165 | #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) | |
166 | return __raw_readl(S3C2412_GSTATUS1); | |
167 | #else | |
168 | return 1UL; /* don't look like an 2400 */ | |
169 | #endif | |
170 | } | |
171 | ||
172 | static unsigned long s3c24xx_read_idcode_v4(void) | |
173 | { | |
174 | #ifndef CONFIG_CPU_S3C2400 | |
175 | return __raw_readl(S3C2410_GSTATUS1); | |
176 | #else | |
177 | return 0UL; | |
178 | #endif | |
179 | } | |
180 | ||
3c7d9c81 BD |
181 | /* Hook for arm_pm_restart to ensure we execute the reset code |
182 | * with the caches enabled. It seems at least the S3C2440 has a problem | |
183 | * resetting if there is bus activity interrupted by the reset. | |
184 | */ | |
185 | static void s3c24xx_pm_restart(char mode) | |
186 | { | |
187 | if (mode != 's') { | |
188 | unsigned long flags; | |
189 | ||
190 | local_irq_save(flags); | |
191 | __cpuc_flush_kern_all(); | |
192 | __cpuc_flush_user_all(); | |
193 | ||
194 | arch_reset(mode); | |
195 | local_irq_restore(flags); | |
196 | } | |
197 | ||
198 | /* fallback, or unhandled */ | |
199 | arm_machine_restart(mode); | |
200 | } | |
201 | ||
1da177e4 LT |
202 | void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) |
203 | { | |
83f755f5 | 204 | unsigned long idcode = 0x0; |
1da177e4 LT |
205 | |
206 | /* initialise the io descriptors we need for initialisation */ | |
74b265d4 | 207 | iotable_init(mach_desc, size); |
1da177e4 LT |
208 | iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); |
209 | ||
68d9ab39 BD |
210 | if (cpu_architecture() >= CPU_ARCH_ARMv5) { |
211 | idcode = s3c24xx_read_idcode_v5(); | |
212 | } else { | |
213 | idcode = s3c24xx_read_idcode_v4(); | |
214 | } | |
83f755f5 | 215 | |
3c7d9c81 BD |
216 | arm_pm_restart = s3c24xx_pm_restart; |
217 | ||
74b265d4 | 218 | s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); |
66a9b49a | 219 | } |