[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / plat-omap / include / plat / display.h

/*
 * linux/include/asm-arm/arch-omap/display.h
 *
 * Copyright (C) 2008 Nokia Corporation
 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __ASM_ARCH_OMAP_DISPLAY_H
#define __ASM_ARCH_OMAP_DISPLAY_H

#include <linux/list.h>
#include <linux/kobject.h>
#include <linux/device.h>
#include <asm/atomic.h>

#define DISPC_IRQ_FRAMEDONE		(1 << 0)
#define DISPC_IRQ_VSYNC			(1 << 1)
#define DISPC_IRQ_EVSYNC_EVEN		(1 << 2)
#define DISPC_IRQ_EVSYNC_ODD		(1 << 3)
#define DISPC_IRQ_ACBIAS_COUNT_STAT	(1 << 4)
#define DISPC_IRQ_PROG_LINE_NUM		(1 << 5)
#define DISPC_IRQ_GFX_FIFO_UNDERFLOW	(1 << 6)
#define DISPC_IRQ_GFX_END_WIN		(1 << 7)
#define DISPC_IRQ_PAL_GAMMA_MASK	(1 << 8)
#define DISPC_IRQ_OCP_ERR		(1 << 9)
#define DISPC_IRQ_VID1_FIFO_UNDERFLOW	(1 << 10)
#define DISPC_IRQ_VID1_END_WIN		(1 << 11)
#define DISPC_IRQ_VID2_FIFO_UNDERFLOW	(1 << 12)
#define DISPC_IRQ_VID2_END_WIN		(1 << 13)
#define DISPC_IRQ_SYNC_LOST		(1 << 14)
#define DISPC_IRQ_SYNC_LOST_DIGIT	(1 << 15)
#define DISPC_IRQ_WAKEUP		(1 << 16)

struct omap_dss_device;
struct omap_overlay_manager;

enum omap_display_type {
	OMAP_DISPLAY_TYPE_NONE		= 0,
	OMAP_DISPLAY_TYPE_DPI		= 1 << 0,
	OMAP_DISPLAY_TYPE_DBI		= 1 << 1,
	OMAP_DISPLAY_TYPE_SDI		= 1 << 2,
	OMAP_DISPLAY_TYPE_DSI		= 1 << 3,
	OMAP_DISPLAY_TYPE_VENC		= 1 << 4,
};

enum omap_plane {
	OMAP_DSS_GFX	= 0,
	OMAP_DSS_VIDEO1	= 1,
	OMAP_DSS_VIDEO2	= 2
};

enum omap_channel {
	OMAP_DSS_CHANNEL_LCD	= 0,
	OMAP_DSS_CHANNEL_DIGIT	= 1,
};

enum omap_color_mode {
	OMAP_DSS_COLOR_CLUT1	= 1 << 0,  /* BITMAP 1 */
	OMAP_DSS_COLOR_CLUT2	= 1 << 1,  /* BITMAP 2 */
	OMAP_DSS_COLOR_CLUT4	= 1 << 2,  /* BITMAP 4 */
	OMAP_DSS_COLOR_CLUT8	= 1 << 3,  /* BITMAP 8 */
	OMAP_DSS_COLOR_RGB12U	= 1 << 4,  /* RGB12, 16-bit container */
	OMAP_DSS_COLOR_ARGB16	= 1 << 5,  /* ARGB16 */
	OMAP_DSS_COLOR_RGB16	= 1 << 6,  /* RGB16 */
	OMAP_DSS_COLOR_RGB24U	= 1 << 7,  /* RGB24, 32-bit container */
	OMAP_DSS_COLOR_RGB24P	= 1 << 8,  /* RGB24, 24-bit container */
	OMAP_DSS_COLOR_YUV2	= 1 << 9,  /* YUV2 4:2:2 co-sited */
	OMAP_DSS_COLOR_UYVY	= 1 << 10, /* UYVY 4:2:2 co-sited */
	OMAP_DSS_COLOR_ARGB32	= 1 << 11, /* ARGB32 */
	OMAP_DSS_COLOR_RGBA32	= 1 << 12, /* RGBA32 */
	OMAP_DSS_COLOR_RGBX32	= 1 << 13, /* RGBx32 */

	OMAP_DSS_COLOR_GFX_OMAP2 =
		OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
		OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
		OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
		OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P,

	OMAP_DSS_COLOR_VID_OMAP2 =
		OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
		OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
		OMAP_DSS_COLOR_UYVY,

	OMAP_DSS_COLOR_GFX_OMAP3 =
		OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
		OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
		OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
		OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
		OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
		OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,

	OMAP_DSS_COLOR_VID1_OMAP3 =
		OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
		OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P |
		OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,

	OMAP_DSS_COLOR_VID2_OMAP3 =
		OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
		OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
		OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
		OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 |
		OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
};

enum omap_lcd_display_type {
	OMAP_DSS_LCD_DISPLAY_STN,
	OMAP_DSS_LCD_DISPLAY_TFT,
};

enum omap_dss_load_mode {
	OMAP_DSS_LOAD_CLUT_AND_FRAME	= 0,
	OMAP_DSS_LOAD_CLUT_ONLY		= 1,
	OMAP_DSS_LOAD_FRAME_ONLY	= 2,
	OMAP_DSS_LOAD_CLUT_ONCE_FRAME	= 3,
};

enum omap_dss_trans_key_type {
	OMAP_DSS_COLOR_KEY_GFX_DST = 0,
	OMAP_DSS_COLOR_KEY_VID_SRC = 1,
};

enum omap_rfbi_te_mode {
	OMAP_DSS_RFBI_TE_MODE_1 = 1,
	OMAP_DSS_RFBI_TE_MODE_2 = 2,
};

enum omap_panel_config {
	OMAP_DSS_LCD_IVS		= 1<<0,
	OMAP_DSS_LCD_IHS		= 1<<1,
	OMAP_DSS_LCD_IPC		= 1<<2,
	OMAP_DSS_LCD_IEO		= 1<<3,
	OMAP_DSS_LCD_RF			= 1<<4,
	OMAP_DSS_LCD_ONOFF		= 1<<5,

	OMAP_DSS_LCD_TFT		= 1<<20,
};

enum omap_dss_venc_type {
	OMAP_DSS_VENC_TYPE_COMPOSITE,
	OMAP_DSS_VENC_TYPE_SVIDEO,
};

enum omap_display_caps {
	OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE	= 1 << 0,
	OMAP_DSS_DISPLAY_CAP_TEAR_ELIM		= 1 << 1,
};

enum omap_dss_update_mode {
	OMAP_DSS_UPDATE_DISABLED = 0,
	OMAP_DSS_UPDATE_AUTO,
	OMAP_DSS_UPDATE_MANUAL,
};

enum omap_dss_display_state {
	OMAP_DSS_DISPLAY_DISABLED = 0,
	OMAP_DSS_DISPLAY_ACTIVE,
	OMAP_DSS_DISPLAY_SUSPENDED,
};

/* XXX perhaps this should be removed */
enum omap_dss_overlay_managers {
	OMAP_DSS_OVL_MGR_LCD,
	OMAP_DSS_OVL_MGR_TV,
};

enum omap_dss_rotation_type {
	OMAP_DSS_ROT_DMA = 0,
	OMAP_DSS_ROT_VRFB = 1,
};

/* clockwise rotation angle */
enum omap_dss_rotation_angle {
	OMAP_DSS_ROT_0   = 0,
	OMAP_DSS_ROT_90  = 1,
	OMAP_DSS_ROT_180 = 2,
	OMAP_DSS_ROT_270 = 3,
};

enum omap_overlay_caps {
	OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
	OMAP_DSS_OVL_CAP_DISPC = 1 << 1,
};

enum omap_overlay_manager_caps {
	OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
};

/* RFBI */

struct rfbi_timings {
	int cs_on_time;
	int cs_off_time;
	int we_on_time;
	int we_off_time;
	int re_on_time;
	int re_off_time;
	int we_cycle_time;
	int re_cycle_time;
	int cs_pulse_width;
	int access_time;

	int clk_div;

	u32 tim[5];             /* set by rfbi_convert_timings() */

	int converted;
};

void omap_rfbi_write_command(const void *buf, u32 len);
void omap_rfbi_read_data(void *buf, u32 len);
void omap_rfbi_write_data(const void *buf, u32 len);
void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
		u16 x, u16 y,
		u16 w, u16 h);
int omap_rfbi_enable_te(bool enable, unsigned line);
int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
			     unsigned hs_pulse_time, unsigned vs_pulse_time,
			     int hs_pol_inv, int vs_pol_inv, int extif_div);

/* DSI */
void dsi_bus_lock(void);
void dsi_bus_unlock(void);
int dsi_vc_dcs_write(int channel, u8 *data, int len);
int dsi_vc_dcs_write_0(int channel, u8 dcs_cmd);
int dsi_vc_dcs_write_1(int channel, u8 dcs_cmd, u8 param);
int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len);
int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen);
int dsi_vc_dcs_read_1(int channel, u8 dcs_cmd, u8 *data);
int dsi_vc_set_max_rx_packet_size(int channel, u16 len);
int dsi_vc_send_null(int channel);
int dsi_vc_send_bta_sync(int channel);

/* Board specific data */
struct omap_dss_board_info {
	int (*get_last_off_on_transaction_id)(struct device *dev);
	int num_devices;
	struct omap_dss_device **devices;
	struct omap_dss_device *default_device;
};

struct omap_video_timings {
	/* Unit: pixels */
	u16 x_res;
	/* Unit: pixels */
	u16 y_res;
	/* Unit: KHz */
	u32 pixel_clock;
	/* Unit: pixel clocks */
	u16 hsw;	/* Horizontal synchronization pulse width */
	/* Unit: pixel clocks */
	u16 hfp;	/* Horizontal front porch */
	/* Unit: pixel clocks */
	u16 hbp;	/* Horizontal back porch */
	/* Unit: line clocks */
	u16 vsw;	/* Vertical synchronization pulse width */
	/* Unit: line clocks */
	u16 vfp;	/* Vertical front porch */
	/* Unit: line clocks */
	u16 vbp;	/* Vertical back porch */
};

#ifdef CONFIG_OMAP2_DSS_VENC
/* Hardcoded timings for tv modes. Venc only uses these to
 * identify the mode, and does not actually use the configs
 * itself. However, the configs should be something that
 * a normal monitor can also show */
const extern struct omap_video_timings omap_dss_pal_timings;
const extern struct omap_video_timings omap_dss_ntsc_timings;
#endif

struct omap_overlay_info {
	bool enabled;

	u32 paddr;
	void __iomem *vaddr;
	u16 screen_width;
	u16 width;
	u16 height;
	enum omap_color_mode color_mode;
	u8 rotation;
	enum omap_dss_rotation_type rotation_type;
	bool mirror;

	u16 pos_x;
	u16 pos_y;
	u16 out_width;	/* if 0, out_width == width */
	u16 out_height;	/* if 0, out_height == height */
	u8 global_alpha;
};

struct omap_overlay {
	struct kobject kobj;
	struct list_head list;

	/* static fields */
	const char *name;
	int id;
	enum omap_color_mode supported_modes;
	enum omap_overlay_caps caps;

	/* dynamic fields */
	struct omap_overlay_manager *manager;
	struct omap_overlay_info info;

	/* if true, info has been changed, but not applied() yet */
	bool info_dirty;

	int (*set_manager)(struct omap_overlay *ovl,
		struct omap_overlay_manager *mgr);
	int (*unset_manager)(struct omap_overlay *ovl);

	int (*set_overlay_info)(struct omap_overlay *ovl,
			struct omap_overlay_info *info);
	void (*get_overlay_info)(struct omap_overlay *ovl,
			struct omap_overlay_info *info);

	int (*wait_for_go)(struct omap_overlay *ovl);
};

struct omap_overlay_manager_info {
	u32 default_color;

	enum omap_dss_trans_key_type trans_key_type;
	u32 trans_key;
	bool trans_enabled;

	bool alpha_enabled;
};

struct omap_overlay_manager {
	struct kobject kobj;
	struct list_head list;

	/* static fields */
	const char *name;
	int id;
	enum omap_overlay_manager_caps caps;
	int num_overlays;
	struct omap_overlay **overlays;
	enum omap_display_type supported_displays;

	/* dynamic fields */
	struct omap_dss_device *device;
	struct omap_overlay_manager_info info;

	bool device_changed;
	/* if true, info has been changed but not applied() yet */
	bool info_dirty;

	int (*set_device)(struct omap_overlay_manager *mgr,
		struct omap_dss_device *dssdev);
	int (*unset_device)(struct omap_overlay_manager *mgr);

	int (*set_manager_info)(struct omap_overlay_manager *mgr,
			struct omap_overlay_manager_info *info);
	void (*get_manager_info)(struct omap_overlay_manager *mgr,
			struct omap_overlay_manager_info *info);

	int (*apply)(struct omap_overlay_manager *mgr);
	int (*wait_for_go)(struct omap_overlay_manager *mgr);
	int (*wait_for_vsync)(struct omap_overlay_manager *mgr);

	int (*enable)(struct omap_overlay_manager *mgr);
	int (*disable)(struct omap_overlay_manager *mgr);
};

struct omap_dss_device {
	struct device dev;

	enum omap_display_type type;

	union {
		struct {
			u8 data_lines;
		} dpi;

		struct {
			u8 channel;
			u8 data_lines;
		} rfbi;

		struct {
			u8 datapairs;
		} sdi;

		struct {
			u8 clk_lane;
			u8 clk_pol;
			u8 data1_lane;
			u8 data1_pol;
			u8 data2_lane;
			u8 data2_pol;

			struct {
				u16 regn;
				u16 regm;
				u16 regm3;
				u16 regm4;

				u16 lp_clk_div;

				u16 lck_div;
				u16 pck_div;
			} div;

			bool ext_te;
			u8 ext_te_gpio;
		} dsi;

		struct {
			enum omap_dss_venc_type type;
			bool invert_polarity;
		} venc;
	} phy;

	struct {
		struct omap_video_timings timings;

		int acbi;	/* ac-bias pin transitions per interrupt */
		/* Unit: line clocks */
		int acb;	/* ac-bias pin frequency */

		enum omap_panel_config config;

		u8 recommended_bpp;
	} panel;

	struct {
		u8 pixel_size;
		struct rfbi_timings rfbi_timings;
	} ctrl;

	int reset_gpio;

	int max_backlight_level;

	const char *name;

	/* used to match device to driver */
	const char *driver_name;

	void *data;

	struct omap_dss_driver *driver;

	/* helper variable for driver suspend/resume */
	bool activate_after_resume;

	enum omap_display_caps caps;

	struct omap_overlay_manager *manager;

	enum omap_dss_display_state state;

	int (*enable)(struct omap_dss_device *dssdev);
	void (*disable)(struct omap_dss_device *dssdev);

	int (*suspend)(struct omap_dss_device *dssdev);
	int (*resume)(struct omap_dss_device *dssdev);

	void (*get_resolution)(struct omap_dss_device *dssdev,
			u16 *xres, u16 *yres);
	int (*get_recommended_bpp)(struct omap_dss_device *dssdev);

	int (*check_timings)(struct omap_dss_device *dssdev,
			struct omap_video_timings *timings);
	void (*set_timings)(struct omap_dss_device *dssdev,
			struct omap_video_timings *timings);
	void (*get_timings)(struct omap_dss_device *dssdev,
			struct omap_video_timings *timings);
	int (*update)(struct omap_dss_device *dssdev,
			       u16 x, u16 y, u16 w, u16 h);
	int (*sync)(struct omap_dss_device *dssdev);

	int (*set_update_mode)(struct omap_dss_device *dssdev,
			enum omap_dss_update_mode);
	enum omap_dss_update_mode (*get_update_mode)
		(struct omap_dss_device *dssdev);

	int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
	int (*get_te)(struct omap_dss_device *dssdev);

	int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
	u32 (*get_wss)(struct omap_dss_device *dssdev);

	/* platform specific  */
	int (*platform_enable)(struct omap_dss_device *dssdev);
	void (*platform_disable)(struct omap_dss_device *dssdev);
	int (*set_backlight)(struct omap_dss_device *dssdev, int level);
	int (*get_backlight)(struct omap_dss_device *dssdev);
};

struct omap_dss_driver {
	struct device_driver driver;

	int (*probe)(struct omap_dss_device *);
	void (*remove)(struct omap_dss_device *);

	int (*enable)(struct omap_dss_device *display);
	void (*disable)(struct omap_dss_device *display);
	int (*suspend)(struct omap_dss_device *display);
	int (*resume)(struct omap_dss_device *display);
	int (*run_test)(struct omap_dss_device *display, int test);

	void (*setup_update)(struct omap_dss_device *dssdev,
			u16 x, u16 y, u16 w, u16 h);

	int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
	int (*wait_for_te)(struct omap_dss_device *dssdev);

	u8 (*get_rotate)(struct omap_dss_device *dssdev);
	int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);

	bool (*get_mirror)(struct omap_dss_device *dssdev);
	int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);

	int (*memory_read)(struct omap_dss_device *dssdev,
			void *buf, size_t size,
			u16 x, u16 y, u16 w, u16 h);
};

int omap_dss_register_driver(struct omap_dss_driver *);
void omap_dss_unregister_driver(struct omap_dss_driver *);

int omap_dss_register_device(struct omap_dss_device *);
void omap_dss_unregister_device(struct omap_dss_device *);

void omap_dss_get_device(struct omap_dss_device *dssdev);
void omap_dss_put_device(struct omap_dss_device *dssdev);
#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
struct omap_dss_device *omap_dss_find_device(void *data,
		int (*match)(struct omap_dss_device *dssdev, void *data));

int omap_dss_start_device(struct omap_dss_device *dssdev);
void omap_dss_stop_device(struct omap_dss_device *dssdev);

int omap_dss_get_num_overlay_managers(void);
struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);

int omap_dss_get_num_overlays(void);
struct omap_overlay *omap_dss_get_overlay(int num);

typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);

int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
		unsigned long timeout);

#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
#define to_dss_device(x) container_of((x), struct omap_dss_device, dev)

void omapdss_dsi_vc_enable_hs(int channel, bool enable);

#endif
Commit	Line	Data
559d6701 TV	1	/*
	2	* linux/include/asm-arm/arch-omap/display.h
	3	*
	4	* Copyright (C) 2008 Nokia Corporation
	5	* Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License version 2 as published by
	9	* the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	* more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along with
	17	* this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#ifndef __ASM_ARCH_OMAP_DISPLAY_H
	21	#define __ASM_ARCH_OMAP_DISPLAY_H
	22
	23	#include <linux/list.h>
	24	#include <linux/kobject.h>
	25	#include <linux/device.h>
	26	#include <asm/atomic.h>
	27
	28	#define DISPC_IRQ_FRAMEDONE (1 << 0)
	29	#define DISPC_IRQ_VSYNC (1 << 1)
	30	#define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
	31	#define DISPC_IRQ_EVSYNC_ODD (1 << 3)
	32	#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
	33	#define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
	34	#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
	35	#define DISPC_IRQ_GFX_END_WIN (1 << 7)
	36	#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
	37	#define DISPC_IRQ_OCP_ERR (1 << 9)
	38	#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
	39	#define DISPC_IRQ_VID1_END_WIN (1 << 11)
	40	#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
	41	#define DISPC_IRQ_VID2_END_WIN (1 << 13)
	42	#define DISPC_IRQ_SYNC_LOST (1 << 14)
	43	#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
	44	#define DISPC_IRQ_WAKEUP (1 << 16)
	45
	46	struct omap_dss_device;
	47	struct omap_overlay_manager;
	48
	49	enum omap_display_type {
	50	OMAP_DISPLAY_TYPE_NONE = 0,
	51	OMAP_DISPLAY_TYPE_DPI = 1 << 0,
	52	OMAP_DISPLAY_TYPE_DBI = 1 << 1,
	53	OMAP_DISPLAY_TYPE_SDI = 1 << 2,
	54	OMAP_DISPLAY_TYPE_DSI = 1 << 3,
	55	OMAP_DISPLAY_TYPE_VENC = 1 << 4,
	56	};
	57
	58	enum omap_plane {
	59	OMAP_DSS_GFX = 0,
	60	OMAP_DSS_VIDEO1 = 1,
	61	OMAP_DSS_VIDEO2 = 2
	62	};
	63
	64	enum omap_channel {
65	OMAP_DSS_CHANNEL_LCD = 0,
66	OMAP_DSS_CHANNEL_DIGIT = 1,
67	};
68
69	enum omap_color_mode {
70	OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
71	OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
72	OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
73	OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
74	OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
75	OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
76	OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
77	OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
78	OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
79	OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
80	OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
81	OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
82	OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
83	OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
84
85	OMAP_DSS_COLOR_GFX_OMAP2 =
86	OMAP_DSS_COLOR_CLUT1 \| OMAP_DSS_COLOR_CLUT2 \|
87	OMAP_DSS_COLOR_CLUT4 \| OMAP_DSS_COLOR_CLUT8 \|
88	OMAP_DSS_COLOR_RGB12U \| OMAP_DSS_COLOR_RGB16 \|
89	OMAP_DSS_COLOR_RGB24U \| OMAP_DSS_COLOR_RGB24P,
90
91	OMAP_DSS_COLOR_VID_OMAP2 =
92	OMAP_DSS_COLOR_RGB16 \| OMAP_DSS_COLOR_RGB24U \|
93	OMAP_DSS_COLOR_RGB24P \| OMAP_DSS_COLOR_YUV2 \|
94	OMAP_DSS_COLOR_UYVY,
95
96	OMAP_DSS_COLOR_GFX_OMAP3 =
97	OMAP_DSS_COLOR_CLUT1 \| OMAP_DSS_COLOR_CLUT2 \|
98	OMAP_DSS_COLOR_CLUT4 \| OMAP_DSS_COLOR_CLUT8 \|
99	OMAP_DSS_COLOR_RGB12U \| OMAP_DSS_COLOR_ARGB16 \|
100	OMAP_DSS_COLOR_RGB16 \| OMAP_DSS_COLOR_RGB24U \|
101	OMAP_DSS_COLOR_RGB24P \| OMAP_DSS_COLOR_ARGB32 \|
102	OMAP_DSS_COLOR_RGBA32 \| OMAP_DSS_COLOR_RGBX32,
103
104	OMAP_DSS_COLOR_VID1_OMAP3 =
105	OMAP_DSS_COLOR_RGB12U \| OMAP_DSS_COLOR_RGB16 \|
106	OMAP_DSS_COLOR_RGB24U \| OMAP_DSS_COLOR_RGB24P \|
107	OMAP_DSS_COLOR_YUV2 \| OMAP_DSS_COLOR_UYVY,
108
109	OMAP_DSS_COLOR_VID2_OMAP3 =
110	OMAP_DSS_COLOR_RGB12U \| OMAP_DSS_COLOR_ARGB16 \|
111	OMAP_DSS_COLOR_RGB16 \| OMAP_DSS_COLOR_RGB24U \|
112	OMAP_DSS_COLOR_RGB24P \| OMAP_DSS_COLOR_YUV2 \|
113	OMAP_DSS_COLOR_UYVY \| OMAP_DSS_COLOR_ARGB32 \|
114	OMAP_DSS_COLOR_RGBA32 \| OMAP_DSS_COLOR_RGBX32,
115	};
116
117	enum omap_lcd_display_type {
118	OMAP_DSS_LCD_DISPLAY_STN,
119	OMAP_DSS_LCD_DISPLAY_TFT,
120	};
121
122	enum omap_dss_load_mode {
123	OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
124	OMAP_DSS_LOAD_CLUT_ONLY = 1,
125	OMAP_DSS_LOAD_FRAME_ONLY = 2,
126	OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
127	};
128
129	enum omap_dss_trans_key_type {
130	OMAP_DSS_COLOR_KEY_GFX_DST = 0,
131	OMAP_DSS_COLOR_KEY_VID_SRC = 1,
132	};
133
134	enum omap_rfbi_te_mode {
135	OMAP_DSS_RFBI_TE_MODE_1 = 1,
136	OMAP_DSS_RFBI_TE_MODE_2 = 2,
137	};
138
139	enum omap_panel_config {
140	OMAP_DSS_LCD_IVS = 1<<0,
141	OMAP_DSS_LCD_IHS = 1<<1,
142	OMAP_DSS_LCD_IPC = 1<<2,
143	OMAP_DSS_LCD_IEO = 1<<3,
144	OMAP_DSS_LCD_RF = 1<<4,
145	OMAP_DSS_LCD_ONOFF = 1<<5,
146
147	OMAP_DSS_LCD_TFT = 1<<20,
148	};
149
150	enum omap_dss_venc_type {
151	OMAP_DSS_VENC_TYPE_COMPOSITE,
152	OMAP_DSS_VENC_TYPE_SVIDEO,
153	};
154
155	enum omap_display_caps {
156	OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
157	OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
158	};
159
160	enum omap_dss_update_mode {
161	OMAP_DSS_UPDATE_DISABLED = 0,
162	OMAP_DSS_UPDATE_AUTO,
163	OMAP_DSS_UPDATE_MANUAL,
164	};
165
166	enum omap_dss_display_state {
167	OMAP_DSS_DISPLAY_DISABLED = 0,
168	OMAP_DSS_DISPLAY_ACTIVE,
169	OMAP_DSS_DISPLAY_SUSPENDED,
170	};
171
172	/* XXX perhaps this should be removed */
173	enum omap_dss_overlay_managers {
174	OMAP_DSS_OVL_MGR_LCD,
175	OMAP_DSS_OVL_MGR_TV,
176	};
177
178	enum omap_dss_rotation_type {
179	OMAP_DSS_ROT_DMA = 0,
180	OMAP_DSS_ROT_VRFB = 1,
181	};
182
183	/* clockwise rotation angle */
184	enum omap_dss_rotation_angle {
185	OMAP_DSS_ROT_0 = 0,
186	OMAP_DSS_ROT_90 = 1,
187	OMAP_DSS_ROT_180 = 2,
188	OMAP_DSS_ROT_270 = 3,
189	};
190
191	enum omap_overlay_caps {
192	OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
193	OMAP_DSS_OVL_CAP_DISPC = 1 << 1,
194	};
195
196	enum omap_overlay_manager_caps {
197	OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
198	};
199
200	/* RFBI */
201
202	struct rfbi_timings {
203	int cs_on_time;
204	int cs_off_time;
205	int we_on_time;
206	int we_off_time;
207	int re_on_time;
208	int re_off_time;
209	int we_cycle_time;
210	int re_cycle_time;
211	int cs_pulse_width;
212	int access_time;
213
214	int clk_div;
215
216	u32 tim[5]; /* set by rfbi_convert_timings() */
217
218	int converted;
219	};
220
221	void omap_rfbi_write_command(const void *buf, u32 len);
222	void omap_rfbi_read_data(void *buf, u32 len);
223	void omap_rfbi_write_data(const void *buf, u32 len);
224	void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
225	u16 x, u16 y,
226	u16 w, u16 h);
227	int omap_rfbi_enable_te(bool enable, unsigned line);
228	int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
229	unsigned hs_pulse_time, unsigned vs_pulse_time,
230	int hs_pol_inv, int vs_pol_inv, int extif_div);
231
232	/* DSI */
233	void dsi_bus_lock(void);
234	void dsi_bus_unlock(void);
235	int dsi_vc_dcs_write(int channel, u8 *data, int len);
828c48f8 TV	236	int dsi_vc_dcs_write_0(int channel, u8 dcs_cmd);
828c48f8 TV	237	int dsi_vc_dcs_write_1(int channel, u8 dcs_cmd, u8 param);
559d6701 TV	238	int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len);
559d6701 TV	239	int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen);
828c48f8	240	int dsi_vc_dcs_read_1(int channel, u8 dcs_cmd, u8 *data);
559d6701 TV	241	int dsi_vc_set_max_rx_packet_size(int channel, u16 len);
	242	int dsi_vc_send_null(int channel);
	243	int dsi_vc_send_bta_sync(int channel);
	244
	245	/* Board specific data */
	246	struct omap_dss_board_info {
	247	int (get_last_off_on_transaction_id)(struct device dev);
	248	int num_devices;
	249	struct omap_dss_device **devices;
	250	struct omap_dss_device *default_device;
	251	};
	252
	253	struct omap_video_timings {
	254	/* Unit: pixels */
	255	u16 x_res;
	256	/* Unit: pixels */
	257	u16 y_res;
	258	/* Unit: KHz */
	259	u32 pixel_clock;
	260	/* Unit: pixel clocks */
	261	u16 hsw; /* Horizontal synchronization pulse width */
	262	/* Unit: pixel clocks */
	263	u16 hfp; /* Horizontal front porch */
	264	/* Unit: pixel clocks */
	265	u16 hbp; /* Horizontal back porch */
	266	/* Unit: line clocks */
	267	u16 vsw; /* Vertical synchronization pulse width */
	268	/* Unit: line clocks */
	269	u16 vfp; /* Vertical front porch */
	270	/* Unit: line clocks */
	271	u16 vbp; /* Vertical back porch */
	272	};
	273
	274	#ifdef CONFIG_OMAP2_DSS_VENC
	275	/* Hardcoded timings for tv modes. Venc only uses these to
	276	* identify the mode, and does not actually use the configs
	277	* itself. However, the configs should be something that
	278	* a normal monitor can also show */
	279	const extern struct omap_video_timings omap_dss_pal_timings;
	280	const extern struct omap_video_timings omap_dss_ntsc_timings;
	281	#endif
	282
	283	struct omap_overlay_info {
	284	bool enabled;
	285
	286	u32 paddr;
	287	void __iomem *vaddr;
	288	u16 screen_width;
	289	u16 width;
	290	u16 height;
	291	enum omap_color_mode color_mode;
	292	u8 rotation;
	293	enum omap_dss_rotation_type rotation_type;
	294	bool mirror;
	295
	296	u16 pos_x;
	297	u16 pos_y;
	298	u16 out_width; /* if 0, out_width == width */
	299	u16 out_height; /* if 0, out_height == height */
	300	u8 global_alpha;
	301	};
	302
	303	struct omap_overlay {
	304	struct kobject kobj;
305	struct list_head list;
306
307	/* static fields */
308	const char *name;
309	int id;
310	enum omap_color_mode supported_modes;
311	enum omap_overlay_caps caps;
312
313	/* dynamic fields */
314	struct omap_overlay_manager *manager;
315	struct omap_overlay_info info;
316
317	/* if true, info has been changed, but not applied() yet */
318	bool info_dirty;
319
320	int (set_manager)(struct omap_overlay ovl,
321	struct omap_overlay_manager *mgr);
322	int (unset_manager)(struct omap_overlay ovl);
323
324	int (set_overlay_info)(struct omap_overlay ovl,
325	struct omap_overlay_info *info);
326	void (get_overlay_info)(struct omap_overlay ovl,
327	struct omap_overlay_info *info);
328
329	int (wait_for_go)(struct omap_overlay ovl);
330	};
331
332	struct omap_overlay_manager_info {
333	u32 default_color;
334
335	enum omap_dss_trans_key_type trans_key_type;
336	u32 trans_key;
337	bool trans_enabled;
338
339	bool alpha_enabled;
340	};
341
342	struct omap_overlay_manager {
343	struct kobject kobj;
344	struct list_head list;
345
346	/* static fields */
347	const char *name;
348	int id;
349	enum omap_overlay_manager_caps caps;
350	int num_overlays;
351	struct omap_overlay **overlays;
352	enum omap_display_type supported_displays;
353
354	/* dynamic fields */
355	struct omap_dss_device *device;
356	struct omap_overlay_manager_info info;
357
358	bool device_changed;
359	/* if true, info has been changed but not applied() yet */
360	bool info_dirty;
361
362	int (set_device)(struct omap_overlay_manager mgr,
363	struct omap_dss_device *dssdev);
364	int (unset_device)(struct omap_overlay_manager mgr);
365
366	int (set_manager_info)(struct omap_overlay_manager mgr,
367	struct omap_overlay_manager_info *info);
368	void (get_manager_info)(struct omap_overlay_manager mgr,
369	struct omap_overlay_manager_info *info);
370
371	int (apply)(struct omap_overlay_manager mgr);
372	int (wait_for_go)(struct omap_overlay_manager mgr);
3f71cbe7	373	int (wait_for_vsync)(struct omap_overlay_manager mgr);
a2faee84 TV	374
	375	int (enable)(struct omap_overlay_manager mgr);
	376	int (disable)(struct omap_overlay_manager mgr);
559d6701 TV	377	};
	378
	379	struct omap_dss_device {
	380	struct device dev;
	381
	382	enum omap_display_type type;
	383
	384	union {
	385	struct {
	386	u8 data_lines;
	387	} dpi;
	388
	389	struct {
	390	u8 channel;
	391	u8 data_lines;
	392	} rfbi;
	393
	394	struct {
	395	u8 datapairs;
	396	} sdi;
	397
	398	struct {
	399	u8 clk_lane;
	400	u8 clk_pol;
	401	u8 data1_lane;
	402	u8 data1_pol;
	403	u8 data2_lane;
	404	u8 data2_pol;
	405
	406	struct {
	407	u16 regn;
	408	u16 regm;
	409	u16 regm3;
	410	u16 regm4;
	411
	412	u16 lp_clk_div;
	413
	414	u16 lck_div;
	415	u16 pck_div;
	416	} div;
	417
	418	bool ext_te;
	419	u8 ext_te_gpio;
	420	} dsi;
	421
	422	struct {
	423	enum omap_dss_venc_type type;
	424	bool invert_polarity;
	425	} venc;
	426	} phy;
	427
	428	struct {
	429	struct omap_video_timings timings;
	430
	431	int acbi; /* ac-bias pin transitions per interrupt */
	432	/* Unit: line clocks */
	433	int acb; /* ac-bias pin frequency */
	434
	435	enum omap_panel_config config;
	436
	437	u8 recommended_bpp;
559d6701 TV	438	} panel;
	439
	440	struct {
	441	u8 pixel_size;
	442	struct rfbi_timings rfbi_timings;
559d6701 TV	443	} ctrl;
	444
	445	int reset_gpio;
	446
	447	int max_backlight_level;
	448
	449	const char *name;
	450
	451	/* used to match device to driver */
	452	const char *driver_name;
	453
	454	void *data;
	455
	456	struct omap_dss_driver *driver;
	457
	458	/* helper variable for driver suspend/resume */
	459	bool activate_after_resume;
	460
	461	enum omap_display_caps caps;
	462
	463	struct omap_overlay_manager *manager;
	464
	465	enum omap_dss_display_state state;
	466
	467	int (enable)(struct omap_dss_device dssdev);
	468	void (disable)(struct omap_dss_device dssdev);
	469
	470	int (suspend)(struct omap_dss_device dssdev);
	471	int (resume)(struct omap_dss_device dssdev);
	472
	473	void (get_resolution)(struct omap_dss_device dssdev,
	474	u16 xres, u16 yres);
	475	int (get_recommended_bpp)(struct omap_dss_device dssdev);
	476
	477	int (check_timings)(struct omap_dss_device dssdev,
	478	struct omap_video_timings *timings);
	479	void (set_timings)(struct omap_dss_device dssdev,
	480	struct omap_video_timings *timings);
	481	void (get_timings)(struct omap_dss_device dssdev,
	482	struct omap_video_timings *timings);
	483	int (update)(struct omap_dss_device dssdev,
	484	u16 x, u16 y, u16 w, u16 h);
	485	int (sync)(struct omap_dss_device dssdev);
559d6701 TV	486
	487	int (set_update_mode)(struct omap_dss_device dssdev,
	488	enum omap_dss_update_mode);
	489	enum omap_dss_update_mode (*get_update_mode)
	490	(struct omap_dss_device *dssdev);
	491
	492	int (enable_te)(struct omap_dss_device dssdev, bool enable);
	493	int (get_te)(struct omap_dss_device dssdev);
	494
559d6701 TV	495	int (set_wss)(struct omap_dss_device dssdev, u32 wss);
	496	u32 (get_wss)(struct omap_dss_device dssdev);
	497
	498	/* platform specific */
	499	int (platform_enable)(struct omap_dss_device dssdev);
	500	void (platform_disable)(struct omap_dss_device dssdev);
	501	int (set_backlight)(struct omap_dss_device dssdev, int level);
	502	int (get_backlight)(struct omap_dss_device dssdev);
	503	};
	504
	505	struct omap_dss_driver {
	506	struct device_driver driver;
	507
	508	int (probe)(struct omap_dss_device );
	509	void (remove)(struct omap_dss_device );
	510
	511	int (enable)(struct omap_dss_device display);
	512	void (disable)(struct omap_dss_device display);
	513	int (suspend)(struct omap_dss_device display);
	514	int (resume)(struct omap_dss_device display);
	515	int (run_test)(struct omap_dss_device display, int test);
	516
	517	void (setup_update)(struct omap_dss_device dssdev,
	518	u16 x, u16 y, u16 w, u16 h);
	519
	520	int (enable_te)(struct omap_dss_device dssdev, bool enable);
	521	int (wait_for_te)(struct omap_dss_device dssdev);
	522
	523	u8 (get_rotate)(struct omap_dss_device dssdev);
	524	int (set_rotate)(struct omap_dss_device dssdev, u8 rotate);
	525
	526	bool (get_mirror)(struct omap_dss_device dssdev);
	527	int (set_mirror)(struct omap_dss_device dssdev, bool enable);
	528
	529	int (memory_read)(struct omap_dss_device dssdev,
	530	void *buf, size_t size,
	531	u16 x, u16 y, u16 w, u16 h);
	532	};
	533
	534	int omap_dss_register_driver(struct omap_dss_driver *);
	535	void omap_dss_unregister_driver(struct omap_dss_driver *);
	536
	537	int omap_dss_register_device(struct omap_dss_device *);
	538	void omap_dss_unregister_device(struct omap_dss_device *);
	539
	540	void omap_dss_get_device(struct omap_dss_device *dssdev);
	541	void omap_dss_put_device(struct omap_dss_device *dssdev);
	542	#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
	543	struct omap_dss_device omap_dss_get_next_device(struct omap_dss_device from);
	544	struct omap_dss_device omap_dss_find_device(void data,
	545	int (match)(struct omap_dss_device dssdev, void *data));
	546
	547	int omap_dss_start_device(struct omap_dss_device *dssdev);
	548	void omap_dss_stop_device(struct omap_dss_device *dssdev);
	549
	550	int omap_dss_get_num_overlay_managers(void);
	551	struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
	552
	553	int omap_dss_get_num_overlays(void);
	554	struct omap_overlay *omap_dss_get_overlay(int num);
	555
	556	typedef void (omap_dispc_isr_t) (void arg, u32 mask);
	557	int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
	558	int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
559
560	int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
561	int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
562	unsigned long timeout);
563
564	#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
565	#define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
566
61140c9a TV	567	void omapdss_dsi_vc_enable_hs(int channel, bool enable);
61140c9a TV	568
559d6701	569	#endif