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arm: omap: gpio: don't access irq_desc array directly
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / plat-omap / gpio.c
CommitLineData
5e1c5ff4
TL		 1/*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
92105bb7 6 * Copyright (C) 2003-2005 Nokia Corporation
96de0e25 7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
5e1c5ff4 8 *
44169075
SS		 9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 *
5e1c5ff4
TL		 12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
5e1c5ff4
TL		 17#include <linux/init.h>
18#include <linux/module.h>
5e1c5ff4 19#include <linux/interrupt.h>
92105bb7
TL		 20#include <linux/sysdev.h>
21#include <linux/err.h>
f8ce2547 22#include <linux/clk.h>
fced80c7 23#include <linux/io.h>
77640aab
VC		 24#include <linux/slab.h>
25#include <linux/pm_runtime.h>
5e1c5ff4 26
a09e64fb 27#include <mach/hardware.h>
5e1c5ff4 28#include <asm/irq.h>
a09e64fb
RK		 29#include <mach/irqs.h>
30#include <mach/gpio.h>
5e1c5ff4
TL		 31#include <asm/mach/irq.h>
32
5e1c5ff4
TL		 33/*
34 * OMAP1510 GPIO registers
35 */
5e1c5ff4
TL		 36#define OMAP1510_GPIO_DATA_INPUT 0x00
37#define OMAP1510_GPIO_DATA_OUTPUT 0x04
38#define OMAP1510_GPIO_DIR_CONTROL 0x08
39#define OMAP1510_GPIO_INT_CONTROL 0x0c
40#define OMAP1510_GPIO_INT_MASK 0x10
41#define OMAP1510_GPIO_INT_STATUS 0x14
42#define OMAP1510_GPIO_PIN_CONTROL 0x18
43
44#define OMAP1510_IH_GPIO_BASE 64
45
46/*
47 * OMAP1610 specific GPIO registers
48 */
5e1c5ff4
TL		 49#define OMAP1610_GPIO_REVISION 0x0000
50#define OMAP1610_GPIO_SYSCONFIG 0x0010
51#define OMAP1610_GPIO_SYSSTATUS 0x0014
52#define OMAP1610_GPIO_IRQSTATUS1 0x0018
53#define OMAP1610_GPIO_IRQENABLE1 0x001c
92105bb7 54#define OMAP1610_GPIO_WAKEUPENABLE 0x0028
5e1c5ff4
TL		 55#define OMAP1610_GPIO_DATAIN 0x002c
56#define OMAP1610_GPIO_DATAOUT 0x0030
57#define OMAP1610_GPIO_DIRECTION 0x0034
58#define OMAP1610_GPIO_EDGE_CTRL1 0x0038
59#define OMAP1610_GPIO_EDGE_CTRL2 0x003c
60#define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
92105bb7 61#define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
5e1c5ff4
TL		 62#define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
63#define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
92105bb7 64#define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
5e1c5ff4
TL		 65#define OMAP1610_GPIO_SET_DATAOUT 0x00f0
66
67/*
7c006926 68 * OMAP7XX specific GPIO registers
5e1c5ff4 69 */
7c006926
AB		 70#define OMAP7XX_GPIO_DATA_INPUT 0x00
71#define OMAP7XX_GPIO_DATA_OUTPUT 0x04
72#define OMAP7XX_GPIO_DIR_CONTROL 0x08
73#define OMAP7XX_GPIO_INT_CONTROL 0x0c
74#define OMAP7XX_GPIO_INT_MASK 0x10
75#define OMAP7XX_GPIO_INT_STATUS 0x14
5e1c5ff4 76
92105bb7 77/*
77640aab 78 * omap2+ specific GPIO registers
92105bb7 79 */
92105bb7 80#define OMAP24XX_GPIO_REVISION 0x0000
92105bb7 81#define OMAP24XX_GPIO_IRQSTATUS1 0x0018
bee7930f
HD		 82#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
83#define OMAP24XX_GPIO_IRQENABLE2 0x002c
92105bb7 84#define OMAP24XX_GPIO_IRQENABLE1 0x001c
723fdb78 85#define OMAP24XX_GPIO_WAKE_EN 0x0020
92105bb7
TL		 86#define OMAP24XX_GPIO_CTRL 0x0030
87#define OMAP24XX_GPIO_OE 0x0034
88#define OMAP24XX_GPIO_DATAIN 0x0038
89#define OMAP24XX_GPIO_DATAOUT 0x003c
90#define OMAP24XX_GPIO_LEVELDETECT0 0x0040
91#define OMAP24XX_GPIO_LEVELDETECT1 0x0044
92#define OMAP24XX_GPIO_RISINGDETECT 0x0048
93#define OMAP24XX_GPIO_FALLINGDETECT 0x004c
5eb3bb9c
KH		 94#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
95#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
92105bb7
TL		 96#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
97#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
98#define OMAP24XX_GPIO_CLEARWKUENA 0x0080
99#define OMAP24XX_GPIO_SETWKUENA 0x0084
100#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
101#define OMAP24XX_GPIO_SETDATAOUT 0x0094
102
78a1a6d3 103#define OMAP4_GPIO_REVISION 0x0000
78a1a6d3
SR		 104#define OMAP4_GPIO_EOI 0x0020
105#define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
106#define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
107#define OMAP4_GPIO_IRQSTATUS0 0x002c
108#define OMAP4_GPIO_IRQSTATUS1 0x0030
109#define OMAP4_GPIO_IRQSTATUSSET0 0x0034
110#define OMAP4_GPIO_IRQSTATUSSET1 0x0038
111#define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
112#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
113#define OMAP4_GPIO_IRQWAKEN0 0x0044
114#define OMAP4_GPIO_IRQWAKEN1 0x0048
9f096868
C		 115#define OMAP4_GPIO_IRQENABLE1 0x011c
116#define OMAP4_GPIO_WAKE_EN 0x0120
117#define OMAP4_GPIO_IRQSTATUS2 0x0128
118#define OMAP4_GPIO_IRQENABLE2 0x012c
78a1a6d3
SR		 119#define OMAP4_GPIO_CTRL 0x0130
120#define OMAP4_GPIO_OE 0x0134
121#define OMAP4_GPIO_DATAIN 0x0138
122#define OMAP4_GPIO_DATAOUT 0x013c
123#define OMAP4_GPIO_LEVELDETECT0 0x0140
124#define OMAP4_GPIO_LEVELDETECT1 0x0144
125#define OMAP4_GPIO_RISINGDETECT 0x0148
126#define OMAP4_GPIO_FALLINGDETECT 0x014c
127#define OMAP4_GPIO_DEBOUNCENABLE 0x0150
128#define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
9f096868
C		 129#define OMAP4_GPIO_CLEARIRQENABLE1 0x0160
130#define OMAP4_GPIO_SETIRQENABLE1 0x0164
131#define OMAP4_GPIO_CLEARWKUENA 0x0180
132#define OMAP4_GPIO_SETWKUENA 0x0184
78a1a6d3
SR		 133#define OMAP4_GPIO_CLEARDATAOUT 0x0190
134#define OMAP4_GPIO_SETDATAOUT 0x0194
5492fb1a 135
5e1c5ff4 136struct gpio_bank {
9f7065da 137 unsigned long pbase;
92105bb7 138 void __iomem *base;
5e1c5ff4
TL		 139 u16 irq;
140 u16 virtual_irq_start;
92105bb7 141 int method;
140455fa 142#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
92105bb7
TL		 143 u32 suspend_wakeup;
144 u32 saved_wakeup;
3ac4fa99 145#endif
3ac4fa99
JY		 146 u32 non_wakeup_gpios;
147 u32 enabled_non_wakeup_gpios;
148
149 u32 saved_datain;
150 u32 saved_fallingdetect;
151 u32 saved_risingdetect;
b144ff6f 152 u32 level_mask;
4318f36b 153 u32 toggle_mask;
5e1c5ff4 154 spinlock_t lock;
52e31344 155 struct gpio_chip chip;
89db9482 156 struct clk *dbck;
058af1ea 157 u32 mod_usage;
8865b9b6 158 u32 dbck_enable_mask;
77640aab
VC		 159 struct device *dev;
160 bool dbck_flag;
5de62b86 161 int stride;
5e1c5ff4
TL		 162};
163
a8eb7ca0 164#ifdef CONFIG_ARCH_OMAP3
40c670f0 165struct omap3_gpio_regs {
40c670f0
RN		 166 u32 irqenable1;
167 u32 irqenable2;
168 u32 wake_en;
169 u32 ctrl;
170 u32 oe;
171 u32 leveldetect0;
172 u32 leveldetect1;
173 u32 risingdetect;
174 u32 fallingdetect;
175 u32 dataout;
5492fb1a
SMK		 176};
177
40c670f0 178static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
5492fb1a
SMK		 179#endif
180
77640aab
VC		 181/*
182 * TODO: Cleanup gpio_bank usage as it is having information
183 * related to all instances of the device
184 */
185static struct gpio_bank *gpio_bank;
44169075 186
77640aab 187static int bank_width;
44169075 188
c95d10bc
VC		 189/* TODO: Analyze removing gpio_bank_count usage from driver code */
190int gpio_bank_count;
5e1c5ff4
TL		 191
192static inline struct gpio_bank *get_gpio_bank(int gpio)
193{
6e60e79a 194 if (cpu_is_omap15xx()) {
5e1c5ff4
TL		 195 if (OMAP_GPIO_IS_MPUIO(gpio))
196 return &gpio_bank[0];
197 return &gpio_bank[1];
198 }
5e1c5ff4
TL		 199 if (cpu_is_omap16xx()) {
200 if (OMAP_GPIO_IS_MPUIO(gpio))
201 return &gpio_bank[0];
202 return &gpio_bank[1 + (gpio >> 4)];
203 }
56739a69 204 if (cpu_is_omap7xx()) {
5e1c5ff4
TL		 205 if (OMAP_GPIO_IS_MPUIO(gpio))
206 return &gpio_bank[0];
207 return &gpio_bank[1 + (gpio >> 5)];
208 }
92105bb7
TL		 209 if (cpu_is_omap24xx())
210 return &gpio_bank[gpio >> 5];
44169075 211 if (cpu_is_omap34xx() || cpu_is_omap44xx())
5492fb1a 212 return &gpio_bank[gpio >> 5];
e031ab23
DB		 213 BUG();
214 return NULL;
5e1c5ff4
TL		 215}
216
217static inline int get_gpio_index(int gpio)
218{
56739a69 219 if (cpu_is_omap7xx())
5e1c5ff4 220 return gpio & 0x1f;
92105bb7
TL		 221 if (cpu_is_omap24xx())
222 return gpio & 0x1f;
44169075 223 if (cpu_is_omap34xx() || cpu_is_omap44xx())
5492fb1a 224 return gpio & 0x1f;
92105bb7 225 return gpio & 0x0f;
5e1c5ff4
TL		 226}
227
228static inline int gpio_valid(int gpio)
229{
230 if (gpio < 0)
231 return -1;
d11ac979 232 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
193e68be 233 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
5e1c5ff4
TL		 234 return -1;
235 return 0;
236 }
6e60e79a 237 if (cpu_is_omap15xx() && gpio < 16)
5e1c5ff4 238 return 0;
5e1c5ff4
TL		 239 if ((cpu_is_omap16xx()) && gpio < 64)
240 return 0;
56739a69 241 if (cpu_is_omap7xx() && gpio < 192)
5e1c5ff4 242 return 0;
25d6f630
TL		 243 if (cpu_is_omap2420() && gpio < 128)
244 return 0;
245 if (cpu_is_omap2430() && gpio < 160)
92105bb7 246 return 0;
44169075 247 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
5492fb1a 248 return 0;
5e1c5ff4
TL		 249 return -1;
250}
251
252static int check_gpio(int gpio)
253{
d32b20fc 254 if (unlikely(gpio_valid(gpio) < 0)) {
5e1c5ff4
TL		 255 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
256 dump_stack();
257 return -1;
258 }
259 return 0;
260}
261
262static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
263{
92105bb7 264 void __iomem *reg = bank->base;
5e1c5ff4
TL		 265 u32 l;
266
267 switch (bank->method) {
e5c56ed3 268#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 269 case METHOD_MPUIO:
5de62b86 270 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
5e1c5ff4 271 break;
e5c56ed3
DB		 272#endif
273#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 274 case METHOD_GPIO_1510:
275 reg += OMAP1510_GPIO_DIR_CONTROL;
276 break;
e5c56ed3
DB		 277#endif
278#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 279 case METHOD_GPIO_1610:
280 reg += OMAP1610_GPIO_DIRECTION;
281 break;
e5c56ed3 282#endif
b718aa81 283#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 284 case METHOD_GPIO_7XX:
285 reg += OMAP7XX_GPIO_DIR_CONTROL;
56739a69
ZM		 286 break;
287#endif
a8eb7ca0 288#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 289 case METHOD_GPIO_24XX:
290 reg += OMAP24XX_GPIO_OE;
291 break;
78a1a6d3
SR		 292#endif
293#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 294 case METHOD_GPIO_44XX:
78a1a6d3
SR		 295 reg += OMAP4_GPIO_OE;
296 break;
e5c56ed3
DB		 297#endif
298 default:
299 WARN_ON(1);
300 return;
5e1c5ff4
TL		 301 }
302 l = __raw_readl(reg);
303 if (is_input)
304 l |= 1 << gpio;
305 else
306 l &= ~(1 << gpio);
307 __raw_writel(l, reg);
308}
309
5e1c5ff4
TL		 310static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
311{
92105bb7 312 void __iomem *reg = bank->base;
5e1c5ff4
TL		 313 u32 l = 0;
314
315 switch (bank->method) {
e5c56ed3 316#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 317 case METHOD_MPUIO:
5de62b86 318 reg += OMAP_MPUIO_OUTPUT / bank->stride;
5e1c5ff4
TL		 319 l = __raw_readl(reg);
320 if (enable)
321 l |= 1 << gpio;
322 else
323 l &= ~(1 << gpio);
324 break;
e5c56ed3
DB		 325#endif
326#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 327 case METHOD_GPIO_1510:
328 reg += OMAP1510_GPIO_DATA_OUTPUT;
329 l = __raw_readl(reg);
330 if (enable)
331 l |= 1 << gpio;
332 else
333 l &= ~(1 << gpio);
334 break;
e5c56ed3
DB		 335#endif
336#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 337 case METHOD_GPIO_1610:
338 if (enable)
339 reg += OMAP1610_GPIO_SET_DATAOUT;
340 else
341 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
342 l = 1 << gpio;
343 break;
e5c56ed3 344#endif
b718aa81 345#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 346 case METHOD_GPIO_7XX:
347 reg += OMAP7XX_GPIO_DATA_OUTPUT;
56739a69
ZM		 348 l = __raw_readl(reg);
349 if (enable)
350 l |= 1 << gpio;
351 else
352 l &= ~(1 << gpio);
353 break;
354#endif
a8eb7ca0 355#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 356 case METHOD_GPIO_24XX:
357 if (enable)
358 reg += OMAP24XX_GPIO_SETDATAOUT;
359 else
360 reg += OMAP24XX_GPIO_CLEARDATAOUT;
361 l = 1 << gpio;
362 break;
78a1a6d3
SR		 363#endif
364#ifdef CONFIG_ARCH_OMAP4
3f1686a9 365 case METHOD_GPIO_44XX:
78a1a6d3
SR		 366 if (enable)
367 reg += OMAP4_GPIO_SETDATAOUT;
368 else
369 reg += OMAP4_GPIO_CLEARDATAOUT;
370 l = 1 << gpio;
371 break;
e5c56ed3 372#endif
5e1c5ff4 373 default:
e5c56ed3 374 WARN_ON(1);
5e1c5ff4
TL		 375 return;
376 }
377 __raw_writel(l, reg);
378}
379
b37c45b8 380static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
5e1c5ff4 381{
92105bb7 382 void __iomem *reg;
5e1c5ff4
TL		 383
384 if (check_gpio(gpio) < 0)
e5c56ed3 385 return -EINVAL;
5e1c5ff4
TL		 386 reg = bank->base;
387 switch (bank->method) {
e5c56ed3 388#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 389 case METHOD_MPUIO:
5de62b86 390 reg += OMAP_MPUIO_INPUT_LATCH / bank->stride;
5e1c5ff4 391 break;
e5c56ed3
DB		 392#endif
393#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 394 case METHOD_GPIO_1510:
395 reg += OMAP1510_GPIO_DATA_INPUT;
396 break;
e5c56ed3
DB		 397#endif
398#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 399 case METHOD_GPIO_1610:
400 reg += OMAP1610_GPIO_DATAIN;
401 break;
e5c56ed3 402#endif
b718aa81 403#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 404 case METHOD_GPIO_7XX:
405 reg += OMAP7XX_GPIO_DATA_INPUT;
56739a69
ZM		 406 break;
407#endif
a8eb7ca0 408#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 409 case METHOD_GPIO_24XX:
410 reg += OMAP24XX_GPIO_DATAIN;
411 break;
78a1a6d3
SR		 412#endif
413#ifdef CONFIG_ARCH_OMAP4
3f1686a9 414 case METHOD_GPIO_44XX:
78a1a6d3
SR		 415 reg += OMAP4_GPIO_DATAIN;
416 break;
e5c56ed3 417#endif
5e1c5ff4 418 default:
e5c56ed3 419 return -EINVAL;
5e1c5ff4 420 }
92105bb7
TL		 421 return (__raw_readl(reg)
422 & (1 << get_gpio_index(gpio))) != 0;
5e1c5ff4
TL		 423}
424
b37c45b8
RQ		 425static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
426{
427 void __iomem *reg;
428
429 if (check_gpio(gpio) < 0)
430 return -EINVAL;
431 reg = bank->base;
432
433 switch (bank->method) {
434#ifdef CONFIG_ARCH_OMAP1
435 case METHOD_MPUIO:
5de62b86 436 reg += OMAP_MPUIO_OUTPUT / bank->stride;
b37c45b8
RQ		 437 break;
438#endif
439#ifdef CONFIG_ARCH_OMAP15XX
440 case METHOD_GPIO_1510:
441 reg += OMAP1510_GPIO_DATA_OUTPUT;
442 break;
443#endif
444#ifdef CONFIG_ARCH_OMAP16XX
445 case METHOD_GPIO_1610:
446 reg += OMAP1610_GPIO_DATAOUT;
447 break;
448#endif
b718aa81 449#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 450 case METHOD_GPIO_7XX:
451 reg += OMAP7XX_GPIO_DATA_OUTPUT;
b37c45b8
RQ		 452 break;
453#endif
9f096868 454#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
b37c45b8
RQ		 455 case METHOD_GPIO_24XX:
456 reg += OMAP24XX_GPIO_DATAOUT;
457 break;
9f096868
C		 458#endif
459#ifdef CONFIG_ARCH_OMAP4
460 case METHOD_GPIO_44XX:
461 reg += OMAP4_GPIO_DATAOUT;
462 break;
b37c45b8
RQ		 463#endif
464 default:
465 return -EINVAL;
466 }
467
468 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
469}
470
92105bb7
TL		 471#define MOD_REG_BIT(reg, bit_mask, set) \
472do { \
473 int l = __raw_readl(base + reg); \
474 if (set) l |= bit_mask; \
475 else l &= ~bit_mask; \
476 __raw_writel(l, base + reg); \
477} while(0)
478
168ef3d9
FB		 479/**
480 * _set_gpio_debounce - low level gpio debounce time
481 * @bank: the gpio bank we're acting upon
482 * @gpio: the gpio number on this @gpio
483 * @debounce: debounce time to use
484 *
485 * OMAP's debounce time is in 31us steps so we need
486 * to convert and round up to the closest unit.
487 */
488static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
489 unsigned debounce)
490{
491 void __iomem *reg = bank->base;
492 u32 val;
493 u32 l;
494
77640aab
VC		 495 if (!bank->dbck_flag)
496 return;
497
168ef3d9
FB		 498 if (debounce < 32)
499 debounce = 0x01;
500 else if (debounce > 7936)
501 debounce = 0xff;
502 else
503 debounce = (debounce / 0x1f) - 1;
504
505 l = 1 << get_gpio_index(gpio);
506
77640aab 507 if (bank->method == METHOD_GPIO_44XX)
168ef3d9
FB		 508 reg += OMAP4_GPIO_DEBOUNCINGTIME;
509 else
510 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
511
512 __raw_writel(debounce, reg);
513
514 reg = bank->base;
77640aab 515 if (bank->method == METHOD_GPIO_44XX)
168ef3d9
FB		 516 reg += OMAP4_GPIO_DEBOUNCENABLE;
517 else
518 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
519
520 val = __raw_readl(reg);
521
522 if (debounce) {
523 val |= l;
77640aab 524 clk_enable(bank->dbck);
168ef3d9
FB		 525 } else {
526 val &= ~l;
77640aab 527 clk_disable(bank->dbck);
168ef3d9 528 }
f7ec0b0b 529 bank->dbck_enable_mask = val;
168ef3d9
FB		 530
531 __raw_writel(val, reg);
532}
533
140455fa 534#ifdef CONFIG_ARCH_OMAP2PLUS
5eb3bb9c
KH		 535static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
536 int trigger)
5e1c5ff4 537{
3ac4fa99 538 void __iomem *base = bank->base;
92105bb7 539 u32 gpio_bit = 1 << gpio;
78a1a6d3 540 u32 val;
92105bb7 541
78a1a6d3
SR		 542 if (cpu_is_omap44xx()) {
543 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
544 trigger & IRQ_TYPE_LEVEL_LOW);
545 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
546 trigger & IRQ_TYPE_LEVEL_HIGH);
547 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
548 trigger & IRQ_TYPE_EDGE_RISING);
549 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
550 trigger & IRQ_TYPE_EDGE_FALLING);
551 } else {
552 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
553 trigger & IRQ_TYPE_LEVEL_LOW);
554 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
555 trigger & IRQ_TYPE_LEVEL_HIGH);
556 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
557 trigger & IRQ_TYPE_EDGE_RISING);
558 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
559 trigger & IRQ_TYPE_EDGE_FALLING);
560 }
3ac4fa99 561 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
78a1a6d3
SR		 562 if (cpu_is_omap44xx()) {
563 if (trigger != 0)
564 __raw_writel(1 << gpio, bank->base+
565 OMAP4_GPIO_IRQWAKEN0);
566 else {
567 val = __raw_readl(bank->base +
568 OMAP4_GPIO_IRQWAKEN0);
569 __raw_writel(val & (~(1 << gpio)), bank->base +
570 OMAP4_GPIO_IRQWAKEN0);
571 }
572 } else {
699117a6
CW		 573 /*
574 * GPIO wakeup request can only be generated on edge
575 * transitions
576 */
577 if (trigger & IRQ_TYPE_EDGE_BOTH)
78a1a6d3 578 __raw_writel(1 << gpio, bank->base
5eb3bb9c 579 + OMAP24XX_GPIO_SETWKUENA);
78a1a6d3
SR		 580 else
581 __raw_writel(1 << gpio, bank->base
5eb3bb9c 582 + OMAP24XX_GPIO_CLEARWKUENA);
78a1a6d3 583 }
a118b5f3
TK		 584 }
585 /* This part needs to be executed always for OMAP34xx */
586 if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
699117a6
CW		 587 /*
588 * Log the edge gpio and manually trigger the IRQ
589 * after resume if the input level changes
590 * to avoid irq lost during PER RET/OFF mode
591 * Applies for omap2 non-wakeup gpio and all omap3 gpios
592 */
593 if (trigger & IRQ_TYPE_EDGE_BOTH)
3ac4fa99
JY		 594 bank->enabled_non_wakeup_gpios |= gpio_bit;
595 else
596 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
597 }
5eb3bb9c 598
78a1a6d3
SR		 599 if (cpu_is_omap44xx()) {
600 bank->level_mask =
601 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
602 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
603 } else {
604 bank->level_mask =
605 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
606 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
607 }
92105bb7 608}
3ac4fa99 609#endif
92105bb7 610
9198bcd3 611#ifdef CONFIG_ARCH_OMAP1
4318f36b
CM		 612/*
613 * This only applies to chips that can't do both rising and falling edge
614 * detection at once. For all other chips, this function is a noop.
615 */
616static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
617{
618 void __iomem *reg = bank->base;
619 u32 l = 0;
620
621 switch (bank->method) {
4318f36b 622 case METHOD_MPUIO:
5de62b86 623 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
4318f36b 624 break;
4318f36b
CM		 625#ifdef CONFIG_ARCH_OMAP15XX
626 case METHOD_GPIO_1510:
627 reg += OMAP1510_GPIO_INT_CONTROL;
628 break;
629#endif
630#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
631 case METHOD_GPIO_7XX:
632 reg += OMAP7XX_GPIO_INT_CONTROL;
633 break;
634#endif
635 default:
636 return;
637 }
638
639 l = __raw_readl(reg);
640 if ((l >> gpio) & 1)
641 l &= ~(1 << gpio);
642 else
643 l |= 1 << gpio;
644
645 __raw_writel(l, reg);
646}
9198bcd3 647#endif
4318f36b 648
92105bb7
TL		 649static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
650{
651 void __iomem *reg = bank->base;
652 u32 l = 0;
5e1c5ff4
TL		 653
654 switch (bank->method) {
e5c56ed3 655#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 656 case METHOD_MPUIO:
5de62b86 657 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
5e1c5ff4 658 l = __raw_readl(reg);
29501577 659 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 660 bank->toggle_mask |= 1 << gpio;
6cab4860 661 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 662 l |= 1 << gpio;
6cab4860 663 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 664 l &= ~(1 << gpio);
92105bb7
TL		 665 else
666 goto bad;
5e1c5ff4 667 break;
e5c56ed3
DB		 668#endif
669#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 670 case METHOD_GPIO_1510:
671 reg += OMAP1510_GPIO_INT_CONTROL;
672 l = __raw_readl(reg);
29501577 673 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 674 bank->toggle_mask |= 1 << gpio;
6cab4860 675 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 676 l |= 1 << gpio;
6cab4860 677 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 678 l &= ~(1 << gpio);
92105bb7
TL		 679 else
680 goto bad;
5e1c5ff4 681 break;
e5c56ed3 682#endif
3ac4fa99 683#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4 684 case METHOD_GPIO_1610:
5e1c5ff4
TL		 685 if (gpio & 0x08)
686 reg += OMAP1610_GPIO_EDGE_CTRL2;
687 else
688 reg += OMAP1610_GPIO_EDGE_CTRL1;
689 gpio &= 0x07;
690 l = __raw_readl(reg);
691 l &= ~(3 << (gpio << 1));
6cab4860 692 if (trigger & IRQ_TYPE_EDGE_RISING)
6e60e79a 693 l |= 2 << (gpio << 1);
6cab4860 694 if (trigger & IRQ_TYPE_EDGE_FALLING)
6e60e79a 695 l |= 1 << (gpio << 1);
3ac4fa99
JY		 696 if (trigger)
697 /* Enable wake-up during idle for dynamic tick */
698 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
699 else
700 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
5e1c5ff4 701 break;
3ac4fa99 702#endif
b718aa81 703#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 704 case METHOD_GPIO_7XX:
705 reg += OMAP7XX_GPIO_INT_CONTROL;
56739a69 706 l = __raw_readl(reg);
29501577 707 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 708 bank->toggle_mask |= 1 << gpio;
56739a69
ZM		 709 if (trigger & IRQ_TYPE_EDGE_RISING)
710 l |= 1 << gpio;
711 else if (trigger & IRQ_TYPE_EDGE_FALLING)
712 l &= ~(1 << gpio);
713 else
714 goto bad;
715 break;
716#endif
140455fa 717#ifdef CONFIG_ARCH_OMAP2PLUS
92105bb7 718 case METHOD_GPIO_24XX:
3f1686a9 719 case METHOD_GPIO_44XX:
3ac4fa99 720 set_24xx_gpio_triggering(bank, gpio, trigger);
f7c5cc45 721 return 0;
3ac4fa99 722#endif
5e1c5ff4 723 default:
92105bb7 724 goto bad;
5e1c5ff4 725 }
92105bb7
TL		 726 __raw_writel(l, reg);
727 return 0;
728bad:
729 return -EINVAL;
5e1c5ff4
TL		 730}
731
92105bb7 732static int gpio_irq_type(unsigned irq, unsigned type)
5e1c5ff4
TL		 733{
734 struct gpio_bank *bank;
92105bb7
TL		 735 unsigned gpio;
736 int retval;
a6472533 737 unsigned long flags;
92105bb7 738
5492fb1a 739 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
92105bb7
TL		 740 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
741 else
742 gpio = irq - IH_GPIO_BASE;
5e1c5ff4
TL		 743
744 if (check_gpio(gpio) < 0)
92105bb7
TL		 745 return -EINVAL;
746
e5c56ed3 747 if (type & ~IRQ_TYPE_SENSE_MASK)
6e60e79a 748 return -EINVAL;
e5c56ed3
DB		 749
750 /* OMAP1 allows only only edge triggering */
5492fb1a 751 if (!cpu_class_is_omap2()
e5c56ed3 752 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
92105bb7
TL		 753 return -EINVAL;
754
58781016 755 bank = get_irq_chip_data(irq);
a6472533 756 spin_lock_irqsave(&bank->lock, flags);
92105bb7 757 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
b9772a22 758 if (retval == 0) {
1a9b5878
FB		 759 struct irq_desc *d = irq_to_desc(irq);
760
761 d->status &= ~IRQ_TYPE_SENSE_MASK;
762 d->status |= type;
b9772a22 763 }
a6472533 764 spin_unlock_irqrestore(&bank->lock, flags);
672e302e
KH		 765
766 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
767 __set_irq_handler_unlocked(irq, handle_level_irq);
768 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
769 __set_irq_handler_unlocked(irq, handle_edge_irq);
770
92105bb7 771 return retval;
5e1c5ff4
TL		 772}
773
774static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
775{
92105bb7 776 void __iomem *reg = bank->base;
5e1c5ff4
TL		 777
778 switch (bank->method) {
e5c56ed3 779#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 780 case METHOD_MPUIO:
781 /* MPUIO irqstatus is reset by reading the status register,
782 * so do nothing here */
783 return;
e5c56ed3
DB		 784#endif
785#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 786 case METHOD_GPIO_1510:
787 reg += OMAP1510_GPIO_INT_STATUS;
788 break;
e5c56ed3
DB		 789#endif
790#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 791 case METHOD_GPIO_1610:
792 reg += OMAP1610_GPIO_IRQSTATUS1;
793 break;
e5c56ed3 794#endif
b718aa81 795#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 796 case METHOD_GPIO_7XX:
797 reg += OMAP7XX_GPIO_INT_STATUS;
56739a69
ZM		 798 break;
799#endif
a8eb7ca0 800#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 801 case METHOD_GPIO_24XX:
802 reg += OMAP24XX_GPIO_IRQSTATUS1;
803 break;
78a1a6d3
SR		 804#endif
805#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 806 case METHOD_GPIO_44XX:
78a1a6d3
SR		 807 reg += OMAP4_GPIO_IRQSTATUS0;
808 break;
e5c56ed3 809#endif
5e1c5ff4 810 default:
e5c56ed3 811 WARN_ON(1);
5e1c5ff4
TL		 812 return;
813 }
814 __raw_writel(gpio_mask, reg);
bee7930f
HD		 815
816 /* Workaround for clearing DSP GPIO interrupts to allow retention */
3f1686a9
TL		 817 if (cpu_is_omap24xx() || cpu_is_omap34xx())
818 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
819 else if (cpu_is_omap44xx())
820 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
821
78a1a6d3 822 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
bedfd154
RQ		 823 __raw_writel(gpio_mask, reg);
824
825 /* Flush posted write for the irq status to avoid spurious interrupts */
826 __raw_readl(reg);
78a1a6d3 827 }
5e1c5ff4
TL		 828}
829
830static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
831{
832 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
833}
834
ea6dedd7
ID		 835static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
836{
837 void __iomem *reg = bank->base;
99c47707
ID		 838 int inv = 0;
839 u32 l;
840 u32 mask;
ea6dedd7
ID		 841
842 switch (bank->method) {
e5c56ed3 843#ifdef CONFIG_ARCH_OMAP1
ea6dedd7 844 case METHOD_MPUIO:
5de62b86 845 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
99c47707
ID		 846 mask = 0xffff;
847 inv = 1;
ea6dedd7 848 break;
e5c56ed3
DB		 849#endif
850#ifdef CONFIG_ARCH_OMAP15XX
ea6dedd7
ID		 851 case METHOD_GPIO_1510:
852 reg += OMAP1510_GPIO_INT_MASK;
99c47707
ID		 853 mask = 0xffff;
854 inv = 1;
ea6dedd7 855 break;
e5c56ed3
DB		 856#endif
857#ifdef CONFIG_ARCH_OMAP16XX
ea6dedd7
ID		 858 case METHOD_GPIO_1610:
859 reg += OMAP1610_GPIO_IRQENABLE1;
99c47707 860 mask = 0xffff;
ea6dedd7 861 break;
e5c56ed3 862#endif
b718aa81 863#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 864 case METHOD_GPIO_7XX:
865 reg += OMAP7XX_GPIO_INT_MASK;
56739a69
ZM		 866 mask = 0xffffffff;
867 inv = 1;
868 break;
869#endif
a8eb7ca0 870#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
ea6dedd7
ID		 871 case METHOD_GPIO_24XX:
872 reg += OMAP24XX_GPIO_IRQENABLE1;
99c47707 873 mask = 0xffffffff;
ea6dedd7 874 break;
78a1a6d3
SR		 875#endif
876#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 877 case METHOD_GPIO_44XX:
78a1a6d3
SR		 878 reg += OMAP4_GPIO_IRQSTATUSSET0;
879 mask = 0xffffffff;
880 break;
e5c56ed3 881#endif
ea6dedd7 882 default:
e5c56ed3 883 WARN_ON(1);
ea6dedd7
ID		 884 return 0;
885 }
886
99c47707
ID		 887 l = __raw_readl(reg);
888 if (inv)
889 l = ~l;
890 l &= mask;
891 return l;
ea6dedd7
ID		 892}
893
5e1c5ff4
TL		 894static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
895{
92105bb7 896 void __iomem *reg = bank->base;
5e1c5ff4
TL		 897 u32 l;
898
899 switch (bank->method) {
e5c56ed3 900#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 901 case METHOD_MPUIO:
5de62b86 902 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
5e1c5ff4
TL		 903 l = __raw_readl(reg);
904 if (enable)
905 l &= ~(gpio_mask);
906 else
907 l |= gpio_mask;
908 break;
e5c56ed3
DB		 909#endif
910#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 911 case METHOD_GPIO_1510:
912 reg += OMAP1510_GPIO_INT_MASK;
913 l = __raw_readl(reg);
914 if (enable)
915 l &= ~(gpio_mask);
916 else
917 l |= gpio_mask;
918 break;
e5c56ed3
DB		 919#endif
920#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 921 case METHOD_GPIO_1610:
922 if (enable)
923 reg += OMAP1610_GPIO_SET_IRQENABLE1;
924 else
925 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
926 l = gpio_mask;
927 break;
e5c56ed3 928#endif
b718aa81 929#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 930 case METHOD_GPIO_7XX:
931 reg += OMAP7XX_GPIO_INT_MASK;
56739a69
ZM		 932 l = __raw_readl(reg);
933 if (enable)
934 l &= ~(gpio_mask);
935 else
936 l |= gpio_mask;
937 break;
938#endif
a8eb7ca0 939#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 940 case METHOD_GPIO_24XX:
941 if (enable)
942 reg += OMAP24XX_GPIO_SETIRQENABLE1;
943 else
944 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
945 l = gpio_mask;
946 break;
78a1a6d3
SR		 947#endif
948#ifdef CONFIG_ARCH_OMAP4
3f1686a9 949 case METHOD_GPIO_44XX:
78a1a6d3
SR		 950 if (enable)
951 reg += OMAP4_GPIO_IRQSTATUSSET0;
952 else
953 reg += OMAP4_GPIO_IRQSTATUSCLR0;
954 l = gpio_mask;
955 break;
e5c56ed3 956#endif
5e1c5ff4 957 default:
e5c56ed3 958 WARN_ON(1);
5e1c5ff4
TL		 959 return;
960 }
961 __raw_writel(l, reg);
962}
963
964static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
965{
966 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
967}
968
92105bb7
TL		 969/*
970 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
971 * 1510 does not seem to have a wake-up register. If JTAG is connected
972 * to the target, system will wake up always on GPIO events. While
973 * system is running all registered GPIO interrupts need to have wake-up
974 * enabled. When system is suspended, only selected GPIO interrupts need
975 * to have wake-up enabled.
976 */
977static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
978{
4cc6420c 979 unsigned long uninitialized_var(flags);
a6472533 980
92105bb7 981 switch (bank->method) {
3ac4fa99 982#ifdef CONFIG_ARCH_OMAP16XX
11a78b79 983 case METHOD_MPUIO:
92105bb7 984 case METHOD_GPIO_1610:
a6472533 985 spin_lock_irqsave(&bank->lock, flags);
b3bb4f68 986 if (enable)
92105bb7 987 bank->suspend_wakeup |= (1 << gpio);
b3bb4f68 988 else
92105bb7 989 bank->suspend_wakeup &= ~(1 << gpio);
a6472533 990 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7 991 return 0;
3ac4fa99 992#endif
140455fa 993#ifdef CONFIG_ARCH_OMAP2PLUS
3ac4fa99 994 case METHOD_GPIO_24XX:
3f1686a9 995 case METHOD_GPIO_44XX:
11a78b79
DB		 996 if (bank->non_wakeup_gpios & (1 << gpio)) {
997 printk(KERN_ERR "Unable to modify wakeup on "
998 "non-wakeup GPIO%d\n",
999 (bank - gpio_bank) * 32 + gpio);
1000 return -EINVAL;
1001 }
a6472533 1002 spin_lock_irqsave(&bank->lock, flags);
b3bb4f68 1003 if (enable)
3ac4fa99 1004 bank->suspend_wakeup |= (1 << gpio);
b3bb4f68 1005 else
3ac4fa99 1006 bank->suspend_wakeup &= ~(1 << gpio);
a6472533 1007 spin_unlock_irqrestore(&bank->lock, flags);
3ac4fa99
JY		 1008 return 0;
1009#endif
92105bb7
TL		 1010 default:
1011 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
1012 bank->method);
1013 return -EINVAL;
1014 }
1015}
1016
4196dd6b
TL		 1017static void _reset_gpio(struct gpio_bank *bank, int gpio)
1018{
1019 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
1020 _set_gpio_irqenable(bank, gpio, 0);
1021 _clear_gpio_irqstatus(bank, gpio);
6cab4860 1022 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
4196dd6b
TL		 1023}
1024
92105bb7
TL		 1025/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
1026static int gpio_wake_enable(unsigned int irq, unsigned int enable)
1027{
1028 unsigned int gpio = irq - IH_GPIO_BASE;
1029 struct gpio_bank *bank;
1030 int retval;
1031
1032 if (check_gpio(gpio) < 0)
1033 return -ENODEV;
58781016 1034 bank = get_irq_chip_data(irq);
92105bb7 1035 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
92105bb7
TL		 1036
1037 return retval;
1038}
1039
3ff164e1 1040static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 1041{
3ff164e1 1042 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 1043 unsigned long flags;
52e31344 1044
a6472533 1045 spin_lock_irqsave(&bank->lock, flags);
92105bb7 1046
4196dd6b
TL		 1047 /* Set trigger to none. You need to enable the desired trigger with
1048 * request_irq() or set_irq_type().
1049 */
3ff164e1 1050 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
92105bb7 1051
1a8bfa1e 1052#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4 1053 if (bank->method == METHOD_GPIO_1510) {
92105bb7 1054 void __iomem *reg;
5e1c5ff4 1055
92105bb7 1056 /* Claim the pin for MPU */
5e1c5ff4 1057 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
3ff164e1 1058 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
5e1c5ff4
TL		 1059 }
1060#endif
058af1ea
C		 1061 if (!cpu_class_is_omap1()) {
1062 if (!bank->mod_usage) {
9f096868 1063 void __iomem *reg = bank->base;
058af1ea 1064 u32 ctrl;
9f096868
C		 1065
1066 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1067 reg += OMAP24XX_GPIO_CTRL;
1068 else if (cpu_is_omap44xx())
1069 reg += OMAP4_GPIO_CTRL;
1070 ctrl = __raw_readl(reg);
058af1ea 1071 /* Module is enabled, clocks are not gated */
9f096868
C		 1072 ctrl &= 0xFFFFFFFE;
1073 __raw_writel(ctrl, reg);
058af1ea
C		 1074 }
1075 bank->mod_usage |= 1 << offset;
1076 }
a6472533 1077 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 1078
1079 return 0;
1080}
1081
3ff164e1 1082static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 1083{
3ff164e1 1084 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 1085 unsigned long flags;
5e1c5ff4 1086
a6472533 1087 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1088#ifdef CONFIG_ARCH_OMAP16XX
1089 if (bank->method == METHOD_GPIO_1610) {
1090 /* Disable wake-up during idle for dynamic tick */
1091 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
3ff164e1 1092 __raw_writel(1 << offset, reg);
92105bb7
TL		 1093 }
1094#endif
9f096868
C		 1095#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1096 if (bank->method == METHOD_GPIO_24XX) {
92105bb7
TL		 1097 /* Disable wake-up during idle for dynamic tick */
1098 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
3ff164e1 1099 __raw_writel(1 << offset, reg);
92105bb7 1100 }
9f096868
C		 1101#endif
1102#ifdef CONFIG_ARCH_OMAP4
1103 if (bank->method == METHOD_GPIO_44XX) {
1104 /* Disable wake-up during idle for dynamic tick */
1105 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
1106 __raw_writel(1 << offset, reg);
1107 }
92105bb7 1108#endif
058af1ea
C		 1109 if (!cpu_class_is_omap1()) {
1110 bank->mod_usage &= ~(1 << offset);
1111 if (!bank->mod_usage) {
9f096868 1112 void __iomem *reg = bank->base;
058af1ea 1113 u32 ctrl;
9f096868
C		 1114
1115 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1116 reg += OMAP24XX_GPIO_CTRL;
1117 else if (cpu_is_omap44xx())
1118 reg += OMAP4_GPIO_CTRL;
1119 ctrl = __raw_readl(reg);
058af1ea
C		 1120 /* Module is disabled, clocks are gated */
1121 ctrl |= 1;
9f096868 1122 __raw_writel(ctrl, reg);
058af1ea
C		 1123 }
1124 }
3ff164e1 1125 _reset_gpio(bank, bank->chip.base + offset);
a6472533 1126 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 1127}
1128
1129/*
1130 * We need to unmask the GPIO bank interrupt as soon as possible to
1131 * avoid missing GPIO interrupts for other lines in the bank.
1132 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1133 * in the bank to avoid missing nested interrupts for a GPIO line.
1134 * If we wait to unmask individual GPIO lines in the bank after the
1135 * line's interrupt handler has been run, we may miss some nested
1136 * interrupts.
1137 */
10dd5ce2 1138static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
5e1c5ff4 1139{
92105bb7 1140 void __iomem *isr_reg = NULL;
5e1c5ff4 1141 u32 isr;
4318f36b 1142 unsigned int gpio_irq, gpio_index;
5e1c5ff4 1143 struct gpio_bank *bank;
ea6dedd7
ID		 1144 u32 retrigger = 0;
1145 int unmasked = 0;
5e1c5ff4
TL		 1146
1147 desc->chip->ack(irq);
1148
418ca1f0 1149 bank = get_irq_data(irq);
e5c56ed3 1150#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 1151 if (bank->method == METHOD_MPUIO)
5de62b86
TL		 1152 isr_reg = bank->base +
1153 OMAP_MPUIO_GPIO_INT / bank->stride;
e5c56ed3 1154#endif
1a8bfa1e 1155#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 1156 if (bank->method == METHOD_GPIO_1510)
1157 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1158#endif
1159#if defined(CONFIG_ARCH_OMAP16XX)
1160 if (bank->method == METHOD_GPIO_1610)
1161 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1162#endif
b718aa81 1163#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 1164 if (bank->method == METHOD_GPIO_7XX)
1165 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
56739a69 1166#endif
a8eb7ca0 1167#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 1168 if (bank->method == METHOD_GPIO_24XX)
1169 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
78a1a6d3
SR		 1170#endif
1171#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 1172 if (bank->method == METHOD_GPIO_44XX)
78a1a6d3 1173 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
92105bb7 1174#endif
b1cc4c55
EK		 1175
1176 if (WARN_ON(!isr_reg))
1177 goto exit;
1178
92105bb7 1179 while(1) {
6e60e79a 1180 u32 isr_saved, level_mask = 0;
ea6dedd7 1181 u32 enabled;
6e60e79a 1182
ea6dedd7
ID		 1183 enabled = _get_gpio_irqbank_mask(bank);
1184 isr_saved = isr = __raw_readl(isr_reg) & enabled;
6e60e79a
TL		 1185
1186 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1187 isr &= 0x0000ffff;
1188
5492fb1a 1189 if (cpu_class_is_omap2()) {
b144ff6f 1190 level_mask = bank->level_mask & enabled;
ea6dedd7 1191 }
6e60e79a
TL		 1192
1193 /* clear edge sensitive interrupts before handler(s) are
1194 called so that we don't miss any interrupt occurred while
1195 executing them */
1196 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1197 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1198 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1199
1200 /* if there is only edge sensitive GPIO pin interrupts
1201 configured, we could unmask GPIO bank interrupt immediately */
ea6dedd7
ID		 1202 if (!level_mask && !unmasked) {
1203 unmasked = 1;
6e60e79a 1204 desc->chip->unmask(irq);
ea6dedd7 1205 }
92105bb7 1206
ea6dedd7
ID		 1207 isr |= retrigger;
1208 retrigger = 0;
92105bb7
TL		 1209 if (!isr)
1210 break;
1211
1212 gpio_irq = bank->virtual_irq_start;
1213 for (; isr != 0; isr >>= 1, gpio_irq++) {
4318f36b
CM		 1214 gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
1215
92105bb7
TL		 1216 if (!(isr & 1))
1217 continue;
29454dde 1218
4318f36b
CM		 1219#ifdef CONFIG_ARCH_OMAP1
1220 /*
1221 * Some chips can't respond to both rising and falling
1222 * at the same time. If this irq was requested with
1223 * both flags, we need to flip the ICR data for the IRQ
1224 * to respond to the IRQ for the opposite direction.
1225 * This will be indicated in the bank toggle_mask.
1226 */
1227 if (bank->toggle_mask & (1 << gpio_index))
1228 _toggle_gpio_edge_triggering(bank, gpio_index);
1229#endif
1230
d8aa0251 1231 generic_handle_irq(gpio_irq);
92105bb7 1232 }
1a8bfa1e 1233 }
ea6dedd7
ID		 1234 /* if bank has any level sensitive GPIO pin interrupt
1235 configured, we must unmask the bank interrupt only after
1236 handler(s) are executed in order to avoid spurious bank
1237 interrupt */
b1cc4c55 1238exit:
ea6dedd7
ID		 1239 if (!unmasked)
1240 desc->chip->unmask(irq);
1241
5e1c5ff4
TL		 1242}
1243
4196dd6b
TL		 1244static void gpio_irq_shutdown(unsigned int irq)
1245{
1246 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1247 struct gpio_bank *bank = get_irq_chip_data(irq);
4196dd6b
TL		 1248
1249 _reset_gpio(bank, gpio);
1250}
1251
5e1c5ff4
TL		 1252static void gpio_ack_irq(unsigned int irq)
1253{
1254 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1255 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1256
1257 _clear_gpio_irqstatus(bank, gpio);
1258}
1259
1260static void gpio_mask_irq(unsigned int irq)
1261{
1262 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1263 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1264
1265 _set_gpio_irqenable(bank, gpio, 0);
55b6019a 1266 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
5e1c5ff4
TL		 1267}
1268
1269static void gpio_unmask_irq(unsigned int irq)
1270{
1271 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1272 struct gpio_bank *bank = get_irq_chip_data(irq);
b144ff6f 1273 unsigned int irq_mask = 1 << get_gpio_index(gpio);
55b6019a
KH		 1274 struct irq_desc *desc = irq_to_desc(irq);
1275 u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
1276
1277 if (trigger)
1278 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
b144ff6f
KH		 1279
1280 /* For level-triggered GPIOs, the clearing must be done after
1281 * the HW source is cleared, thus after the handler has run */
1282 if (bank->level_mask & irq_mask) {
1283 _set_gpio_irqenable(bank, gpio, 0);
1284 _clear_gpio_irqstatus(bank, gpio);
1285 }
5e1c5ff4 1286
4de8c75b 1287 _set_gpio_irqenable(bank, gpio, 1);
5e1c5ff4
TL		 1288}
1289
e5c56ed3
DB		 1290static struct irq_chip gpio_irq_chip = {
1291 .name = "GPIO",
1292 .shutdown = gpio_irq_shutdown,
1293 .ack = gpio_ack_irq,
1294 .mask = gpio_mask_irq,
1295 .unmask = gpio_unmask_irq,
1296 .set_type = gpio_irq_type,
1297 .set_wake = gpio_wake_enable,
1298};
1299
1300/*---------------------------------------------------------------------*/
1301
1302#ifdef CONFIG_ARCH_OMAP1
1303
1304/* MPUIO uses the always-on 32k clock */
1305
5e1c5ff4
TL		 1306static void mpuio_ack_irq(unsigned int irq)
1307{
1308 /* The ISR is reset automatically, so do nothing here. */
1309}
1310
1311static void mpuio_mask_irq(unsigned int irq)
1312{
1313 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
58781016 1314 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1315
1316 _set_gpio_irqenable(bank, gpio, 0);
1317}
1318
1319static void mpuio_unmask_irq(unsigned int irq)
1320{
1321 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
58781016 1322 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1323
1324 _set_gpio_irqenable(bank, gpio, 1);
1325}
1326
e5c56ed3
DB		 1327static struct irq_chip mpuio_irq_chip = {
1328 .name = "MPUIO",
1329 .ack = mpuio_ack_irq,
1330 .mask = mpuio_mask_irq,
1331 .unmask = mpuio_unmask_irq,
92105bb7 1332 .set_type = gpio_irq_type,
11a78b79
DB		 1333#ifdef CONFIG_ARCH_OMAP16XX
1334 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1335 .set_wake = gpio_wake_enable,
1336#endif
5e1c5ff4
TL		 1337};
1338
e5c56ed3
DB		 1339
1340#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1341
11a78b79
DB		 1342
1343#ifdef CONFIG_ARCH_OMAP16XX
1344
1345#include <linux/platform_device.h>
1346
79ee031f 1347static int omap_mpuio_suspend_noirq(struct device *dev)
11a78b79 1348{
79ee031f 1349 struct platform_device *pdev = to_platform_device(dev);
11a78b79 1350 struct gpio_bank *bank = platform_get_drvdata(pdev);
5de62b86
TL		 1351 void __iomem *mask_reg = bank->base +
1352 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
a6472533 1353 unsigned long flags;
11a78b79 1354
a6472533 1355 spin_lock_irqsave(&bank->lock, flags);
11a78b79
DB		 1356 bank->saved_wakeup = __raw_readl(mask_reg);
1357 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
a6472533 1358 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1359
1360 return 0;
1361}
1362
79ee031f 1363static int omap_mpuio_resume_noirq(struct device *dev)
11a78b79 1364{
79ee031f 1365 struct platform_device *pdev = to_platform_device(dev);
11a78b79 1366 struct gpio_bank *bank = platform_get_drvdata(pdev);
5de62b86
TL		 1367 void __iomem *mask_reg = bank->base +
1368 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
a6472533 1369 unsigned long flags;
11a78b79 1370
a6472533 1371 spin_lock_irqsave(&bank->lock, flags);
11a78b79 1372 __raw_writel(bank->saved_wakeup, mask_reg);
a6472533 1373 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1374
1375 return 0;
1376}
1377
47145210 1378static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
79ee031f
MD		 1379 .suspend_noirq = omap_mpuio_suspend_noirq,
1380 .resume_noirq = omap_mpuio_resume_noirq,
1381};
1382
11a78b79
DB		 1383/* use platform_driver for this, now that there's no longer any
1384 * point to sys_device (other than not disturbing old code).
1385 */
1386static struct platform_driver omap_mpuio_driver = {
11a78b79
DB		 1387 .driver = {
1388 .name = "mpuio",
79ee031f 1389 .pm = &omap_mpuio_dev_pm_ops,
11a78b79
DB		 1390 },
1391};
1392
1393static struct platform_device omap_mpuio_device = {
1394 .name = "mpuio",
1395 .id = -1,
1396 .dev = {
1397 .driver = &omap_mpuio_driver.driver,
1398 }
1399 /* could list the /proc/iomem resources */
1400};
1401
1402static inline void mpuio_init(void)
1403{
77640aab
VC		 1404 struct gpio_bank *bank = get_gpio_bank(OMAP_MPUIO(0));
1405 platform_set_drvdata(&omap_mpuio_device, bank);
fcf126d8 1406
11a78b79
DB		 1407 if (platform_driver_register(&omap_mpuio_driver) == 0)
1408 (void) platform_device_register(&omap_mpuio_device);
1409}
1410
1411#else
1412static inline void mpuio_init(void) {}
1413#endif /* 16xx */
1414
e5c56ed3
DB		 1415#else
1416
1417extern struct irq_chip mpuio_irq_chip;
1418
1419#define bank_is_mpuio(bank) 0
11a78b79 1420static inline void mpuio_init(void) {}
e5c56ed3
DB		 1421
1422#endif
1423
1424/*---------------------------------------------------------------------*/
5e1c5ff4 1425
52e31344
DB		 1426/* REVISIT these are stupid implementations! replace by ones that
1427 * don't switch on METHOD_* and which mostly avoid spinlocks
1428 */
1429
1430static int gpio_input(struct gpio_chip *chip, unsigned offset)
1431{
1432 struct gpio_bank *bank;
1433 unsigned long flags;
1434
1435 bank = container_of(chip, struct gpio_bank, chip);
1436 spin_lock_irqsave(&bank->lock, flags);
1437 _set_gpio_direction(bank, offset, 1);
1438 spin_unlock_irqrestore(&bank->lock, flags);
1439 return 0;
1440}
1441
b37c45b8
RQ		 1442static int gpio_is_input(struct gpio_bank *bank, int mask)
1443{
1444 void __iomem *reg = bank->base;
1445
1446 switch (bank->method) {
1447 case METHOD_MPUIO:
5de62b86 1448 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
b37c45b8
RQ		 1449 break;
1450 case METHOD_GPIO_1510:
1451 reg += OMAP1510_GPIO_DIR_CONTROL;
1452 break;
1453 case METHOD_GPIO_1610:
1454 reg += OMAP1610_GPIO_DIRECTION;
1455 break;
7c006926
AB		 1456 case METHOD_GPIO_7XX:
1457 reg += OMAP7XX_GPIO_DIR_CONTROL;
b37c45b8
RQ		 1458 break;
1459 case METHOD_GPIO_24XX:
1460 reg += OMAP24XX_GPIO_OE;
1461 break;
9f096868
C		 1462 case METHOD_GPIO_44XX:
1463 reg += OMAP4_GPIO_OE;
1464 break;
1465 default:
1466 WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method");
1467 return -EINVAL;
b37c45b8
RQ		 1468 }
1469 return __raw_readl(reg) & mask;
1470}
1471
52e31344
DB		 1472static int gpio_get(struct gpio_chip *chip, unsigned offset)
1473{
b37c45b8
RQ		 1474 struct gpio_bank *bank;
1475 void __iomem *reg;
1476 int gpio;
1477 u32 mask;
1478
1479 gpio = chip->base + offset;
1480 bank = get_gpio_bank(gpio);
1481 reg = bank->base;
1482 mask = 1 << get_gpio_index(gpio);
1483
1484 if (gpio_is_input(bank, mask))
1485 return _get_gpio_datain(bank, gpio);
1486 else
1487 return _get_gpio_dataout(bank, gpio);
52e31344
DB		 1488}
1489
1490static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1491{
1492 struct gpio_bank *bank;
1493 unsigned long flags;
1494
1495 bank = container_of(chip, struct gpio_bank, chip);
1496 spin_lock_irqsave(&bank->lock, flags);
1497 _set_gpio_dataout(bank, offset, value);
1498 _set_gpio_direction(bank, offset, 0);
1499 spin_unlock_irqrestore(&bank->lock, flags);
1500 return 0;
1501}
1502
168ef3d9
FB		 1503static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
1504 unsigned debounce)
1505{
1506 struct gpio_bank *bank;
1507 unsigned long flags;
1508
1509 bank = container_of(chip, struct gpio_bank, chip);
77640aab
VC		 1510
1511 if (!bank->dbck) {
1512 bank->dbck = clk_get(bank->dev, "dbclk");
1513 if (IS_ERR(bank->dbck))
1514 dev_err(bank->dev, "Could not get gpio dbck\n");
1515 }
1516
168ef3d9
FB		 1517 spin_lock_irqsave(&bank->lock, flags);
1518 _set_gpio_debounce(bank, offset, debounce);
1519 spin_unlock_irqrestore(&bank->lock, flags);
1520
1521 return 0;
1522}
1523
52e31344
DB		 1524static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1525{
1526 struct gpio_bank *bank;
1527 unsigned long flags;
1528
1529 bank = container_of(chip, struct gpio_bank, chip);
1530 spin_lock_irqsave(&bank->lock, flags);
1531 _set_gpio_dataout(bank, offset, value);
1532 spin_unlock_irqrestore(&bank->lock, flags);
1533}
1534
a007b709
DB		 1535static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1536{
1537 struct gpio_bank *bank;
1538
1539 bank = container_of(chip, struct gpio_bank, chip);
1540 return bank->virtual_irq_start + offset;
1541}
1542
52e31344
DB		 1543/*---------------------------------------------------------------------*/
1544
9a748053 1545static void __init omap_gpio_show_rev(struct gpio_bank *bank)
9f7065da
TL		 1546{
1547 u32 rev;
1548
9a748053
TL		 1549 if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO))
1550 rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION);
9f7065da 1551 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
9a748053 1552 rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION);
9f7065da 1553 else if (cpu_is_omap44xx())
9a748053 1554 rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION);
9f7065da
TL		 1555 else
1556 return;
1557
1558 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1559 (rev >> 4) & 0x0f, rev & 0x0f);
1560}
1561
8ba55c5c
DB		 1562/* This lock class tells lockdep that GPIO irqs are in a different
1563 * category than their parents, so it won't report false recursion.
1564 */
1565static struct lock_class_key gpio_lock_class;
1566
77640aab
VC		 1567static inline int init_gpio_info(struct platform_device *pdev)
1568{
1569 /* TODO: Analyze removing gpio_bank_count usage from driver code */
1570 gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
1571 GFP_KERNEL);
1572 if (!gpio_bank) {
1573 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1574 return -ENOMEM;
1575 }
1576 return 0;
1577}
1578
1579/* TODO: Cleanup cpu_is_* checks */
2fae7fbe
VC		 1580static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1581{
1582 if (cpu_class_is_omap2()) {
1583 if (cpu_is_omap44xx()) {
1584 __raw_writel(0xffffffff, bank->base +
1585 OMAP4_GPIO_IRQSTATUSCLR0);
1586 __raw_writel(0x00000000, bank->base +
1587 OMAP4_GPIO_DEBOUNCENABLE);
1588 /* Initialize interface clk ungated, module enabled */
1589 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1590 } else if (cpu_is_omap34xx()) {
1591 __raw_writel(0x00000000, bank->base +
1592 OMAP24XX_GPIO_IRQENABLE1);
1593 __raw_writel(0xffffffff, bank->base +
1594 OMAP24XX_GPIO_IRQSTATUS1);
1595 __raw_writel(0x00000000, bank->base +
1596 OMAP24XX_GPIO_DEBOUNCE_EN);
1597
1598 /* Initialize interface clk ungated, module enabled */
1599 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1600 } else if (cpu_is_omap24xx()) {
1601 static const u32 non_wakeup_gpios[] = {
1602 0xe203ffc0, 0x08700040
1603 };
1604 if (id < ARRAY_SIZE(non_wakeup_gpios))
1605 bank->non_wakeup_gpios = non_wakeup_gpios[id];
1606 }
1607 } else if (cpu_class_is_omap1()) {
1608 if (bank_is_mpuio(bank))
5de62b86
TL		 1609 __raw_writew(0xffff, bank->base +
1610 OMAP_MPUIO_GPIO_MASKIT / bank->stride);
2fae7fbe
VC		 1611 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1612 __raw_writew(0xffff, bank->base
1613 + OMAP1510_GPIO_INT_MASK);
1614 __raw_writew(0x0000, bank->base
1615 + OMAP1510_GPIO_INT_STATUS);
1616 }
1617 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1618 __raw_writew(0x0000, bank->base
1619 + OMAP1610_GPIO_IRQENABLE1);
1620 __raw_writew(0xffff, bank->base
1621 + OMAP1610_GPIO_IRQSTATUS1);
1622 __raw_writew(0x0014, bank->base
1623 + OMAP1610_GPIO_SYSCONFIG);
1624
1625 /*
1626 * Enable system clock for GPIO module.
1627 * The CAM_CLK_CTRL *is* really the right place.
1628 */
1629 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1630 ULPD_CAM_CLK_CTRL);
1631 }
1632 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1633 __raw_writel(0xffffffff, bank->base
1634 + OMAP7XX_GPIO_INT_MASK);
1635 __raw_writel(0x00000000, bank->base
1636 + OMAP7XX_GPIO_INT_STATUS);
1637 }
1638 }
1639}
1640
1641static void __init omap_gpio_chip_init(struct gpio_bank *bank)
1642{
77640aab 1643 int j;
2fae7fbe
VC		 1644 static int gpio;
1645
2fae7fbe
VC		 1646 bank->mod_usage = 0;
1647 /*
1648 * REVISIT eventually switch from OMAP-specific gpio structs
1649 * over to the generic ones
1650 */
1651 bank->chip.request = omap_gpio_request;
1652 bank->chip.free = omap_gpio_free;
1653 bank->chip.direction_input = gpio_input;
1654 bank->chip.get = gpio_get;
1655 bank->chip.direction_output = gpio_output;
1656 bank->chip.set_debounce = gpio_debounce;
1657 bank->chip.set = gpio_set;
1658 bank->chip.to_irq = gpio_2irq;
1659 if (bank_is_mpuio(bank)) {
1660 bank->chip.label = "mpuio";
1661#ifdef CONFIG_ARCH_OMAP16XX
1662 bank->chip.dev = &omap_mpuio_device.dev;
1663#endif
1664 bank->chip.base = OMAP_MPUIO(0);
1665 } else {
1666 bank->chip.label = "gpio";
1667 bank->chip.base = gpio;
1668 gpio += bank_width;
1669 }
1670 bank->chip.ngpio = bank_width;
1671
1672 gpiochip_add(&bank->chip);
1673
1674 for (j = bank->virtual_irq_start;
1675 j < bank->virtual_irq_start + bank_width; j++) {
1a9b5878
FB		 1676 struct irq_desc *d = irq_to_desc(j);
1677
1678 lockdep_set_class(&d->lock, &gpio_lock_class);
2fae7fbe
VC		 1679 set_irq_chip_data(j, bank);
1680 if (bank_is_mpuio(bank))
1681 set_irq_chip(j, &mpuio_irq_chip);
1682 else
1683 set_irq_chip(j, &gpio_irq_chip);
1684 set_irq_handler(j, handle_simple_irq);
1685 set_irq_flags(j, IRQF_VALID);
1686 }
1687 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1688 set_irq_data(bank->irq, bank);
1689}
1690
77640aab 1691static int __devinit omap_gpio_probe(struct platform_device *pdev)
5e1c5ff4 1692{
77640aab
VC		 1693 static int gpio_init_done;
1694 struct omap_gpio_platform_data *pdata;
1695 struct resource *res;
1696 int id;
5e1c5ff4
TL		 1697 struct gpio_bank *bank;
1698
77640aab
VC		 1699 if (!pdev->dev.platform_data)
1700 return -EINVAL;
5e1c5ff4 1701
77640aab 1702 pdata = pdev->dev.platform_data;
56a25641 1703
77640aab
VC		 1704 if (!gpio_init_done) {
1705 int ret;
5492fb1a 1706
77640aab
VC		 1707 ret = init_gpio_info(pdev);
1708 if (ret)
1709 return ret;
5492fb1a 1710 }
5492fb1a 1711
77640aab
VC		 1712 id = pdev->id;
1713 bank = &gpio_bank[id];
92105bb7 1714
77640aab
VC		 1715 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1716 if (unlikely(!res)) {
1717 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
1718 return -ENODEV;
44169075 1719 }
5e1c5ff4 1720
77640aab
VC		 1721 bank->irq = res->start;
1722 bank->virtual_irq_start = pdata->virtual_irq_start;
1723 bank->method = pdata->bank_type;
1724 bank->dev = &pdev->dev;
1725 bank->dbck_flag = pdata->dbck_flag;
5de62b86 1726 bank->stride = pdata->bank_stride;
77640aab 1727 bank_width = pdata->bank_width;
9f7065da 1728
77640aab 1729 spin_lock_init(&bank->lock);
9f7065da 1730
77640aab
VC		 1731 /* Static mapping, never released */
1732 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1733 if (unlikely(!res)) {
1734 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
1735 return -ENODEV;
1736 }
89db9482 1737
77640aab
VC		 1738 bank->base = ioremap(res->start, resource_size(res));
1739 if (!bank->base) {
1740 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
1741 return -ENOMEM;
5e1c5ff4
TL		 1742 }
1743
77640aab
VC		 1744 pm_runtime_enable(bank->dev);
1745 pm_runtime_get_sync(bank->dev);
1746
1747 omap_gpio_mod_init(bank, id);
1748 omap_gpio_chip_init(bank);
9a748053 1749 omap_gpio_show_rev(bank);
9f7065da 1750
77640aab
VC		 1751 if (!gpio_init_done)
1752 gpio_init_done = 1;
1753
5e1c5ff4
TL		 1754 return 0;
1755}
1756
140455fa 1757#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
92105bb7
TL		 1758static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1759{
1760 int i;
1761
5492fb1a 1762 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
92105bb7
TL		 1763 return 0;
1764
1765 for (i = 0; i < gpio_bank_count; i++) {
1766 struct gpio_bank *bank = &gpio_bank[i];
1767 void __iomem *wake_status;
1768 void __iomem *wake_clear;
1769 void __iomem *wake_set;
a6472533 1770 unsigned long flags;
92105bb7
TL		 1771
1772 switch (bank->method) {
e5c56ed3 1773#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1774 case METHOD_GPIO_1610:
1775 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1776 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1777 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1778 break;
e5c56ed3 1779#endif
a8eb7ca0 1780#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7 1781 case METHOD_GPIO_24XX:
723fdb78 1782 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
92105bb7
TL		 1783 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1784 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1785 break;
78a1a6d3
SR		 1786#endif
1787#ifdef CONFIG_ARCH_OMAP4
3f1686a9 1788 case METHOD_GPIO_44XX:
78a1a6d3
SR		 1789 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1790 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1791 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1792 break;
e5c56ed3 1793#endif
92105bb7
TL		 1794 default:
1795 continue;
1796 }
1797
a6472533 1798 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1799 bank->saved_wakeup = __raw_readl(wake_status);
1800 __raw_writel(0xffffffff, wake_clear);
1801 __raw_writel(bank->suspend_wakeup, wake_set);
a6472533 1802 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 1803 }
1804
1805 return 0;
1806}
1807
1808static int omap_gpio_resume(struct sys_device *dev)
1809{
1810 int i;
1811
723fdb78 1812 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
92105bb7
TL		 1813 return 0;
1814
1815 for (i = 0; i < gpio_bank_count; i++) {
1816 struct gpio_bank *bank = &gpio_bank[i];
1817 void __iomem *wake_clear;
1818 void __iomem *wake_set;
a6472533 1819 unsigned long flags;
92105bb7
TL		 1820
1821 switch (bank->method) {
e5c56ed3 1822#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1823 case METHOD_GPIO_1610:
1824 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1825 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1826 break;
e5c56ed3 1827#endif
a8eb7ca0 1828#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7 1829 case METHOD_GPIO_24XX:
0d9356cb
TL		 1830 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1831 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
92105bb7 1832 break;
78a1a6d3
SR		 1833#endif
1834#ifdef CONFIG_ARCH_OMAP4
3f1686a9 1835 case METHOD_GPIO_44XX:
78a1a6d3
SR		 1836 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1837 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1838 break;
e5c56ed3 1839#endif
92105bb7
TL		 1840 default:
1841 continue;
1842 }
1843
a6472533 1844 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1845 __raw_writel(0xffffffff, wake_clear);
1846 __raw_writel(bank->saved_wakeup, wake_set);
a6472533 1847 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 1848 }
1849
1850 return 0;
1851}
1852
1853static struct sysdev_class omap_gpio_sysclass = {
af5ca3f4 1854 .name = "gpio",
92105bb7
TL		 1855 .suspend = omap_gpio_suspend,
1856 .resume = omap_gpio_resume,
1857};
1858
1859static struct sys_device omap_gpio_device = {
1860 .id = 0,
1861 .cls = &omap_gpio_sysclass,
1862};
3ac4fa99
JY		 1863
1864#endif
1865
140455fa 1866#ifdef CONFIG_ARCH_OMAP2PLUS
3ac4fa99
JY		 1867
1868static int workaround_enabled;
1869
72e06d08 1870void omap2_gpio_prepare_for_idle(int off_mode)
3ac4fa99
JY		 1871{
1872 int i, c = 0;
a118b5f3 1873 int min = 0;
3ac4fa99 1874
a118b5f3
TK		 1875 if (cpu_is_omap34xx())
1876 min = 1;
43ffcd9a 1877
a118b5f3 1878 for (i = min; i < gpio_bank_count; i++) {
3ac4fa99 1879 struct gpio_bank *bank = &gpio_bank[i];
ca828760 1880 u32 l1 = 0, l2 = 0;
0aed0435 1881 int j;
3ac4fa99 1882
0aed0435 1883 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
8865b9b6
KH		 1884 clk_disable(bank->dbck);
1885
72e06d08 1886 if (!off_mode)
43ffcd9a
KH		 1887 continue;
1888
1889 /* If going to OFF, remove triggering for all
1890 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1891 * generated. See OMAP2420 Errata item 1.101. */
3ac4fa99
JY		 1892 if (!(bank->enabled_non_wakeup_gpios))
1893 continue;
3f1686a9
TL		 1894
1895 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1896 bank->saved_datain = __raw_readl(bank->base +
1897 OMAP24XX_GPIO_DATAIN);
1898 l1 = __raw_readl(bank->base +
1899 OMAP24XX_GPIO_FALLINGDETECT);
1900 l2 = __raw_readl(bank->base +
1901 OMAP24XX_GPIO_RISINGDETECT);
1902 }
1903
1904 if (cpu_is_omap44xx()) {
1905 bank->saved_datain = __raw_readl(bank->base +
1906 OMAP4_GPIO_DATAIN);
1907 l1 = __raw_readl(bank->base +
1908 OMAP4_GPIO_FALLINGDETECT);
1909 l2 = __raw_readl(bank->base +
1910 OMAP4_GPIO_RISINGDETECT);
1911 }
1912
3ac4fa99
JY		 1913 bank->saved_fallingdetect = l1;
1914 bank->saved_risingdetect = l2;
1915 l1 &= ~bank->enabled_non_wakeup_gpios;
1916 l2 &= ~bank->enabled_non_wakeup_gpios;
3f1686a9
TL		 1917
1918 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1919 __raw_writel(l1, bank->base +
1920 OMAP24XX_GPIO_FALLINGDETECT);
1921 __raw_writel(l2, bank->base +
1922 OMAP24XX_GPIO_RISINGDETECT);
1923 }
1924
1925 if (cpu_is_omap44xx()) {
1926 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1927 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1928 }
1929
3ac4fa99
JY		 1930 c++;
1931 }
1932 if (!c) {
1933 workaround_enabled = 0;
1934 return;
1935 }
1936 workaround_enabled = 1;
1937}
1938
43ffcd9a 1939void omap2_gpio_resume_after_idle(void)
3ac4fa99
JY		 1940{
1941 int i;
a118b5f3 1942 int min = 0;
3ac4fa99 1943
a118b5f3
TK		 1944 if (cpu_is_omap34xx())
1945 min = 1;
1946 for (i = min; i < gpio_bank_count; i++) {
3ac4fa99 1947 struct gpio_bank *bank = &gpio_bank[i];
ca828760 1948 u32 l = 0, gen, gen0, gen1;
0aed0435 1949 int j;
3ac4fa99 1950
0aed0435 1951 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
8865b9b6
KH		 1952 clk_enable(bank->dbck);
1953
43ffcd9a
KH		 1954 if (!workaround_enabled)
1955 continue;
1956
3ac4fa99
JY		 1957 if (!(bank->enabled_non_wakeup_gpios))
1958 continue;
3f1686a9
TL		 1959
1960 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1961 __raw_writel(bank->saved_fallingdetect,
3ac4fa99 1962 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
3f1686a9 1963 __raw_writel(bank->saved_risingdetect,
3ac4fa99 1964 bank->base + OMAP24XX_GPIO_RISINGDETECT);
3f1686a9
TL		 1965 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1966 }
1967
1968 if (cpu_is_omap44xx()) {
1969 __raw_writel(bank->saved_fallingdetect,
78a1a6d3 1970 bank->base + OMAP4_GPIO_FALLINGDETECT);
3f1686a9 1971 __raw_writel(bank->saved_risingdetect,
78a1a6d3 1972 bank->base + OMAP4_GPIO_RISINGDETECT);
3f1686a9
TL		 1973 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1974 }
1975
3ac4fa99
JY		 1976 /* Check if any of the non-wakeup interrupt GPIOs have changed
1977 * state. If so, generate an IRQ by software. This is
1978 * horribly racy, but it's the best we can do to work around
1979 * this silicon bug. */
3ac4fa99 1980 l ^= bank->saved_datain;
a118b5f3 1981 l &= bank->enabled_non_wakeup_gpios;
82dbb9d3
EN		 1982
1983 /*
1984 * No need to generate IRQs for the rising edge for gpio IRQs
1985 * configured with falling edge only; and vice versa.
1986 */
1987 gen0 = l & bank->saved_fallingdetect;
1988 gen0 &= bank->saved_datain;
1989
1990 gen1 = l & bank->saved_risingdetect;
1991 gen1 &= ~(bank->saved_datain);
1992
1993 /* FIXME: Consider GPIO IRQs with level detections properly! */
1994 gen = l & (~(bank->saved_fallingdetect) &
1995 ~(bank->saved_risingdetect));
1996 /* Consider all GPIO IRQs needed to be updated */
1997 gen |= gen0 | gen1;
1998
1999 if (gen) {
3ac4fa99 2000 u32 old0, old1;
3f1686a9 2001
f00d6497 2002 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
3f1686a9
TL		 2003 old0 = __raw_readl(bank->base +
2004 OMAP24XX_GPIO_LEVELDETECT0);
2005 old1 = __raw_readl(bank->base +
2006 OMAP24XX_GPIO_LEVELDETECT1);
f00d6497 2007 __raw_writel(old0 | gen, bank->base +
82dbb9d3 2008 OMAP24XX_GPIO_LEVELDETECT0);
f00d6497 2009 __raw_writel(old1 | gen, bank->base +
82dbb9d3 2010 OMAP24XX_GPIO_LEVELDETECT1);
f00d6497 2011 __raw_writel(old0, bank->base +
3f1686a9 2012 OMAP24XX_GPIO_LEVELDETECT0);
f00d6497 2013 __raw_writel(old1, bank->base +
3f1686a9
TL		 2014 OMAP24XX_GPIO_LEVELDETECT1);
2015 }
2016
2017 if (cpu_is_omap44xx()) {
2018 old0 = __raw_readl(bank->base +
78a1a6d3 2019 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 2020 old1 = __raw_readl(bank->base +
78a1a6d3 2021 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 2022 __raw_writel(old0 | l, bank->base +
78a1a6d3 2023 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 2024 __raw_writel(old1 | l, bank->base +
78a1a6d3 2025 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 2026 __raw_writel(old0, bank->base +
78a1a6d3 2027 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 2028 __raw_writel(old1, bank->base +
78a1a6d3 2029 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 2030 }
3ac4fa99
JY		 2031 }
2032 }
2033
2034}
2035
92105bb7
TL		 2036#endif
2037
a8eb7ca0 2038#ifdef CONFIG_ARCH_OMAP3
40c670f0
RN		 2039/* save the registers of bank 2-6 */
2040void omap_gpio_save_context(void)
2041{
2042 int i;
2043
2044 /* saving banks from 2-6 only since GPIO1 is in WKUP */
2045 for (i = 1; i < gpio_bank_count; i++) {
2046 struct gpio_bank *bank = &gpio_bank[i];
40c670f0
RN		 2047 gpio_context[i].irqenable1 =
2048 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
2049 gpio_context[i].irqenable2 =
2050 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
2051 gpio_context[i].wake_en =
2052 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
2053 gpio_context[i].ctrl =
2054 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
2055 gpio_context[i].oe =
2056 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
2057 gpio_context[i].leveldetect0 =
2058 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2059 gpio_context[i].leveldetect1 =
2060 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2061 gpio_context[i].risingdetect =
2062 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
2063 gpio_context[i].fallingdetect =
2064 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2065 gpio_context[i].dataout =
2066 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
40c670f0
RN		 2067 }
2068}
2069
2070/* restore the required registers of bank 2-6 */
2071void omap_gpio_restore_context(void)
2072{
2073 int i;
2074
2075 for (i = 1; i < gpio_bank_count; i++) {
2076 struct gpio_bank *bank = &gpio_bank[i];
40c670f0
RN		 2077 __raw_writel(gpio_context[i].irqenable1,
2078 bank->base + OMAP24XX_GPIO_IRQENABLE1);
2079 __raw_writel(gpio_context[i].irqenable2,
2080 bank->base + OMAP24XX_GPIO_IRQENABLE2);
2081 __raw_writel(gpio_context[i].wake_en,
2082 bank->base + OMAP24XX_GPIO_WAKE_EN);
2083 __raw_writel(gpio_context[i].ctrl,
2084 bank->base + OMAP24XX_GPIO_CTRL);
2085 __raw_writel(gpio_context[i].oe,
2086 bank->base + OMAP24XX_GPIO_OE);
2087 __raw_writel(gpio_context[i].leveldetect0,
2088 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2089 __raw_writel(gpio_context[i].leveldetect1,
2090 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2091 __raw_writel(gpio_context[i].risingdetect,
2092 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2093 __raw_writel(gpio_context[i].fallingdetect,
2094 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2095 __raw_writel(gpio_context[i].dataout,
2096 bank->base + OMAP24XX_GPIO_DATAOUT);
40c670f0
RN		 2097 }
2098}
2099#endif
2100
77640aab
VC		 2101static struct platform_driver omap_gpio_driver = {
2102 .probe = omap_gpio_probe,
2103 .driver = {
2104 .name = "omap_gpio",
2105 },
2106};
2107
5e1c5ff4 2108/*
77640aab
VC		 2109 * gpio driver register needs to be done before
2110 * machine_init functions access gpio APIs.
2111 * Hence omap_gpio_drv_reg() is a postcore_initcall.
5e1c5ff4 2112 */
77640aab 2113static int __init omap_gpio_drv_reg(void)
5e1c5ff4 2114{
77640aab 2115 return platform_driver_register(&omap_gpio_driver);
5e1c5ff4 2116}
77640aab 2117postcore_initcall(omap_gpio_drv_reg);
5e1c5ff4 2118
92105bb7
TL		 2119static int __init omap_gpio_sysinit(void)
2120{
2121 int ret = 0;
2122
11a78b79
DB		 2123 mpuio_init();
2124
140455fa 2125#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
5492fb1a 2126 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
92105bb7
TL		 2127 if (ret == 0) {
2128 ret = sysdev_class_register(&omap_gpio_sysclass);
2129 if (ret == 0)
2130 ret = sysdev_register(&omap_gpio_device);
2131 }
2132 }
2133#endif
2134
2135 return ret;
2136}
2137
92105bb7 2138arch_initcall(omap_gpio_sysinit);
kernel source for telekom puls (alcatel/mediatek)