Commit | Line | Data |
---|---|---|
28ad94ec | 1 | /* |
a0719f52 | 2 | * linux/arch/arm/plat-nomadik/timer.c |
28ad94ec AR |
3 | * |
4 | * Copyright (C) 2008 STMicroelectronics | |
b102c01f | 5 | * Copyright (C) 2010 Alessandro Rubini |
8fbb97a2 | 6 | * Copyright (C) 2010 Linus Walleij for ST-Ericsson |
28ad94ec AR |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2, as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | #include <linux/init.h> | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/irq.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/clockchips.h> | |
ba327b1e | 17 | #include <linux/clk.h> |
28ad94ec | 18 | #include <linux/jiffies.h> |
ba327b1e | 19 | #include <linux/err.h> |
5e06b649 | 20 | #include <linux/sched.h> |
28ad94ec | 21 | #include <asm/mach/time.h> |
ec05aa13 | 22 | #include <asm/sched_clock.h> |
28ad94ec | 23 | |
59b559d7 | 24 | #include <plat/mtu.h> |
28ad94ec | 25 | |
8fbb97a2 | 26 | void __iomem *mtu_base; /* Assigned by machine code */ |
59b559d7 | 27 | |
2a847513 LW |
28 | /* |
29 | * Kernel assumes that sched_clock can be called early | |
30 | * but the MTU may not yet be initialized. | |
31 | */ | |
32 | static cycle_t nmdk_read_timer_dummy(struct clocksource *cs) | |
33 | { | |
34 | return 0; | |
35 | } | |
36 | ||
b102c01f | 37 | /* clocksource: MTU decrements, so we negate the value being read. */ |
28ad94ec AR |
38 | static cycle_t nmdk_read_timer(struct clocksource *cs) |
39 | { | |
b102c01f | 40 | return -readl(mtu_base + MTU_VAL(0)); |
28ad94ec AR |
41 | } |
42 | ||
43 | static struct clocksource nmdk_clksrc = { | |
44 | .name = "mtu_0", | |
b102c01f | 45 | .rating = 200, |
2a847513 | 46 | .read = nmdk_read_timer_dummy, |
b102c01f | 47 | .mask = CLOCKSOURCE_MASK(32), |
28ad94ec AR |
48 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
49 | }; | |
50 | ||
2a847513 LW |
51 | /* |
52 | * Override the global weak sched_clock symbol with this | |
53 | * local implementation which uses the clocksource to get some | |
8fbb97a2 | 54 | * better resolution when scheduling the kernel. |
2a847513 | 55 | */ |
ec05aa13 | 56 | static DEFINE_CLOCK_DATA(cd); |
8fbb97a2 | 57 | |
2a847513 LW |
58 | unsigned long long notrace sched_clock(void) |
59 | { | |
ec05aa13 | 60 | u32 cyc; |
8fbb97a2 LW |
61 | |
62 | if (unlikely(!mtu_base)) | |
63 | return 0; | |
64 | ||
ec05aa13 RK |
65 | cyc = -readl(mtu_base + MTU_VAL(0)); |
66 | return cyc_to_sched_clock(&cd, cyc, (u32)~0); | |
8fbb97a2 LW |
67 | } |
68 | ||
ec05aa13 | 69 | static void notrace nomadik_update_sched_clock(void) |
8fbb97a2 | 70 | { |
ec05aa13 RK |
71 | u32 cyc = -readl(mtu_base + MTU_VAL(0)); |
72 | update_sched_clock(&cd, cyc, (u32)~0); | |
2a847513 LW |
73 | } |
74 | ||
b102c01f | 75 | /* Clockevent device: use one-shot mode */ |
28ad94ec AR |
76 | static void nmdk_clkevt_mode(enum clock_event_mode mode, |
77 | struct clock_event_device *dev) | |
78 | { | |
b102c01f AR |
79 | u32 cr; |
80 | ||
28ad94ec AR |
81 | switch (mode) { |
82 | case CLOCK_EVT_MODE_PERIODIC: | |
b102c01f | 83 | pr_err("%s: periodic mode not supported\n", __func__); |
28ad94ec AR |
84 | break; |
85 | case CLOCK_EVT_MODE_ONESHOT: | |
b102c01f AR |
86 | /* Load highest value, enable device, enable interrupts */ |
87 | cr = readl(mtu_base + MTU_CR(1)); | |
88 | writel(0, mtu_base + MTU_LR(1)); | |
89 | writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(1)); | |
a0719f52 | 90 | writel(1 << 1, mtu_base + MTU_IMSC); |
b102c01f | 91 | break; |
28ad94ec AR |
92 | case CLOCK_EVT_MODE_SHUTDOWN: |
93 | case CLOCK_EVT_MODE_UNUSED: | |
b102c01f AR |
94 | /* disable irq */ |
95 | writel(0, mtu_base + MTU_IMSC); | |
2917947a LW |
96 | /* disable timer */ |
97 | cr = readl(mtu_base + MTU_CR(1)); | |
98 | cr &= ~MTU_CRn_ENA; | |
99 | writel(cr, mtu_base + MTU_CR(1)); | |
100 | /* load some high default value */ | |
101 | writel(0xffffffff, mtu_base + MTU_LR(1)); | |
28ad94ec AR |
102 | break; |
103 | case CLOCK_EVT_MODE_RESUME: | |
104 | break; | |
105 | } | |
106 | } | |
107 | ||
b102c01f AR |
108 | static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev) |
109 | { | |
110 | /* writing the value has immediate effect */ | |
111 | writel(evt, mtu_base + MTU_LR(1)); | |
112 | return 0; | |
113 | } | |
114 | ||
28ad94ec | 115 | static struct clock_event_device nmdk_clkevt = { |
b102c01f AR |
116 | .name = "mtu_1", |
117 | .features = CLOCK_EVT_FEAT_ONESHOT, | |
b102c01f | 118 | .rating = 200, |
28ad94ec | 119 | .set_mode = nmdk_clkevt_mode, |
b102c01f | 120 | .set_next_event = nmdk_clkevt_next, |
28ad94ec AR |
121 | }; |
122 | ||
123 | /* | |
b102c01f | 124 | * IRQ Handler for timer 1 of the MTU block. |
28ad94ec AR |
125 | */ |
126 | static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id) | |
127 | { | |
b102c01f | 128 | struct clock_event_device *evdev = dev_id; |
28ad94ec | 129 | |
b102c01f AR |
130 | writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */ |
131 | evdev->event_handler(evdev); | |
28ad94ec AR |
132 | return IRQ_HANDLED; |
133 | } | |
134 | ||
28ad94ec AR |
135 | static struct irqaction nmdk_timer_irq = { |
136 | .name = "Nomadik Timer Tick", | |
137 | .flags = IRQF_DISABLED | IRQF_TIMER, | |
138 | .handler = nmdk_timer_interrupt, | |
b102c01f | 139 | .dev_id = &nmdk_clkevt, |
28ad94ec AR |
140 | }; |
141 | ||
59b559d7 | 142 | void __init nmdk_timer_init(void) |
28ad94ec | 143 | { |
28ad94ec | 144 | unsigned long rate; |
ba327b1e | 145 | struct clk *clk0; |
a0719f52 | 146 | u32 cr = MTU_CRn_32BITS; |
ba327b1e LW |
147 | |
148 | clk0 = clk_get_sys("mtu0", NULL); | |
149 | BUG_ON(IS_ERR(clk0)); | |
150 | ||
ba327b1e | 151 | clk_enable(clk0); |
b102c01f AR |
152 | |
153 | /* | |
a0719f52 LW |
154 | * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz |
155 | * for ux500. | |
156 | * Use a divide-by-16 counter if the tick rate is more than 32MHz. | |
157 | * At 32 MHz, the timer (with 32 bit counter) can be programmed | |
158 | * to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer | |
159 | * with 16 gives too low timer resolution. | |
b102c01f | 160 | */ |
ba327b1e | 161 | rate = clk_get_rate(clk0); |
a0719f52 | 162 | if (rate > 32000000) { |
b102c01f AR |
163 | rate /= 16; |
164 | cr |= MTU_CRn_PRESCALE_16; | |
165 | } else { | |
166 | cr |= MTU_CRn_PRESCALE_1; | |
167 | } | |
28ad94ec | 168 | |
b102c01f AR |
169 | /* Timer 0 is the free running clocksource */ |
170 | writel(cr, mtu_base + MTU_CR(0)); | |
171 | writel(0, mtu_base + MTU_LR(0)); | |
172 | writel(0, mtu_base + MTU_BGLR(0)); | |
173 | writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0)); | |
28ad94ec | 174 | |
8fbb97a2 | 175 | /* Now the clock source is ready */ |
2a847513 | 176 | nmdk_clksrc.read = nmdk_read_timer; |
28ad94ec | 177 | |
8492fd28 | 178 | if (clocksource_register_hz(&nmdk_clksrc, rate)) |
b102c01f AR |
179 | pr_err("timer: failed to initialize clock source %s\n", |
180 | nmdk_clksrc.name); | |
181 | ||
ec05aa13 | 182 | init_sched_clock(&cd, nomadik_update_sched_clock, 32, rate); |
8fbb97a2 | 183 | |
99f76891 LW |
184 | /* Timer 1 is used for events */ |
185 | ||
2917947a LW |
186 | clockevents_calc_mult_shift(&nmdk_clkevt, rate, MTU_MIN_RANGE); |
187 | ||
b102c01f | 188 | writel(cr | MTU_CRn_ONESHOT, mtu_base + MTU_CR(1)); /* off, currently */ |
2917947a | 189 | |
b102c01f AR |
190 | nmdk_clkevt.max_delta_ns = |
191 | clockevent_delta2ns(0xffffffff, &nmdk_clkevt); | |
192 | nmdk_clkevt.min_delta_ns = | |
193 | clockevent_delta2ns(0x00000002, &nmdk_clkevt); | |
194 | nmdk_clkevt.cpumask = cpumask_of(0); | |
28ad94ec AR |
195 | |
196 | /* Register irq and clockevents */ | |
197 | setup_irq(IRQ_MTU0, &nmdk_timer_irq); | |
28ad94ec AR |
198 | clockevents_register_device(&nmdk_clkevt); |
199 | } |