projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| 52c543f9 QJ |
1 | /* |
| 2 | * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org> | |
| a003708a | 3 | * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. |
| 52c543f9 QJ |
4 | */ |
| 5 | ||
| 6 | /* | |
| 7 | * This program is free software; you can redistribute it and/or modify | |
| 8 | * it under the terms of the GNU General Public License version 2 as | |
| 9 | * published by the Free Software Foundation. | |
| 10 | */ | |
| 11 | ||
| a2449091 SH |
12 | #include <mach/hardware.h> |
| 13 | ||
| 479c901f DA |
14 | #define AVIC_NIMASK 0x04 |
| 15 | ||
| 52c543f9 QJ |
16 | @ this macro disables fast irq (not implemented) |
| 17 | .macro disable_fiq | |
| 18 | .endm | |
| 19 | ||
| 20 | .macro get_irqnr_preamble, base, tmp | |
| a003708a | 21 | #ifndef CONFIG_MXC_TZIC |
| 12b8eb86 SH |
22 | ldr \base, =avic_base |
| 23 | ldr \base, [\base] | |
| 479c901f DA |
24 | #ifdef CONFIG_MXC_IRQ_PRIOR |
| 25 | ldr r4, [\base, #AVIC_NIMASK] | |
| 26 | #endif | |
| a003708a AK |
27 | #elif defined CONFIG_MXC_TZIC |
| 28 | ldr \base, =tzic_base | |
| 29 | ldr \base, [\base] | |
| 30 | #endif /* CONFIG_MXC_TZIC */ | |
| 52c543f9 QJ |
31 | .endm |
| 32 | ||
| 33 | .macro arch_ret_to_user, tmp1, tmp2 | |
| 34 | .endm | |
| 35 | ||
| 25985edc | 36 | @ this macro checks which interrupt occurred |
| 52c543f9 | 37 | @ and returns its number in irqnr |
| 25985edc | 38 | @ and returns if an interrupt occurred in irqstat |
| 52c543f9 | 39 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp |
| a003708a | 40 | #ifndef CONFIG_MXC_TZIC |
| 52c543f9 QJ |
41 | @ Load offset & priority of the highest priority |
| 42 | @ interrupt pending from AVIC_NIVECSR | |
| 43 | ldr \irqstat, [\base, #0x40] | |
| 44 | @ Shift to get the decoded IRQ number, using ASR so | |
| 45 | @ 'no interrupt pending' becomes 0xffffffff | |
| 46 | mov \irqnr, \irqstat, asr #16 | |
| 47 | @ set zero flag if IRQ + 1 == 0 | |
| 48 | adds \tmp, \irqnr, #1 | |
| 479c901f DA |
49 | #ifdef CONFIG_MXC_IRQ_PRIOR |
| 50 | bicne \tmp, \irqstat, #0xFFFFFFE0 | |
| 51 | strne \tmp, [\base, #AVIC_NIMASK] | |
| 52 | streq r4, [\base, #AVIC_NIMASK] | |
| a003708a AK |
53 | #endif |
| 54 | #elif defined CONFIG_MXC_TZIC | |
| 55 | @ Load offset & priority of the highest priority | |
| 56 | @ interrupt pending. | |
| cdc3f106 | 57 | @ 0x080 is INTSEC0 register |
| a003708a AK |
58 | @ 0xD80 is HIPND0 register |
| 59 | mov \irqnr, #0 | |
| cdc3f106 PH |
60 | 1000: add \irqstat, \base, \irqnr, lsr #3 |
| 61 | ldr \tmp, [\irqstat, #0xd80] | |
| 62 | ldr \irqstat, [\irqstat, #0x080] | |
| 63 | ands \tmp, \tmp, \irqstat | |
| 64 | bne 1001f | |
| 65 | add \irqnr, \irqnr, #32 | |
| a003708a AK |
66 | cmp \irqnr, #128 |
| 67 | blo 1000b | |
| 68 | b 2001f | |
| 69 | 1001: mov \irqstat, #1 | |
| 70 | 1002: tst \tmp, \irqstat | |
| 71 | bne 2002f | |
| 72 | movs \tmp, \tmp, lsr #1 | |
| 73 | addne \irqnr, \irqnr, #1 | |
| 74 | bne 1002b | |
| 75 | 2001: | |
| 76 | mov \irqnr, #0 | |
| 77 | 2002: | |
| 78 | movs \irqnr, \irqnr | |
| 479c901f | 79 | #endif |
| 52c543f9 QJ |
80 | .endm |
| 81 | ||
| 82 | @ irq priority table (not used) | |
| 83 | .macro irq_prio_table | |
| 84 | .endm |