[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mm / tlb-fa.S

/*
 *  linux/arch/arm/mm/tlb-fa.S
 *
 *  Copyright (C) 2005 Faraday Corp.
 *  Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
 *
 * Based on tlb-v4wbi.S:
 *  Copyright (C) 1997-2002 Russell King
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  ARM architecture version 4, Faraday variation.
 *  This assume an unified TLBs, with a write buffer, and branch target buffer (BTB)
 *
 *  Processors: FA520 FA526 FA626
 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/asm-offsets.h>
#include <asm/tlbflush.h>
#include "proc-macros.S"


/*
 *	flush_user_tlb_range(start, end, mm)
 *
 *	Invalidate a range of TLB entries in the specified address space.
 *
 *	- start - range start address
 *	- end   - range end address
 *	- mm    - mm_struct describing address space
 */
	.align	4
ENTRY(fa_flush_user_tlb_range)
	vma_vm_mm ip, r2
	act_mm	r3				@ get current->active_mm
	eors	r3, ip, r3			@ == mm ?
	movne	pc, lr				@ no, we dont do anything
	mov	r3, #0
	mcr	p15, 0, r3, c7, c10, 4		@ drain WB
	bic	r0, r0, #0x0ff
	bic	r0, r0, #0xf00
1:	mcr	p15, 0, r0, c8, c7, 1		@ invalidate UTLB entry
	add	r0, r0, #PAGE_SZ
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r3, c7, c10, 4		@ data write barrier
	mov	pc, lr


ENTRY(fa_flush_kern_tlb_range)
	mov	r3, #0
	mcr	p15, 0, r3, c7, c10, 4		@ drain WB
	bic	r0, r0, #0x0ff
	bic	r0, r0, #0xf00
1:	mcr	p15, 0, r0, c8, c7, 1		@ invalidate UTLB entry
	add	r0, r0, #PAGE_SZ
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r3, c7, c10, 4		@ data write barrier
	mcr	p15, 0, r3, c7, c5, 4		@ prefetch flush (isb)
	mov	pc, lr

	__INITDATA

	/* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */
	define_tlb_functions fa, fa_tlb_flags
Commit	Line	Data
28853ac8 PZ	1	/*
	2	* linux/arch/arm/mm/tlb-fa.S
	3	*
	4	* Copyright (C) 2005 Faraday Corp.
	5	* Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
	6	*
	7	* Based on tlb-v4wbi.S:
	8	* Copyright (C) 1997-2002 Russell King
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*
	14	* ARM architecture version 4, Faraday variation.
	15	* This assume an unified TLBs, with a write buffer, and branch target buffer (BTB)
	16	*
	17	* Processors: FA520 FA526 FA626
	18	*/
	19	#include <linux/linkage.h>
	20	#include <linux/init.h>
	21	#include <asm/asm-offsets.h>
	22	#include <asm/tlbflush.h>
	23	#include "proc-macros.S"
	24
	25
	26	/*
	27	* flush_user_tlb_range(start, end, mm)
	28	*
	29	* Invalidate a range of TLB entries in the specified address space.
	30	*
	31	* - start - range start address
	32	* - end - range end address
	33	* - mm - mm_struct describing address space
	34	*/
	35	.align 4
	36	ENTRY(fa_flush_user_tlb_range)
	37	vma_vm_mm ip, r2
	38	act_mm r3 @ get current->active_mm
	39	eors r3, ip, r3 @ == mm ?
	40	movne pc, lr @ no, we dont do anything
	41	mov r3, #0
	42	mcr p15, 0, r3, c7, c10, 4 @ drain WB
	43	bic r0, r0, #0x0ff
	44	bic r0, r0, #0xf00
	45	1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
	46	add r0, r0, #PAGE_SZ
	47	cmp r0, r1
	48	blo 1b
28853ac8 PZ	49	mcr p15, 0, r3, c7, c10, 4 @ data write barrier
	50	mov pc, lr
	51
	52
	53	ENTRY(fa_flush_kern_tlb_range)
	54	mov r3, #0
	55	mcr p15, 0, r3, c7, c10, 4 @ drain WB
	56	bic r0, r0, #0x0ff
	57	bic r0, r0, #0xf00
	58	1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
	59	add r0, r0, #PAGE_SZ
	60	cmp r0, r1
	61	blo 1b
28853ac8	62	mcr p15, 0, r3, c7, c10, 4 @ data write barrier
4348810a	63	mcr p15, 0, r3, c7, c5, 4 @ prefetch flush (isb)
28853ac8 PZ	64	mov pc, lr
	65
	66	__INITDATA
	67
27eebe4c DM	68	/* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */
27eebe4c DM	69	define_tlb_functions fa, fa_tlb_flags