[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mm / proc-v6.S

/*
 *  linux/arch/arm/mm/proc-v6.S
 *
 *  Copyright (C) 2001 Deep Blue Solutions Ltd.
 *  Modified by Catalin Marinas for noMMU support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  This is the "shell" of the ARMv6 processor support.
 */
#include <linux/init.h>
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>

#include "proc-macros.S"

#define D_CACHE_LINE_SIZE	32

#define TTB_C		(1 << 0)
#define TTB_S		(1 << 1)
#define TTB_IMP		(1 << 2)
#define TTB_RGN_NC	(0 << 3)
#define TTB_RGN_WBWA	(1 << 3)
#define TTB_RGN_WT	(2 << 3)
#define TTB_RGN_WB	(3 << 3)

#define TTB_FLAGS_UP	TTB_RGN_WBWA
#define PMD_FLAGS_UP	PMD_SECT_WB
#define TTB_FLAGS_SMP	TTB_RGN_WBWA|TTB_S
#define PMD_FLAGS_SMP	PMD_SECT_WBWA|PMD_SECT_S

ENTRY(cpu_v6_proc_init)
	mov	pc, lr

ENTRY(cpu_v6_proc_fin)
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1000			@ ...i............
	bic	r0, r0, #0x0006			@ .............ca.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	mov	pc, lr

/*
 *	cpu_v6_reset(loc)
 *
 *	Perform a soft reset of the system.  Put the CPU into the
 *	same state as it would be if it had been reset, and branch
 *	to what would be the reset vector.
 *
 *	- loc   - location to jump to for soft reset
 */
	.align	5
ENTRY(cpu_v6_reset)
	mov	pc, r0

/*
 *	cpu_v6_do_idle()
 *
 *	Idle the processor (eg, wait for interrupt).
 *
 *	IRQs are already disabled.
 */
ENTRY(cpu_v6_do_idle)
	mov	r1, #0
	mcr	p15, 0, r1, c7, c10, 4		@ DWB - WFI may enter a low-power mode
	mcr	p15, 0, r1, c7, c0, 4		@ wait for interrupt
	mov	pc, lr

ENTRY(cpu_v6_dcache_clean_area)
#ifndef TLB_CAN_READ_FROM_L1_CACHE
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #D_CACHE_LINE_SIZE
	subs	r1, r1, #D_CACHE_LINE_SIZE
	bhi	1b
#endif
	mov	pc, lr

/*
 *	cpu_arm926_switch_mm(pgd_phys, tsk)
 *
 *	Set the translation table base pointer to be pgd_phys
 *
 *	- pgd_phys - physical address of new TTB
 *
 *	It is assumed that:
 *	- we are not using split page tables
 */
ENTRY(cpu_v6_switch_mm)
#ifdef CONFIG_MMU
	mov	r2, #0
	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
	ALT_SMP(orr	r0, r0, #TTB_FLAGS_SMP)
	ALT_UP(orr	r0, r0, #TTB_FLAGS_UP)
	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
	mcr	p15, 0, r2, c7, c10, 4		@ drain write buffer
	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
	mcr	p15, 0, r1, c13, c0, 1		@ set context ID
#endif
	mov	pc, lr

/*
 *	cpu_v6_set_pte_ext(ptep, pte, ext)
 *
 *	Set a level 2 translation table entry.
 *
 *	- ptep  - pointer to level 2 translation table entry
 *		  (hardware version is stored at -1024 bytes)
 *	- pte   - PTE value to store
 *	- ext	- value for extended PTE bits
 */
	armv6_mt_table cpu_v6

ENTRY(cpu_v6_set_pte_ext)
#ifdef CONFIG_MMU
	armv6_set_pte_ext cpu_v6
#endif
	mov	pc, lr

/* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */
.globl	cpu_v6_suspend_size
.equ	cpu_v6_suspend_size, 4 * 8
#ifdef CONFIG_PM_SLEEP
ENTRY(cpu_v6_do_suspend)
	stmfd	sp!, {r4 - r11, lr}
	mrc	p15, 0, r4, c13, c0, 0	@ FCSE/PID
	mrc	p15, 0, r5, c13, c0, 1	@ Context ID
	mrc	p15, 0, r6, c3, c0, 0	@ Domain ID
	mrc	p15, 0, r7, c2, c0, 0	@ Translation table base 0
	mrc	p15, 0, r8, c2, c0, 1	@ Translation table base 1
	mrc	p15, 0, r9, c1, c0, 1	@ auxiliary control register
	mrc	p15, 0, r10, c1, c0, 2	@ co-processor access control
	mrc	p15, 0, r11, c1, c0, 0	@ control register
	stmia	r0, {r4 - r11}
	ldmfd	sp!, {r4- r11, pc}
ENDPROC(cpu_v6_do_suspend)

ENTRY(cpu_v6_do_resume)
	mov	ip, #0
	mcr	p15, 0, ip, c7, c14, 0	@ clean+invalidate D cache
	mcr	p15, 0, ip, c7, c5, 0	@ invalidate I cache
	mcr	p15, 0, ip, c7, c15, 0	@ clean+invalidate cache
	mcr	p15, 0, ip, c7, c10, 4	@ drain write buffer
	ldmia	r0, {r4 - r11}
	mcr	p15, 0, r4, c13, c0, 0	@ FCSE/PID
	mcr	p15, 0, r5, c13, c0, 1	@ Context ID
	mcr	p15, 0, r6, c3, c0, 0	@ Domain ID
	mcr	p15, 0, r7, c2, c0, 0	@ Translation table base 0
	mcr	p15, 0, r8, c2, c0, 1	@ Translation table base 1
	mcr	p15, 0, r9, c1, c0, 1	@ auxiliary control register
	mcr	p15, 0, r10, c1, c0, 2	@ co-processor access control
	mcr	p15, 0, ip, c2, c0, 2	@ TTB control register
	mcr	p15, 0, ip, c7, c5, 4	@ ISB
	mov	r0, r11			@ control register
	mov	r2, r7, lsr #14		@ get TTB0 base
	mov	r2, r2, lsl #14
	ldr	r3, cpu_resume_l1_flags
	b	cpu_resume_mmu
ENDPROC(cpu_v6_do_resume)
cpu_resume_l1_flags:
	ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_SMP)
	ALT_UP(.long  PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_UP)
#else
#define cpu_v6_do_suspend 0
#define cpu_v6_do_resume 0
#endif


	.type	cpu_v6_name, #object
cpu_v6_name:
	.asciz	"ARMv6-compatible processor"
	.size	cpu_v6_name, . - cpu_v6_name

	.align

	__CPUINIT

/*
 *	__v6_setup
 *
 *	Initialise TLB, Caches, and MMU state ready to switch the MMU
 *	on.  Return in r0 the new CP15 C1 control register setting.
 *
 *	We automatically detect if we have a Harvard cache, and use the
 *	Harvard cache control instructions insead of the unified cache
 *	control instructions.
 *
 *	This should be able to cover all ARMv6 cores.
 *
 *	It is assumed that:
 *	- cache type register is implemented
 */
__v6_setup:
#ifdef CONFIG_SMP
	ALT_SMP(mrc	p15, 0, r0, c1, c0, 1)	@ Enable SMP/nAMP mode
	ALT_UP(nop)
	orr	r0, r0, #0x20
	ALT_SMP(mcr	p15, 0, r0, c1, c0, 1)
	ALT_UP(nop)
#endif

	mov	r0, #0
	mcr	p15, 0, r0, c7, c14, 0		@ clean+invalidate D cache
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, r0, c7, c15, 0		@ clean+invalidate cache
	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer
#ifdef CONFIG_MMU
	mcr	p15, 0, r0, c8, c7, 0		@ invalidate I + D TLBs
	mcr	p15, 0, r0, c2, c0, 2		@ TTB control register
	ALT_SMP(orr	r4, r4, #TTB_FLAGS_SMP)
	ALT_UP(orr	r4, r4, #TTB_FLAGS_UP)
	ALT_SMP(orr	r8, r8, #TTB_FLAGS_SMP)
	ALT_UP(orr	r8, r8, #TTB_FLAGS_UP)
	mcr	p15, 0, r8, c2, c0, 1		@ load TTB1
#endif /* CONFIG_MMU */
	adr	r5, v6_crval
	ldmia	r5, {r5, r6}
#ifdef CONFIG_CPU_ENDIAN_BE8
	orr	r6, r6, #1 << 25		@ big-endian page tables
#endif
	mrc	p15, 0, r0, c1, c0, 0		@ read control register
	bic	r0, r0, r5			@ clear bits them
	orr	r0, r0, r6			@ set them
	mov	pc, lr				@ return to head.S:__ret

	/*
	 *         V X F   I D LR
	 * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
	 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
	 *         0 110       0011 1.00 .111 1101 < we want
	 */
	.type	v6_crval, #object
v6_crval:
	crval	clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c

	__INITDATA

	.type	v6_processor_functions, #object
ENTRY(v6_processor_functions)
	.word	v6_early_abort
	.word	v6_pabort
	.word	cpu_v6_proc_init
	.word	cpu_v6_proc_fin
	.word	cpu_v6_reset
	.word	cpu_v6_do_idle
	.word	cpu_v6_dcache_clean_area
	.word	cpu_v6_switch_mm
	.word	cpu_v6_set_pte_ext
	.word	cpu_v6_suspend_size
	.word	cpu_v6_do_suspend
	.word	cpu_v6_do_resume
	.size	v6_processor_functions, . - v6_processor_functions

	.section ".rodata"

	.type	cpu_arch_name, #object
cpu_arch_name:
	.asciz	"armv6"
	.size	cpu_arch_name, . - cpu_arch_name

	.type	cpu_elf_name, #object
cpu_elf_name:
	.asciz	"v6"
	.size	cpu_elf_name, . - cpu_elf_name
	.align

	.section ".proc.info.init", #alloc, #execinstr

	/*
	 * Match any ARMv6 processor core.
	 */
	.type	__v6_proc_info, #object
__v6_proc_info:
	.long	0x0007b000
	.long	0x0007f000
	ALT_SMP(.long \
		PMD_TYPE_SECT | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ | \
		PMD_FLAGS_SMP)
	ALT_UP(.long \
		PMD_TYPE_SECT | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ | \
		PMD_FLAGS_UP)
	.long   PMD_TYPE_SECT | \
		PMD_SECT_XN | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	b	__v6_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	/* See also feat_v6_fixup() for HWCAP_TLS */
	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA|HWCAP_TLS
	.long	cpu_v6_name
	.long	v6_processor_functions
	.long	v6wbi_tlb_fns
	.long	v6_user_fns
	.long	v6_cache_fns
	.size	__v6_proc_info, . - __v6_proc_info
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mm/proc-v6.S
	3	*
	4	* Copyright (C) 2001 Deep Blue Solutions Ltd.
d090ddda	5	* Modified by Catalin Marinas for noMMU support
1da177e4 LT	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This is the "shell" of the ARMv6 processor support.
	12	*/
991da17e	13	#include <linux/init.h>
1da177e4 LT	14	#include <linux/linkage.h>
1da177e4 LT	15	#include <asm/assembler.h>
e6ae744d	16	#include <asm/asm-offsets.h>
5ec9407d	17	#include <asm/hwcap.h>
74945c86	18	#include <asm/pgtable-hwdef.h>
1da177e4 LT	19	#include <asm/pgtable.h>
	20
	21	#include "proc-macros.S"
	22
	23	#define D_CACHE_LINE_SIZE 32
	24
3747b36e RK	25	#define TTB_C (1 << 0)
	26	#define TTB_S (1 << 1)
	27	#define TTB_IMP (1 << 2)
	28	#define TTB_RGN_NC (0 << 3)
	29	#define TTB_RGN_WBWA (1 << 3)
	30	#define TTB_RGN_WT (2 << 3)
	31	#define TTB_RGN_WB (3 << 3)
	32
f00ec48f RK	33	#define TTB_FLAGS_UP TTB_RGN_WBWA
	34	#define PMD_FLAGS_UP PMD_SECT_WB
	35	#define TTB_FLAGS_SMP TTB_RGN_WBWA\|TTB_S
	36	#define PMD_FLAGS_SMP PMD_SECT_WBWA\|PMD_SECT_S
f2131d34	37
1da177e4 LT	38	ENTRY(cpu_v6_proc_init)
	39	mov pc, lr
	40
	41	ENTRY(cpu_v6_proc_fin)
67c5587a TL	42	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	43	bic r0, r0, #0x1000 @ ...i............
	44	bic r0, r0, #0x0006 @ .............ca.
	45	mcr p15, 0, r0, c1, c0, 0 @ disable caches
9ca03a21	46	mov pc, lr
1da177e4 LT	47
	48	/*
	49	* cpu_v6_reset(loc)
	50	*
	51	* Perform a soft reset of the system. Put the CPU into the
	52	* same state as it would be if it had been reset, and branch
	53	* to what would be the reset vector.
	54	*
	55	* - loc - location to jump to for soft reset
1da177e4 LT	56	*/
	57	.align 5
	58	ENTRY(cpu_v6_reset)
	59	mov pc, r0
	60
	61	/*
	62	* cpu_v6_do_idle()
	63	*
	64	* Idle the processor (eg, wait for interrupt).
	65	*
	66	* IRQs are already disabled.
	67	*/
	68	ENTRY(cpu_v6_do_idle)
8553cb67 CM	69	mov r1, #0
8553cb67 CM	70	mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
1da177e4 LT	71	mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
	72	mov pc, lr
	73
	74	ENTRY(cpu_v6_dcache_clean_area)
	75	#ifndef TLB_CAN_READ_FROM_L1_CACHE
	76	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	77	add r0, r0, #D_CACHE_LINE_SIZE
	78	subs r1, r1, #D_CACHE_LINE_SIZE
	79	bhi 1b
	80	#endif
	81	mov pc, lr
	82
	83	/*
	84	* cpu_arm926_switch_mm(pgd_phys, tsk)
	85	*
	86	* Set the translation table base pointer to be pgd_phys
	87	*
	88	* - pgd_phys - physical address of new TTB
	89	*
	90	* It is assumed that:
	91	* - we are not using split page tables
	92	*/
	93	ENTRY(cpu_v6_switch_mm)
d090ddda	94	#ifdef CONFIG_MMU
1da177e4 LT	95	mov r2, #0
1da177e4 LT	96	ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
f00ec48f RK	97	ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
f00ec48f RK	98	ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
d93742f5	99	mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
1da177e4 LT	100	mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
	101	mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
	102	mcr p15, 0, r1, c13, c0, 1 @ set context ID
d090ddda	103	#endif
1da177e4 LT	104	mov pc, lr
1da177e4 LT	105
1da177e4	106	/*
ad1ae2fe	107	* cpu_v6_set_pte_ext(ptep, pte, ext)
1da177e4 LT	108	*
	109	* Set a level 2 translation table entry.
	110	*
	111	* - ptep - pointer to level 2 translation table entry
	112	* (hardware version is stored at -1024 bytes)
	113	* - pte - PTE value to store
ad1ae2fe	114	* - ext - value for extended PTE bits
1da177e4	115	*/
639b0ae7 RK	116	armv6_mt_table cpu_v6
639b0ae7 RK	117
ad1ae2fe	118	ENTRY(cpu_v6_set_pte_ext)
d090ddda	119	#ifdef CONFIG_MMU
639b0ae7	120	armv6_set_pte_ext cpu_v6
d090ddda	121	#endif
1da177e4 LT	122	mov pc, lr
1da177e4 LT	123
f6b0fa02 RK	124	/* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */
	125	.globl cpu_v6_suspend_size
	126	.equ cpu_v6_suspend_size, 4 * 8
29ea23ff	127	#ifdef CONFIG_PM_SLEEP
f6b0fa02 RK	128	ENTRY(cpu_v6_do_suspend)
	129	stmfd sp!, {r4 - r11, lr}
	130	mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
	131	mrc p15, 0, r5, c13, c0, 1 @ Context ID
	132	mrc p15, 0, r6, c3, c0, 0 @ Domain ID
	133	mrc p15, 0, r7, c2, c0, 0 @ Translation table base 0
	134	mrc p15, 0, r8, c2, c0, 1 @ Translation table base 1
25985edc	135	mrc p15, 0, r9, c1, c0, 1 @ auxiliary control register
f6b0fa02 RK	136	mrc p15, 0, r10, c1, c0, 2 @ co-processor access control
	137	mrc p15, 0, r11, c1, c0, 0 @ control register
	138	stmia r0, {r4 - r11}
	139	ldmfd sp!, {r4- r11, pc}
	140	ENDPROC(cpu_v6_do_suspend)
	141
	142	ENTRY(cpu_v6_do_resume)
	143	mov ip, #0
	144	mcr p15, 0, ip, c7, c14, 0 @ clean+invalidate D cache
	145	mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
	146	mcr p15, 0, ip, c7, c15, 0 @ clean+invalidate cache
	147	mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
	148	ldmia r0, {r4 - r11}
	149	mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
	150	mcr p15, 0, r5, c13, c0, 1 @ Context ID
	151	mcr p15, 0, r6, c3, c0, 0 @ Domain ID
	152	mcr p15, 0, r7, c2, c0, 0 @ Translation table base 0
	153	mcr p15, 0, r8, c2, c0, 1 @ Translation table base 1
25985edc	154	mcr p15, 0, r9, c1, c0, 1 @ auxiliary control register
f6b0fa02 RK	155	mcr p15, 0, r10, c1, c0, 2 @ co-processor access control
	156	mcr p15, 0, ip, c2, c0, 2 @ TTB control register
	157	mcr p15, 0, ip, c7, c5, 4 @ ISB
	158	mov r0, r11 @ control register
	159	mov r2, r7, lsr #14 @ get TTB0 base
	160	mov r2, r2, lsl #14
	161	ldr r3, cpu_resume_l1_flags
	162	b cpu_resume_mmu
	163	ENDPROC(cpu_v6_do_resume)
	164	cpu_resume_l1_flags:
	165	ALT_SMP(.long PMD_TYPE_SECT \| PMD_SECT_AP_WRITE \| PMD_FLAGS_SMP)
	166	ALT_UP(.long PMD_TYPE_SECT \| PMD_SECT_AP_WRITE \| PMD_FLAGS_UP)
	167	#else
	168	#define cpu_v6_do_suspend 0
	169	#define cpu_v6_do_resume 0
	170	#endif
1da177e4 LT	171
1da177e4 LT	172
edabd38e	173	.type cpu_v6_name, #object
1da177e4	174	cpu_v6_name:
94b1e96d	175	.asciz "ARMv6-compatible processor"
edabd38e SB	176	.size cpu_v6_name, . - cpu_v6_name
edabd38e SB	177
1da177e4 LT	178	.align
1da177e4 LT	179
5085f3ff	180	__CPUINIT
1da177e4 LT	181
	182	/*
	183	* __v6_setup
	184	*
	185	* Initialise TLB, Caches, and MMU state ready to switch the MMU
	186	* on. Return in r0 the new CP15 C1 control register setting.
	187	*
	188	* We automatically detect if we have a Harvard cache, and use the
	189	* Harvard cache control instructions insead of the unified cache
	190	* control instructions.
	191	*
	192	* This should be able to cover all ARMv6 cores.
	193	*
	194	* It is assumed that:
	195	* - cache type register is implemented
	196	*/
	197	__v6_setup:
862184fe	198	#ifdef CONFIG_SMP
f00ec48f RK	199	ALT_SMP(mrc p15, 0, r0, c1, c0, 1) @ Enable SMP/nAMP mode
f00ec48f RK	200	ALT_UP(nop)
862184fe	201	orr r0, r0, #0x20
f00ec48f RK	202	ALT_SMP(mcr p15, 0, r0, c1, c0, 1)
f00ec48f RK	203	ALT_UP(nop)
862184fe RK	204	#endif
862184fe RK	205
1da177e4 LT	206	mov r0, #0
	207	mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
	208	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
	209	mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
	210	mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
d090ddda	211	#ifdef CONFIG_MMU
1da177e4 LT	212	mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
1da177e4 LT	213	mcr p15, 0, r0, c2, c0, 2 @ TTB control register
f00ec48f RK	214	ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP)
f00ec48f RK	215	ALT_UP(orr r4, r4, #TTB_FLAGS_UP)
d427958a CM	216	ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP)
	217	ALT_UP(orr r8, r8, #TTB_FLAGS_UP)
	218	mcr p15, 0, r8, c2, c0, 1 @ load TTB1
d090ddda	219	#endif /* CONFIG_MMU */
22b19086 RK	220	adr r5, v6_crval
22b19086 RK	221	ldmia r5, {r5, r6}
26584853 CM	222	#ifdef CONFIG_CPU_ENDIAN_BE8
	223	orr r6, r6, #1 << 25 @ big-endian page tables
	224	#endif
1da177e4	225	mrc p15, 0, r0, c1, c0, 0 @ read control register
1da177e4	226	bic r0, r0, r5 @ clear bits them
22b19086	227	orr r0, r0, r6 @ set them
1da177e4 LT	228	mov pc, lr @ return to head.S:__ret
	229
	230	/*
	231	* V X F I D LR
	232	* .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
	233	* rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
	234	* 0 110 0011 1.00 .111 1101 < we want
	235	*/
22b19086 RK	236	.type v6_crval, #object
	237	v6_crval:
	238	crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
1da177e4	239
5085f3ff RK	240	__INITDATA
5085f3ff RK	241
1da177e4 LT	242	.type v6_processor_functions, #object
	243	ENTRY(v6_processor_functions)
	244	.word v6_early_abort
4fb28474	245	.word v6_pabort
1da177e4 LT	246	.word cpu_v6_proc_init
	247	.word cpu_v6_proc_fin
	248	.word cpu_v6_reset
	249	.word cpu_v6_do_idle
	250	.word cpu_v6_dcache_clean_area
	251	.word cpu_v6_switch_mm
ad1ae2fe	252	.word cpu_v6_set_pte_ext
f6b0fa02 RK	253	.word cpu_v6_suspend_size
	254	.word cpu_v6_do_suspend
	255	.word cpu_v6_do_resume
1da177e4 LT	256	.size v6_processor_functions, . - v6_processor_functions
1da177e4 LT	257
5085f3ff RK	258	.section ".rodata"
5085f3ff RK	259
1da177e4 LT	260	.type cpu_arch_name, #object
	261	cpu_arch_name:
	262	.asciz "armv6"
	263	.size cpu_arch_name, . - cpu_arch_name
	264
	265	.type cpu_elf_name, #object
	266	cpu_elf_name:
	267	.asciz "v6"
	268	.size cpu_elf_name, . - cpu_elf_name
	269	.align
	270
02b7dd12	271	.section ".proc.info.init", #alloc, #execinstr
1da177e4 LT	272
	273	/*
	274	* Match any ARMv6 processor core.
	275	*/
	276	.type __v6_proc_info, #object
	277	__v6_proc_info:
	278	.long 0x0007b000
	279	.long 0x0007f000
f00ec48f RK	280	ALT_SMP(.long \
	281	PMD_TYPE_SECT \| \
	282	PMD_SECT_AP_WRITE \| \
	283	PMD_SECT_AP_READ \| \
	284	PMD_FLAGS_SMP)
	285	ALT_UP(.long \
	286	PMD_TYPE_SECT \| \
1da177e4	287	PMD_SECT_AP_WRITE \| \
4b46d641	288	PMD_SECT_AP_READ \| \
f00ec48f	289	PMD_FLAGS_UP)
8799ee9f RK	290	.long PMD_TYPE_SECT \| \
	291	PMD_SECT_XN \| \
	292	PMD_SECT_AP_WRITE \| \
	293	PMD_SECT_AP_READ
1da177e4 LT	294	b __v6_setup
	295	.long cpu_arch_name
	296	.long cpu_elf_name
f159f4ed TL	297	/* See also feat_v6_fixup() for HWCAP_TLS */
f159f4ed TL	298	.long HWCAP_SWP\|HWCAP_HALF\|HWCAP_THUMB\|HWCAP_FAST_MULT\|HWCAP_EDSP\|HWCAP_JAVA\|HWCAP_TLS
1da177e4 LT	299	.long cpu_v6_name
	300	.long v6_processor_functions
	301	.long v6wbi_tlb_fns
	302	.long v6_user_fns
	303	.long v6_cache_fns
	304	.size __v6_proc_info, . - __v6_proc_info