[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mm / proc-arm740.S

/*
 *  linux/arch/arm/mm/arm740.S: utility functions for ARM740
 *
 *  Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>
#include <asm/ptrace.h>

	.text
/*
 * cpu_arm740_proc_init()
 * cpu_arm740_do_idle()
 * cpu_arm740_dcache_clean_area()
 * cpu_arm740_switch_mm()
 *
 * These are not required.
 */
ENTRY(cpu_arm740_proc_init)
ENTRY(cpu_arm740_do_idle)
ENTRY(cpu_arm740_dcache_clean_area)
ENTRY(cpu_arm740_switch_mm)
	mov	pc, lr

/*
 * cpu_arm740_proc_fin()
 */
ENTRY(cpu_arm740_proc_fin)
	mrc	p15, 0, r0, c1, c0, 0
	bic	r0, r0, #0x3f000000		@ bank/f/lock/s
	bic	r0, r0, #0x0000000c		@ w-buffer/cache
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	mov	pc, lr

/*
 * cpu_arm740_reset(loc)
 * Params  : r0 = address to jump to
 * Notes   : This sets up everything for a reset
 */
ENTRY(cpu_arm740_reset)
	mov	ip, #0
	mcr	p15, 0, ip, c7, c0, 0		@ invalidate cache
	mrc	p15, 0, ip, c1, c0, 0		@ get ctrl register
	bic	ip, ip, #0x0000000c		@ ............wc..
	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
	mov	pc, r0

	__CPUINIT

	.type	__arm740_setup, #function
__arm740_setup:
	mov	r0, #0
	mcr	p15, 0, r0, c7, c0, 0		@ invalidate caches

	mcr	p15, 0, r0, c6, c3		@ disable area 3~7
	mcr	p15, 0, r0, c6, c4
	mcr	p15, 0, r0, c6, c5
	mcr	p15, 0, r0, c6, c6
	mcr	p15, 0, r0, c6, c7

	mov	r0, #0x0000003F			@ base = 0, size = 4GB
	mcr	p15, 0, r0, c6,	c0		@ set area 0, default

	ldr	r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
	ldr	r1, =(CONFIG_DRAM_SIZE >> 12)	@ size of RAM (must be >= 4KB)
	mov	r2, #10				@ 11 is the minimum (4KB)
1:	add	r2, r2, #1			@ area size *= 2
	mov	r1, r1, lsr #1
	bne	1b				@ count not zero r-shift
	orr	r0, r0, r2, lsl #1		@ the area register value
	orr	r0, r0, #1			@ set enable bit
	mcr	p15, 0, r0, c6,	c1		@ set area 1, RAM

	ldr	r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
	ldr	r1, =(CONFIG_FLASH_SIZE >> 12)	@ size of FLASH (must be >= 4KB)
	mov	r2, #10				@ 11 is the minimum (4KB)
1:	add	r2, r2, #1			@ area size *= 2
	mov	r1, r1, lsr #1
	bne	1b				@ count not zero r-shift
	orr	r0, r0, r2, lsl #1		@ the area register value
	orr	r0, r0, #1			@ set enable bit
	mcr	p15, 0, r0, c6,	c2		@ set area 2, ROM/FLASH

	mov	r0, #0x06
	mcr	p15, 0, r0, c2, c0		@ Region 1&2 cacheable
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mov	r0, #0x00			@ disable whole write buffer
#else
	mov	r0, #0x02			@ Region 1 write bufferred
#endif
	mcr	p15, 0, r0, c3, c0

	mov	r0, #0x10000
	sub	r0, r0, #1			@ r0 = 0xffff
	mcr	p15, 0, r0, c5, c0		@ all read/write access

	mrc	p15, 0, r0, c1, c0		@ get control register
	bic	r0, r0, #0x3F000000		@ set to standard caching mode
						@ need some benchmark
	orr	r0, r0, #0x0000000d		@ MPU/Cache/WB

	mov	pc, lr

	.size	__arm740_setup, . - __arm740_setup

	__INITDATA

/*
 * Purpose : Function pointers used to access above functions - all calls
 *	     come through these
 */
	.type	arm740_processor_functions, #object
ENTRY(arm740_processor_functions)
	.word	v4t_late_abort
	.word	legacy_pabort
	.word	cpu_arm740_proc_init
	.word	cpu_arm740_proc_fin
	.word	cpu_arm740_reset
	.word   cpu_arm740_do_idle
	.word	cpu_arm740_dcache_clean_area
	.word	cpu_arm740_switch_mm
	.word	0			@ cpu_*_set_pte
	.word	0
	.word	0
	.word	0
	.size	arm740_processor_functions, . - arm740_processor_functions

	.section ".rodata"

	.type	cpu_arch_name, #object
cpu_arch_name:
	.asciz	"armv4"
	.size	cpu_arch_name, . - cpu_arch_name

	.type	cpu_elf_name, #object
cpu_elf_name:
	.asciz	"v4"
	.size	cpu_elf_name, . - cpu_elf_name

	.type	cpu_arm740_name, #object
cpu_arm740_name:
	.ascii	"ARM740T"
	.size	cpu_arm740_name, . - cpu_arm740_name

	.align

	.section ".proc.info.init", #alloc, #execinstr
	.type	__arm740_proc_info,#object
__arm740_proc_info:
	.long	0x41807400
	.long	0xfffffff0
	.long	0
	b	__arm740_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT
	.long	cpu_arm740_name
	.long	arm740_processor_functions
	.long	0
	.long	0
	.long	v3_cache_fns			@ cache model
	.size	__arm740_proc_info, . - __arm740_proc_info
Commit	Line	Data
b731c311 HC	1	/*
	2	* linux/arch/arm/mm/arm740.S: utility functions for ARM740
	3	*
	4	* Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	*/
	11	#include <linux/linkage.h>
	12	#include <linux/init.h>
	13	#include <asm/assembler.h>
	14	#include <asm/asm-offsets.h>
5ec9407d	15	#include <asm/hwcap.h>
b731c311 HC	16	#include <asm/pgtable-hwdef.h>
b731c311 HC	17	#include <asm/pgtable.h>
b731c311 HC	18	#include <asm/ptrace.h>
	19
	20	.text
	21	/*
	22	* cpu_arm740_proc_init()
	23	* cpu_arm740_do_idle()
	24	* cpu_arm740_dcache_clean_area()
	25	* cpu_arm740_switch_mm()
	26	*
	27	* These are not required.
	28	*/
	29	ENTRY(cpu_arm740_proc_init)
	30	ENTRY(cpu_arm740_do_idle)
	31	ENTRY(cpu_arm740_dcache_clean_area)
	32	ENTRY(cpu_arm740_switch_mm)
	33	mov pc, lr
	34
	35	/*
	36	* cpu_arm740_proc_fin()
	37	*/
	38	ENTRY(cpu_arm740_proc_fin)
b731c311 HC	39	mrc p15, 0, r0, c1, c0, 0
	40	bic r0, r0, #0x3f000000 @ bank/f/lock/s
	41	bic r0, r0, #0x0000000c @ w-buffer/cache
	42	mcr p15, 0, r0, c1, c0, 0 @ disable caches
9ca03a21	43	mov pc, lr
b731c311 HC	44
	45	/*
	46	* cpu_arm740_reset(loc)
	47	* Params : r0 = address to jump to
	48	* Notes : This sets up everything for a reset
	49	*/
	50	ENTRY(cpu_arm740_reset)
	51	mov ip, #0
	52	mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
	53	mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
	54	bic ip, ip, #0x0000000c @ ............wc..
	55	mcr p15, 0, ip, c1, c0, 0 @ ctrl register
	56	mov pc, r0
	57
5085f3ff	58	__CPUINIT
b731c311 HC	59
	60	.type __arm740_setup, #function
	61	__arm740_setup:
	62	mov r0, #0
	63	mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
	64
	65	mcr p15, 0, r0, c6, c3 @ disable area 3~7
	66	mcr p15, 0, r0, c6, c4
	67	mcr p15, 0, r0, c6, c5
	68	mcr p15, 0, r0, c6, c6
	69	mcr p15, 0, r0, c6, c7
	70
	71	mov r0, #0x0000003F @ base = 0, size = 4GB
	72	mcr p15, 0, r0, c6, c0 @ set area 0, default
	73
	74	ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
	75	ldr r1, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB)
	76	mov r2, #10 @ 11 is the minimum (4KB)
	77	1: add r2, r2, #1 @ area size *= 2
	78	mov r1, r1, lsr #1
	79	bne 1b @ count not zero r-shift
	80	orr r0, r0, r2, lsl #1 @ the area register value
	81	orr r0, r0, #1 @ set enable bit
	82	mcr p15, 0, r0, c6, c1 @ set area 1, RAM
	83
	84	ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
	85	ldr r1, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB)
	86	mov r2, #10 @ 11 is the minimum (4KB)
	87	1: add r2, r2, #1 @ area size *= 2
	88	mov r1, r1, lsr #1
	89	bne 1b @ count not zero r-shift
	90	orr r0, r0, r2, lsl #1 @ the area register value
	91	orr r0, r0, #1 @ set enable bit
	92	mcr p15, 0, r0, c6, c2 @ set area 2, ROM/FLASH
	93
	94	mov r0, #0x06
	95	mcr p15, 0, r0, c2, c0 @ Region 1&2 cacheable
	96	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	97	mov r0, #0x00 @ disable whole write buffer
	98	#else
	99	mov r0, #0x02 @ Region 1 write bufferred
	100	#endif
	101	mcr p15, 0, r0, c3, c0
	102
	103	mov r0, #0x10000
	104	sub r0, r0, #1 @ r0 = 0xffff
	105	mcr p15, 0, r0, c5, c0 @ all read/write access
	106
	107	mrc p15, 0, r0, c1, c0 @ get control register
	108	bic r0, r0, #0x3F000000 @ set to standard caching mode
	109	@ need some benchmark
	110	orr r0, r0, #0x0000000d @ MPU/Cache/WB
	111
	112	mov pc, lr
	113
	114	.size __arm740_setup, . - __arm740_setup
	115
	116	__INITDATA
	117
	118	/*
	119	* Purpose : Function pointers used to access above functions - all calls
	120	* come through these
	121	*/
	122	.type arm740_processor_functions, #object
123	ENTRY(arm740_processor_functions)
124	.word v4t_late_abort
4fb28474	125	.word legacy_pabort
b731c311 HC	126	.word cpu_arm740_proc_init
	127	.word cpu_arm740_proc_fin
	128	.word cpu_arm740_reset
	129	.word cpu_arm740_do_idle
	130	.word cpu_arm740_dcache_clean_area
	131	.word cpu_arm740_switch_mm
	132	.word 0 @ cpu_*_set_pte
f6b0fa02 RK	133	.word 0
	134	.word 0
	135	.word 0
b731c311 HC	136	.size arm740_processor_functions, . - arm740_processor_functions
	137
	138	.section ".rodata"
	139
	140	.type cpu_arch_name, #object
	141	cpu_arch_name:
	142	.asciz "armv4"
	143	.size cpu_arch_name, . - cpu_arch_name
	144
	145	.type cpu_elf_name, #object
	146	cpu_elf_name:
	147	.asciz "v4"
	148	.size cpu_elf_name, . - cpu_elf_name
	149
	150	.type cpu_arm740_name, #object
	151	cpu_arm740_name:
	152	.ascii "ARM740T"
	153	.size cpu_arm740_name, . - cpu_arm740_name
	154
	155	.align
	156
	157	.section ".proc.info.init", #alloc, #execinstr
	158	.type __arm740_proc_info,#object
	159	__arm740_proc_info:
	160	.long 0x41807400
	161	.long 0xfffffff0
	162	.long 0
	163	b __arm740_setup
	164	.long cpu_arch_name
	165	.long cpu_elf_name
	166	.long HWCAP_SWP \| HWCAP_HALF \| HWCAP_26BIT
	167	.long cpu_arm740_name
	168	.long arm740_processor_functions
	169	.long 0
	170	.long 0
	171	.long v3_cache_fns @ cache model
	172	.size __arm740_proc_info, . - __arm740_proc_info
	173
	174