[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mm / fault-armv.c

/*
 *  linux/arch/arm/mm/fault-armv.c
 *
 *  Copyright (C) 1995  Linus Torvalds
 *  Modifications for ARM processor (c) 1995-2002 Russell King
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/bitops.h>
#include <linux/vmalloc.h>
#include <linux/init.h>
#include <linux/pagemap.h>

#include <asm/cacheflush.h>
#include <asm/pgtable.h>
#include <asm/tlbflush.h>

static unsigned long shared_pte_mask = L_PTE_CACHEABLE;

/*
 * We take the easy way out of this problem - we make the
 * PTE uncacheable.  However, we leave the write buffer on.
 */
static int adjust_pte(struct vm_area_struct *vma, unsigned long address)
{
	pgd_t *pgd;
	pmd_t *pmd;
	pte_t *pte, entry;
	int ret = 0;

	pgd = pgd_offset(vma->vm_mm, address);
	if (pgd_none(*pgd))
		goto no_pgd;
	if (pgd_bad(*pgd))
		goto bad_pgd;

	pmd = pmd_offset(pgd, address);
	if (pmd_none(*pmd))
		goto no_pmd;
	if (pmd_bad(*pmd))
		goto bad_pmd;

	pte = pte_offset_map(pmd, address);
	entry = *pte;

	/*
	 * If this page isn't present, or is already setup to
	 * fault (ie, is old), we can safely ignore any issues.
	 */
	if (pte_present(entry) && pte_val(entry) & shared_pte_mask) {
		flush_cache_page(vma, address, pte_pfn(entry));
		pte_val(entry) &= ~shared_pte_mask;
		set_pte(pte, entry);
		flush_tlb_page(vma, address);
		ret = 1;
	}
	pte_unmap(pte);
	return ret;

bad_pgd:
	pgd_ERROR(*pgd);
	pgd_clear(pgd);
no_pgd:
	return 0;

bad_pmd:
	pmd_ERROR(*pmd);
	pmd_clear(pmd);
no_pmd:
	return 0;
}

static void
make_coherent(struct address_space *mapping, struct vm_area_struct *vma, unsigned long addr, unsigned long pfn)
{
	struct mm_struct *mm = vma->vm_mm;
	struct vm_area_struct *mpnt;
	struct prio_tree_iter iter;
	unsigned long offset;
	pgoff_t pgoff;
	int aliases = 0;

	pgoff = vma->vm_pgoff + ((addr - vma->vm_start) >> PAGE_SHIFT);

	/*
	 * If we have any shared mappings that are in the same mm
	 * space, then we need to handle them specially to maintain
	 * cache coherency.
	 */
	flush_dcache_mmap_lock(mapping);
	vma_prio_tree_foreach(mpnt, &iter, &mapping->i_mmap, pgoff, pgoff) {
		/*
		 * If this VMA is not in our MM, we can ignore it.
		 * Note that we intentionally mask out the VMA
		 * that we are fixing up.
		 */
		if (mpnt->vm_mm != mm || mpnt == vma)
			continue;
		if (!(mpnt->vm_flags & VM_MAYSHARE))
			continue;
		offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
		aliases += adjust_pte(mpnt, mpnt->vm_start + offset);
	}
	flush_dcache_mmap_unlock(mapping);
	if (aliases)
		adjust_pte(vma, addr);
	else
		flush_cache_page(vma, addr, pfn);
}

void __flush_dcache_page(struct address_space *mapping, struct page *page);

/*
 * Take care of architecture specific things when placing a new PTE into
 * a page table, or changing an existing PTE.  Basically, there are two
 * things that we need to take care of:
 *
 *  1. If PG_dcache_dirty is set for the page, we need to ensure
 *     that any cache entries for the kernels virtual memory
 *     range are written back to the page.
 *  2. If we have multiple shared mappings of the same space in
 *     an object, we need to deal with the cache aliasing issues.
 *
 * Note that the page_table_lock will be held.
 */
void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
{
	unsigned long pfn = pte_pfn(pte);
	struct address_space *mapping;
	struct page *page;

	if (!pfn_valid(pfn))
		return;

	page = pfn_to_page(pfn);
	mapping = page_mapping(page);
	if (mapping) {
		int dirty = test_and_clear_bit(PG_dcache_dirty, &page->flags);

		if (dirty)
			__flush_dcache_page(mapping, page);

		if (cache_is_vivt())
			make_coherent(mapping, vma, addr, pfn);
	}
}

/*
 * Check whether the write buffer has physical address aliasing
 * issues.  If it has, we need to avoid them for the case where
 * we have several shared mappings of the same object in user
 * space.
 */
static int __init check_writebuffer(unsigned long *p1, unsigned long *p2)
{
	register unsigned long zero = 0, one = 1, val;

	local_irq_disable();
	mb();
	*p1 = one;
	mb();
	*p2 = zero;
	mb();
	val = *p1;
	mb();
	local_irq_enable();
	return val != zero;
}

void __init check_writebuffer_bugs(void)
{
	struct page *page;
	const char *reason;
	unsigned long v = 1;

	printk(KERN_INFO "CPU: Testing write buffer coherency: ");

	page = alloc_page(GFP_KERNEL);
	if (page) {
		unsigned long *p1, *p2;
		pgprot_t prot = __pgprot(L_PTE_PRESENT|L_PTE_YOUNG|
					 L_PTE_DIRTY|L_PTE_WRITE|
					 L_PTE_BUFFERABLE);

		p1 = vmap(&page, 1, VM_IOREMAP, prot);
		p2 = vmap(&page, 1, VM_IOREMAP, prot);

		if (p1 && p2) {
			v = check_writebuffer(p1, p2);
			reason = "enabling work-around";
		} else {
			reason = "unable to map memory\n";
		}

		vunmap(p1);
		vunmap(p2);
		put_page(page);
	} else {
		reason = "unable to grab page\n";
	}

	if (v) {
		printk("failed, %s\n", reason);
		shared_pte_mask |= L_PTE_BUFFERABLE;
	} else {
		printk("ok\n");
	}
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mm/fault-armv.c
	3	*
	4	* Copyright (C) 1995 Linus Torvalds
	5	* Modifications for ARM processor (c) 1995-2002 Russell King
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11	#include <linux/module.h>
	12	#include <linux/sched.h>
	13	#include <linux/kernel.h>
	14	#include <linux/mm.h>
	15	#include <linux/bitops.h>
	16	#include <linux/vmalloc.h>
	17	#include <linux/init.h>
	18	#include <linux/pagemap.h>
	19
	20	#include <asm/cacheflush.h>
	21	#include <asm/pgtable.h>
	22	#include <asm/tlbflush.h>
	23
	24	static unsigned long shared_pte_mask = L_PTE_CACHEABLE;
	25
	26	/*
	27	* We take the easy way out of this problem - we make the
	28	* PTE uncacheable. However, we leave the write buffer on.
	29	*/
	30	static int adjust_pte(struct vm_area_struct *vma, unsigned long address)
	31	{
	32	pgd_t *pgd;
	33	pmd_t *pmd;
	34	pte_t *pte, entry;
	35	int ret = 0;
	36
	37	pgd = pgd_offset(vma->vm_mm, address);
	38	if (pgd_none(*pgd))
	39	goto no_pgd;
	40	if (pgd_bad(*pgd))
	41	goto bad_pgd;
	42
	43	pmd = pmd_offset(pgd, address);
	44	if (pmd_none(*pmd))
	45	goto no_pmd;
	46	if (pmd_bad(*pmd))
	47	goto bad_pmd;
	48
	49	pte = pte_offset_map(pmd, address);
	50	entry = *pte;
	51
	52	/*
	53	* If this page isn't present, or is already setup to
	54	* fault (ie, is old), we can safely ignore any issues.
	55	*/
	56	if (pte_present(entry) && pte_val(entry) & shared_pte_mask) {
	57	flush_cache_page(vma, address, pte_pfn(entry));
	58	pte_val(entry) &= ~shared_pte_mask;
	59	set_pte(pte, entry);
	60	flush_tlb_page(vma, address);
	61	ret = 1;
	62	}
	63	pte_unmap(pte);
	64	return ret;
65
66	bad_pgd:
67	pgd_ERROR(*pgd);
68	pgd_clear(pgd);
69	no_pgd:
70	return 0;
71
72	bad_pmd:
73	pmd_ERROR(*pmd);
74	pmd_clear(pmd);
75	no_pmd:
76	return 0;
77	}
78
79	static void
8830f04a	80	make_coherent(struct address_space mapping, struct vm_area_struct vma, unsigned long addr, unsigned long pfn)
1da177e4	81	{
1da177e4 LT	82	struct mm_struct *mm = vma->vm_mm;
	83	struct vm_area_struct *mpnt;
	84	struct prio_tree_iter iter;
	85	unsigned long offset;
	86	pgoff_t pgoff;
	87	int aliases = 0;
	88
1da177e4 LT	89	pgoff = vma->vm_pgoff + ((addr - vma->vm_start) >> PAGE_SHIFT);
	90
	91	/*
	92	* If we have any shared mappings that are in the same mm
	93	* space, then we need to handle them specially to maintain
	94	* cache coherency.
	95	*/
	96	flush_dcache_mmap_lock(mapping);
	97	vma_prio_tree_foreach(mpnt, &iter, &mapping->i_mmap, pgoff, pgoff) {
	98	/*
	99	* If this VMA is not in our MM, we can ignore it.
	100	* Note that we intentionally mask out the VMA
	101	* that we are fixing up.
	102	*/
	103	if (mpnt->vm_mm != mm \|\| mpnt == vma)
	104	continue;
	105	if (!(mpnt->vm_flags & VM_MAYSHARE))
	106	continue;
	107	offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
	108	aliases += adjust_pte(mpnt, mpnt->vm_start + offset);
	109	}
	110	flush_dcache_mmap_unlock(mapping);
	111	if (aliases)
	112	adjust_pte(vma, addr);
	113	else
8830f04a	114	flush_cache_page(vma, addr, pfn);
1da177e4 LT	115	}
1da177e4 LT	116
8830f04a RK	117	void __flush_dcache_page(struct address_space mapping, struct page page);
8830f04a RK	118
1da177e4 LT	119	/*
	120	* Take care of architecture specific things when placing a new PTE into
	121	* a page table, or changing an existing PTE. Basically, there are two
	122	* things that we need to take care of:
	123	*
	124	* 1. If PG_dcache_dirty is set for the page, we need to ensure
	125	* that any cache entries for the kernels virtual memory
	126	* range are written back to the page.
	127	* 2. If we have multiple shared mappings of the same space in
	128	* an object, we need to deal with the cache aliasing issues.
	129	*
	130	* Note that the page_table_lock will be held.
	131	*/
	132	void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
	133	{
	134	unsigned long pfn = pte_pfn(pte);
8830f04a	135	struct address_space *mapping;
1da177e4 LT	136	struct page *page;
	137
	138	if (!pfn_valid(pfn))
	139	return;
8830f04a	140
1da177e4	141	page = pfn_to_page(pfn);
8830f04a RK	142	mapping = page_mapping(page);
8830f04a RK	143	if (mapping) {
1da177e4 LT	144	int dirty = test_and_clear_bit(PG_dcache_dirty, &page->flags);
1da177e4 LT	145
8830f04a RK	146	if (dirty)
8830f04a RK	147	__flush_dcache_page(mapping, page);
1da177e4 LT	148
1da177e4 LT	149	if (cache_is_vivt())
8830f04a	150	make_coherent(mapping, vma, addr, pfn);
1da177e4 LT	151	}
	152	}
	153
	154	/*
	155	* Check whether the write buffer has physical address aliasing
	156	* issues. If it has, we need to avoid them for the case where
	157	* we have several shared mappings of the same object in user
	158	* space.
	159	*/
	160	static int __init check_writebuffer(unsigned long p1, unsigned long p2)
	161	{
	162	register unsigned long zero = 0, one = 1, val;
	163
	164	local_irq_disable();
	165	mb();
	166	*p1 = one;
	167	mb();
	168	*p2 = zero;
	169	mb();
	170	val = *p1;
	171	mb();
	172	local_irq_enable();
	173	return val != zero;
	174	}
	175
	176	void __init check_writebuffer_bugs(void)
	177	{
	178	struct page *page;
	179	const char *reason;
	180	unsigned long v = 1;
	181
	182	printk(KERN_INFO "CPU: Testing write buffer coherency: ");
	183
	184	page = alloc_page(GFP_KERNEL);
	185	if (page) {
	186	unsigned long p1, p2;
	187	pgprot_t prot = __pgprot(L_PTE_PRESENT\|L_PTE_YOUNG\|
	188	L_PTE_DIRTY\|L_PTE_WRITE\|
	189	L_PTE_BUFFERABLE);
	190
	191	p1 = vmap(&page, 1, VM_IOREMAP, prot);
	192	p2 = vmap(&page, 1, VM_IOREMAP, prot);
	193
	194	if (p1 && p2) {
	195	v = check_writebuffer(p1, p2);
	196	reason = "enabling work-around";
	197	} else {
	198	reason = "unable to map memory\n";
	199	}
	200
	201	vunmap(p1);
	202	vunmap(p2);
	203	put_page(page);
	204	} else {
	205	reason = "unable to grab page\n";
	206	}
	207
	208	if (v) {
	209	printk("failed, %s\n", reason);
	210	shared_pte_mask \|= L_PTE_BUFFERABLE;
	211	} else {
	212	printk("ok\n");
	213	}
	214	}