[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mm / abort-macro.S

/*
 * The ARM LDRD and Thumb LDRSB instructions use bit 20/11 (ARM/Thumb)
 * differently than every other instruction, so it is set to 0 (write)
 * even though the instructions are read instructions. This means that
 * during an abort the instructions will be treated as a write and the
 * handler will raise a signal from unwriteable locations if they
 * fault. We have to specifically check for these instructions
 * from the abort handlers to treat them properly.
 *
 */

	.macro	do_thumb_abort, fsr, pc, psr, tmp
	tst	\psr, #PSR_T_BIT
	beq	not_thumb
	ldrh	\tmp, [\pc]			@ Read aborted Thumb instruction
	and	\tmp, \tmp, # 0xfe00		@ Mask opcode field
	cmp	\tmp, # 0x5600			@ Is it ldrsb?
	orreq	\tmp, \tmp, #1 << 11		@ Set L-bit if yes
	tst	\tmp, #1 << 11			@ L = 0 -> write
	orreq	\fsr, \fsr, #1 << 11		@ yes.
	b	do_DataAbort
not_thumb:
	.endm

/*
 * We check for the following instruction encoding for LDRD.
 *
 * [27:25] == 000
 *   [7:4] == 1101
 *    [20] == 0
 */
	.macro	do_ldrd_abort, tmp, insn
	tst	\insn, #0x0e100000		@ [27:25,20] == 0
	bne	not_ldrd
	and	\tmp, \insn, #0x000000f0	@ [7:4] == 1101
	cmp	\tmp, #0x000000d0
	beq	do_DataAbort
not_ldrd:
	.endm
Commit	Line	Data
1da177e4 LT	1	/*
	2	* The ARM LDRD and Thumb LDRSB instructions use bit 20/11 (ARM/Thumb)
	3	* differently than every other instruction, so it is set to 0 (write)
	4	* even though the instructions are read instructions. This means that
	5	* during an abort the instructions will be treated as a write and the
	6	* handler will raise a signal from unwriteable locations if they
	7	* fault. We have to specifically check for these instructions
	8	* from the abort handlers to treat them properly.
	9	*
	10	*/
	11
be020f86 RK	12	.macro do_thumb_abort, fsr, pc, psr, tmp
be020f86 RK	13	tst \psr, #PSR_T_BIT
1da177e4	14	beq not_thumb
be020f86 RK	15	ldrh \tmp, [\pc] @ Read aborted Thumb instruction
	16	and \tmp, \tmp, # 0xfe00 @ Mask opcode field
	17	cmp \tmp, # 0x5600 @ Is it ldrsb?
	18	orreq \tmp, \tmp, #1 << 11 @ Set L-bit if yes
	19	tst \tmp, #1 << 11 @ L = 0 -> write
6c6d8deb	20	orreq \fsr, \fsr, #1 << 11 @ yes.
da740472	21	b do_DataAbort
1da177e4 LT	22	not_thumb:
	23	.endm
	24
	25	/*
be020f86	26	* We check for the following instruction encoding for LDRD.
1da177e4	27	*
be020f86	28	* [27:25] == 000
1da177e4 LT	29	* [7:4] == 1101
	30	* [20] == 0
	31	*/
be020f86	32	.macro do_ldrd_abort, tmp, insn
198a0a92	33	tst \insn, #0x0e100000 @ [27:25,20] == 0
1da177e4	34	bne not_ldrd
be020f86 RK	35	and \tmp, \insn, #0x000000f0 @ [7:4] == 1101
be020f86 RK	36	cmp \tmp, #0x000000d0
da740472	37	beq do_DataAbort
1da177e4 LT	38	not_ldrd:
	39	.endm
	40