[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mm / abort-ev6.S

#include <linux/linkage.h>
#include <asm/assembler.h>
#include "abort-macro.S"
/*
 * Function: v6_early_abort
 *
 * Params  : r2 = address of aborted instruction
 *         : r3 = saved SPSR
 *
 * Returns : r0 = address of abort
 *	   : r1 = FSR, bit 11 = write
 *	   : r2-r8 = corrupted
 *	   : r9 = preserved
 *	   : sp = pointer to registers
 *
 * Purpose : obtain information about current aborted instruction.
 * Note: we read user space.  This means we might cause a data
 * abort here if the I-TLB and D-TLB aren't seeing the same
 * picture.  Unfortunately, this does happen.  We live with it.
 */
	.align	5
ENTRY(v6_early_abort)
#ifdef CONFIG_CPU_V6
	sub	r1, sp, #4			@ Get unused stack location
	strex	r0, r1, [r1]			@ Clear the exclusive monitor
#elif defined(CONFIG_CPU_32v6K)
	clrex
#endif
	mrc	p15, 0, r1, c5, c0, 0		@ get FSR
	mrc	p15, 0, r0, c6, c0, 0		@ get FAR
/*
 * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR (erratum 326103).
 * The test below covers all the write situations, including Java bytecodes
 */
	bic	r1, r1, #1 << 11		@ clear bit 11 of FSR
	tst	r3, #PSR_J_BIT			@ Java?
	movne	pc, lr
	do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3
	ldreq	r3, [r2]			@ read aborted ARM instruction
#ifdef CONFIG_CPU_ENDIAN_BE8
	reveq	r3, r3
#endif
	do_ldrd_abort tmp=r2, insn=r3
	tst	r3, #1 << 20			@ L = 0 -> write
	orreq	r1, r1, #1 << 11		@ yes.
	mov	pc, lr
Commit	Line	Data
1da177e4 LT	1	#include <linux/linkage.h>
1da177e4 LT	2	#include <asm/assembler.h>
3a1e5015	3	#include "abort-macro.S"
1da177e4 LT	4	/*
	5	* Function: v6_early_abort
	6	*
	7	* Params : r2 = address of aborted instruction
	8	* : r3 = saved SPSR
	9	*
	10	* Returns : r0 = address of abort
	11	* : r1 = FSR, bit 11 = write
	12	* : r2-r8 = corrupted
	13	* : r9 = preserved
	14	* : sp = pointer to registers
	15	*
	16	* Purpose : obtain information about current aborted instruction.
3a1e5015 GD	17	* Note: we read user space. This means we might cause a data
	18	* abort here if the I-TLB and D-TLB aren't seeing the same
	19	* picture. Unfortunately, this does happen. We live with it.
1da177e4 LT	20	*/
	21	.align 5
	22	ENTRY(v6_early_abort)
7db44c75	23	#ifdef CONFIG_CPU_V6
25ef4a67 SF	24	sub r1, sp, #4 @ Get unused stack location
25ef4a67 SF	25	strex r0, r1, [r1] @ Clear the exclusive monitor
7db44c75 RK	26	#elif defined(CONFIG_CPU_32v6K)
7db44c75 RK	27	clrex
2c3a0540	28	#endif
1da177e4 LT	29	mrc p15, 0, r1, c5, c0, 0 @ get FSR
1da177e4 LT	30	mrc p15, 0, r0, c6, c0, 0 @ get FAR
3a1e5015	31	/*
fe68e68f	32	* Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR (erratum 326103).
3a1e5015 GD	33	* The test below covers all the write situations, including Java bytecodes
3a1e5015 GD	34	*/
fe68e68f	35	bic r1, r1, #1 << 11 @ clear bit 11 of FSR
3a1e5015 GD	36	tst r3, #PSR_J_BIT @ Java?
3a1e5015 GD	37	movne pc, lr
be020f86	38	do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3
3a1e5015	39	ldreq r3, [r2] @ read aborted ARM instruction
26584853 CM	40	#ifdef CONFIG_CPU_ENDIAN_BE8
	41	reveq r3, r3
	42	#endif
be020f86	43	do_ldrd_abort tmp=r2, insn=r3
3a1e5015 GD	44	tst r3, #1 << 20 @ L = 0 -> write
3a1e5015 GD	45	orreq r1, r1, #1 << 11 @ yes.
1da177e4 LT	46	mov pc, lr
	47
	48