[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-vexpress / include / mach / motherboard.h

#ifndef __MACH_MOTHERBOARD_H
#define __MACH_MOTHERBOARD_H

#include <linux/clk-provider.h>

/*
 * Physical addresses, offset from V2M_PA_CS0-3
 */
#define V2M_NOR0		(V2M_PA_CS0)
#define V2M_NOR1		(V2M_PA_CS1)
#define V2M_SRAM		(V2M_PA_CS2)
#define V2M_VIDEO_SRAM		(V2M_PA_CS3 + 0x00000000)
#define V2M_LAN9118		(V2M_PA_CS3 + 0x02000000)
#define V2M_ISP1761		(V2M_PA_CS3 + 0x03000000)

/*
 * Physical addresses, offset from V2M_PA_CS7
 */
#define V2M_SYSREGS		(V2M_PA_CS7 + 0x00000000)
#define V2M_SYSCTL		(V2M_PA_CS7 + 0x00001000)
#define V2M_SERIAL_BUS_PCI	(V2M_PA_CS7 + 0x00002000)

#define V2M_AACI		(V2M_PA_CS7 + 0x00004000)
#define V2M_MMCI		(V2M_PA_CS7 + 0x00005000)
#define V2M_KMI0		(V2M_PA_CS7 + 0x00006000)
#define V2M_KMI1		(V2M_PA_CS7 + 0x00007000)

#define V2M_UART0		(V2M_PA_CS7 + 0x00009000)
#define V2M_UART1		(V2M_PA_CS7 + 0x0000a000)
#define V2M_UART2		(V2M_PA_CS7 + 0x0000b000)
#define V2M_UART3		(V2M_PA_CS7 + 0x0000c000)

#define V2M_WDT			(V2M_PA_CS7 + 0x0000f000)

#define V2M_TIMER01		(V2M_PA_CS7 + 0x00011000)
#define V2M_TIMER23		(V2M_PA_CS7 + 0x00012000)

#define V2M_SERIAL_BUS_DVI	(V2M_PA_CS7 + 0x00016000)
#define V2M_RTC			(V2M_PA_CS7 + 0x00017000)

#define V2M_CF			(V2M_PA_CS7 + 0x0001a000)
#define V2M_CLCD		(V2M_PA_CS7 + 0x0001f000)

/*
 * Offsets from SYSREGS base
 */
#define V2M_SYS_ID		0x000
#define V2M_SYS_SW		0x004
#define V2M_SYS_LED		0x008
#define V2M_SYS_100HZ		0x024
#define V2M_SYS_FLAGS		0x030
#define V2M_SYS_FLAGSSET	0x030
#define V2M_SYS_FLAGSCLR	0x034
#define V2M_SYS_NVFLAGS		0x038
#define V2M_SYS_NVFLAGSSET	0x038
#define V2M_SYS_NVFLAGSCLR	0x03c
#define V2M_SYS_MCI		0x048
#define V2M_SYS_FLASH		0x03c
#define V2M_SYS_CFGSW		0x058
#define V2M_SYS_24MHZ		0x05c
#define V2M_SYS_MISC		0x060
#define V2M_SYS_DMA		0x064
#define V2M_SYS_PROCID0		0x084
#define V2M_SYS_PROCID1		0x088
#define V2M_SYS_CFGDATA		0x0a0
#define V2M_SYS_CFGCTRL		0x0a4
#define V2M_SYS_CFGSTAT		0x0a8


/*
 * Interrupts.  Those in {} are for AMBA devices
 */
#define IRQ_V2M_WDT		{ (32 + 0) }
#define IRQ_V2M_TIMER0		(32 + 2)
#define IRQ_V2M_TIMER1		(32 + 2)
#define IRQ_V2M_TIMER2		(32 + 3)
#define IRQ_V2M_TIMER3		(32 + 3)
#define IRQ_V2M_RTC		{ (32 + 4) }
#define IRQ_V2M_UART0		{ (32 + 5) }
#define IRQ_V2M_UART1		{ (32 + 6) }
#define IRQ_V2M_UART2		{ (32 + 7) }
#define IRQ_V2M_UART3		{ (32 + 8) }
#define IRQ_V2M_MMCI		{ (32 + 9), (32 + 10) }
#define IRQ_V2M_AACI		{ (32 + 11) }
#define IRQ_V2M_KMI0		{ (32 + 12) }
#define IRQ_V2M_KMI1		{ (32 + 13) }
#define IRQ_V2M_CLCD		{ (32 + 14) }
#define IRQ_V2M_LAN9118		(32 + 15)
#define IRQ_V2M_ISP1761		(32 + 16)
#define IRQ_V2M_PCIE		(32 + 17)


/*
 * Configuration
 */
#define SYS_CFG_START		(1 << 31)
#define SYS_CFG_WRITE		(1 << 30)
#define SYS_CFG_OSC		(1 << 20)
#define SYS_CFG_VOLT		(2 << 20)
#define SYS_CFG_AMP		(3 << 20)
#define SYS_CFG_TEMP		(4 << 20)
#define SYS_CFG_RESET		(5 << 20)
#define SYS_CFG_SCC		(6 << 20)
#define SYS_CFG_MUXFPGA		(7 << 20)
#define SYS_CFG_SHUTDOWN	(8 << 20)
#define SYS_CFG_REBOOT		(9 << 20)
#define SYS_CFG_DVIMODE		(11 << 20)
#define SYS_CFG_POWER		(12 << 20)
#define SYS_CFG_SITE(n)		((n) << 16)
#define SYS_CFG_SITE_MB		0
#define SYS_CFG_SITE_DB1	1
#define SYS_CFG_SITE_DB2	2
#define SYS_CFG_STACK(n)	((n) << 12)

#define SYS_CFG_ERR		(1 << 1)
#define SYS_CFG_COMPLETE	(1 << 0)

int v2m_cfg_write(u32 devfn, u32 data);
int v2m_cfg_read(u32 devfn, u32 *data);
void v2m_flags_set(u32 data);

/*
 * Miscellaneous
 */
#define SYS_MISC_MASTERSITE	(1 << 14)
#define SYS_PROCIDx_HBI_MASK	0xfff

int v2m_get_master_site(void);

/*
 * Core tile IDs
 */
#define V2M_CT_ID_CA9		0x0c000191
#define V2M_CT_ID_UNSUPPORTED	0xff000191
#define V2M_CT_ID_MASK		0xff000fff

struct ct_desc {
	u32			id;
	const char		*name;
	void			(*map_io)(void);
	void			(*init_early)(void);
	void			(*init_irq)(void);
	void			(*init_tile)(void);
#ifdef CONFIG_SMP
	void			(*init_cpu_map)(void);
	void			(*smp_enable)(unsigned int);
#endif
};

extern struct ct_desc *ct_desc;

/*
 * OSC clock provider
 */
struct v2m_osc {
	struct clk_hw hw;
	u8 site; /* 0 = motherboard, 1 = site 1, 2 = site 2 */
	u8 stack; /* board stack position */
	u16 osc;
	unsigned long rate_min;
	unsigned long rate_max;
	unsigned long rate_default;
};

#define to_v2m_osc(osc) container_of(osc, struct v2m_osc, hw)

struct clk *v2m_osc_register(const char *name, struct v2m_osc *osc);

#endif
Commit	Line	Data
ceade897 RK	1	#ifndef __MACH_MOTHERBOARD_H
	2	#define __MACH_MOTHERBOARD_H
	3
d1b8a775 PM	4	#include <linux/clk-provider.h>
d1b8a775 PM	5
ceade897 RK	6	/*
	7	* Physical addresses, offset from V2M_PA_CS0-3
	8	*/
	9	#define V2M_NOR0 (V2M_PA_CS0)
	10	#define V2M_NOR1 (V2M_PA_CS1)
	11	#define V2M_SRAM (V2M_PA_CS2)
	12	#define V2M_VIDEO_SRAM (V2M_PA_CS3 + 0x00000000)
	13	#define V2M_LAN9118 (V2M_PA_CS3 + 0x02000000)
	14	#define V2M_ISP1761 (V2M_PA_CS3 + 0x03000000)
	15
	16	/*
	17	* Physical addresses, offset from V2M_PA_CS7
	18	*/
	19	#define V2M_SYSREGS (V2M_PA_CS7 + 0x00000000)
	20	#define V2M_SYSCTL (V2M_PA_CS7 + 0x00001000)
	21	#define V2M_SERIAL_BUS_PCI (V2M_PA_CS7 + 0x00002000)
	22
	23	#define V2M_AACI (V2M_PA_CS7 + 0x00004000)
	24	#define V2M_MMCI (V2M_PA_CS7 + 0x00005000)
	25	#define V2M_KMI0 (V2M_PA_CS7 + 0x00006000)
	26	#define V2M_KMI1 (V2M_PA_CS7 + 0x00007000)
	27
	28	#define V2M_UART0 (V2M_PA_CS7 + 0x00009000)
	29	#define V2M_UART1 (V2M_PA_CS7 + 0x0000a000)
	30	#define V2M_UART2 (V2M_PA_CS7 + 0x0000b000)
	31	#define V2M_UART3 (V2M_PA_CS7 + 0x0000c000)
	32
	33	#define V2M_WDT (V2M_PA_CS7 + 0x0000f000)
	34
	35	#define V2M_TIMER01 (V2M_PA_CS7 + 0x00011000)
	36	#define V2M_TIMER23 (V2M_PA_CS7 + 0x00012000)
	37
	38	#define V2M_SERIAL_BUS_DVI (V2M_PA_CS7 + 0x00016000)
	39	#define V2M_RTC (V2M_PA_CS7 + 0x00017000)
	40
	41	#define V2M_CF (V2M_PA_CS7 + 0x0001a000)
	42	#define V2M_CLCD (V2M_PA_CS7 + 0x0001f000)
	43
98ed4ceb PM	44	/*
	45	* Offsets from SYSREGS base
	46	*/
	47	#define V2M_SYS_ID 0x000
	48	#define V2M_SYS_SW 0x004
	49	#define V2M_SYS_LED 0x008
	50	#define V2M_SYS_100HZ 0x024
	51	#define V2M_SYS_FLAGS 0x030
	52	#define V2M_SYS_FLAGSSET 0x030
	53	#define V2M_SYS_FLAGSCLR 0x034
	54	#define V2M_SYS_NVFLAGS 0x038
	55	#define V2M_SYS_NVFLAGSSET 0x038
	56	#define V2M_SYS_NVFLAGSCLR 0x03c
	57	#define V2M_SYS_MCI 0x048
	58	#define V2M_SYS_FLASH 0x03c
	59	#define V2M_SYS_CFGSW 0x058
	60	#define V2M_SYS_24MHZ 0x05c
	61	#define V2M_SYS_MISC 0x060
	62	#define V2M_SYS_DMA 0x064
	63	#define V2M_SYS_PROCID0 0x084
	64	#define V2M_SYS_PROCID1 0x088
	65	#define V2M_SYS_CFGDATA 0x0a0
	66	#define V2M_SYS_CFGCTRL 0x0a4
	67	#define V2M_SYS_CFGSTAT 0x0a8
ceade897 RK	68
	69
	70	/*
	71	* Interrupts. Those in {} are for AMBA devices
	72	*/
	73	#define IRQ_V2M_WDT { (32 + 0) }
	74	#define IRQ_V2M_TIMER0 (32 + 2)
	75	#define IRQ_V2M_TIMER1 (32 + 2)
	76	#define IRQ_V2M_TIMER2 (32 + 3)
	77	#define IRQ_V2M_TIMER3 (32 + 3)
	78	#define IRQ_V2M_RTC { (32 + 4) }
	79	#define IRQ_V2M_UART0 { (32 + 5) }
	80	#define IRQ_V2M_UART1 { (32 + 6) }
	81	#define IRQ_V2M_UART2 { (32 + 7) }
	82	#define IRQ_V2M_UART3 { (32 + 8) }
	83	#define IRQ_V2M_MMCI { (32 + 9), (32 + 10) }
	84	#define IRQ_V2M_AACI { (32 + 11) }
	85	#define IRQ_V2M_KMI0 { (32 + 12) }
	86	#define IRQ_V2M_KMI1 { (32 + 13) }
	87	#define IRQ_V2M_CLCD { (32 + 14) }
	88	#define IRQ_V2M_LAN9118 (32 + 15)
	89	#define IRQ_V2M_ISP1761 (32 + 16)
	90	#define IRQ_V2M_PCIE (32 + 17)
	91
	92
	93	/*
	94	* Configuration
	95	*/
	96	#define SYS_CFG_START (1 << 31)
	97	#define SYS_CFG_WRITE (1 << 30)
	98	#define SYS_CFG_OSC (1 << 20)
	99	#define SYS_CFG_VOLT (2 << 20)
	100	#define SYS_CFG_AMP (3 << 20)
	101	#define SYS_CFG_TEMP (4 << 20)
	102	#define SYS_CFG_RESET (5 << 20)
	103	#define SYS_CFG_SCC (6 << 20)
	104	#define SYS_CFG_MUXFPGA (7 << 20)
	105	#define SYS_CFG_SHUTDOWN (8 << 20)
	106	#define SYS_CFG_REBOOT (9 << 20)
	107	#define SYS_CFG_DVIMODE (11 << 20)
	108	#define SYS_CFG_POWER (12 << 20)
d927daf5 PM	109	#define SYS_CFG_SITE(n) ((n) << 16)
	110	#define SYS_CFG_SITE_MB 0
	111	#define SYS_CFG_SITE_DB1 1
	112	#define SYS_CFG_SITE_DB2 2
ceade897 RK	113	#define SYS_CFG_STACK(n) ((n) << 12)
	114
	115	#define SYS_CFG_ERR (1 << 1)
	116	#define SYS_CFG_COMPLETE (1 << 0)
	117
	118	int v2m_cfg_write(u32 devfn, u32 data);
	119	int v2m_cfg_read(u32 devfn, u32 *data);
98ed4ceb	120	void v2m_flags_set(u32 data);
ceade897	121
8deed178 PM	122	/*
	123	* Miscellaneous
	124	*/
	125	#define SYS_MISC_MASTERSITE (1 << 14)
	126	#define SYS_PROCIDx_HBI_MASK 0xfff
	127
d927daf5 PM	128	int v2m_get_master_site(void);
d927daf5 PM	129
80b5efbd WD	130	/*
	131	* Core tile IDs
	132	*/
	133	#define V2M_CT_ID_CA9 0x0c000191
	134	#define V2M_CT_ID_UNSUPPORTED 0xff000191
	135	#define V2M_CT_ID_MASK 0xff000fff
	136
	137	struct ct_desc {
	138	u32 id;
	139	const char *name;
	140	void (*map_io)(void);
	141	void (*init_early)(void);
	142	void (*init_irq)(void);
	143	void (*init_tile)(void);
	144	#ifdef CONFIG_SMP
	145	void (*init_cpu_map)(void);
	146	void (*smp_enable)(unsigned int);
	147	#endif
	148	};
	149
	150	extern struct ct_desc *ct_desc;
	151
d1b8a775 PM	152	/*
	153	* OSC clock provider
	154	*/
	155	struct v2m_osc {
	156	struct clk_hw hw;
	157	u8 site; /* 0 = motherboard, 1 = site 1, 2 = site 2 */
	158	u8 stack; /* board stack position */
	159	u16 osc;
	160	unsigned long rate_min;
	161	unsigned long rate_max;
	162	unsigned long rate_default;
	163	};
	164
	165	#define to_v2m_osc(osc) container_of(osc, struct v2m_osc, hw)
	166
	167	struct clk v2m_osc_register(const char name, struct v2m_osc *osc);
	168
ceade897	169	#endif