Commit | Line | Data |
---|---|---|
c5f80065 | 1 | /* |
c37c07dd | 2 | * arch/arm/mach-tegra/common.c |
c5f80065 | 3 | * |
d2ffb918 | 4 | * Copyright (c) 2013 NVIDIA Corporation. All rights reserved. |
c5f80065 EG |
5 | * Copyright (C) 2010 Google, Inc. |
6 | * | |
7 | * Author: | |
8 | * Colin Cross <ccross@android.com> | |
9 | * | |
10 | * This software is licensed under the terms of the GNU General Public | |
11 | * License version 2, as published by the Free Software Foundation, and | |
12 | * may be copied, distributed, and modified under those terms. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | */ | |
20 | ||
21 | #include <linux/init.h> | |
22 | #include <linux/io.h> | |
4de3a8fa CC |
23 | #include <linux/clk.h> |
24 | #include <linux/delay.h> | |
79e43826 | 25 | #include <linux/of.h> |
0529e315 | 26 | #include <linux/irqchip.h> |
61fd290d | 27 | #include <linux/clk/tegra.h> |
c5f80065 EG |
28 | |
29 | #include <asm/hardware/cache-l2x0.h> | |
30 | ||
c5f80065 | 31 | #include "board.h" |
a1725732 | 32 | #include "common.h" |
73625e3e | 33 | #include "fuse.h" |
2be39c07 | 34 | #include "iomap.h" |
e307cc89 | 35 | #include "irq.h" |
d3b8bdd5 | 36 | #include "pmc.h" |
b861c275 | 37 | #include "apbio.h" |
59b0f682 | 38 | #include "sleep.h" |
29a0e7be | 39 | #include "pm.h" |
9e32366f | 40 | #include "reset.h" |
d8611961 | 41 | |
6d7d7b3e SW |
42 | /* |
43 | * Storage for debug-macro.S's state. | |
44 | * | |
45 | * This must be in .data not .bss so that it gets initialized each time the | |
46 | * kernel is loaded. The data is declared here rather than debug-macro.S so | |
47 | * that multiple inclusions of debug-macro.S point at the same data. | |
48 | */ | |
1a6d3da8 | 49 | u32 tegra_uart_config[4] = { |
6d7d7b3e SW |
50 | /* Debug UART initialization required */ |
51 | 1, | |
52 | /* Debug UART physical address */ | |
adc18315 | 53 | 0, |
6d7d7b3e | 54 | /* Debug UART virtual address */ |
adc18315 | 55 | 0, |
1a6d3da8 SW |
56 | /* Scratch space for debug macro */ |
57 | 0, | |
6d7d7b3e | 58 | }; |
d8611961 | 59 | |
6cc04a44 | 60 | #ifdef CONFIG_OF |
c37c07dd PDS |
61 | void __init tegra_dt_init_irq(void) |
62 | { | |
61fd290d | 63 | tegra_clocks_init(); |
0337c3e0 | 64 | tegra_pmc_init(); |
c37c07dd | 65 | tegra_init_irq(); |
0529e315 | 66 | irqchip_init(); |
e307cc89 | 67 | tegra_legacy_irq_syscore_init(); |
c37c07dd | 68 | } |
6cc04a44 | 69 | #endif |
c37c07dd | 70 | |
699fe145 CC |
71 | void tegra_assert_system_reset(char mode, const char *cmd) |
72 | { | |
9bfc3f0d | 73 | void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0); |
699fe145 CC |
74 | u32 reg; |
75 | ||
375b19cd | 76 | reg = readl_relaxed(reset); |
9bfc3f0d | 77 | reg |= 0x10; |
375b19cd | 78 | writel_relaxed(reg, reset); |
699fe145 CC |
79 | } |
80 | ||
d065ab71 | 81 | static void __init tegra_init_cache(void) |
c5f80065 EG |
82 | { |
83 | #ifdef CONFIG_CACHE_L2X0 | |
79e43826 SW |
84 | static const struct of_device_id pl310_ids[] __initconst = { |
85 | { .compatible = "arm,pl310-cache", }, | |
86 | {} | |
87 | }; | |
88 | ||
89 | struct device_node *np; | |
29a0e7be | 90 | int ret; |
c5f80065 | 91 | void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; |
01548673 | 92 | u32 aux_ctrl, cache_type; |
c5f80065 | 93 | |
79e43826 SW |
94 | np = of_find_matching_node(NULL, pl310_ids); |
95 | if (!np) | |
96 | return; | |
97 | ||
01548673 PDS |
98 | cache_type = readl(p + L2X0_CACHE_TYPE); |
99 | aux_ctrl = (cache_type & 0x700) << (17-8); | |
fd072a86 | 100 | aux_ctrl |= 0x7C400001; |
01548673 | 101 | |
29a0e7be JL |
102 | ret = l2x0_of_init(aux_ctrl, 0x8200c3fe); |
103 | if (!ret) | |
104 | l2x0_saved_regs_addr = virt_to_phys(&l2x0_saved_regs); | |
c5f80065 | 105 | #endif |
4de3a8fa | 106 | |
c5f80065 EG |
107 | } |
108 | ||
7469688e | 109 | void __init tegra_init_early(void) |
c5f80065 | 110 | { |
9e32366f | 111 | tegra_cpu_reset_handler_init(); |
b861c275 | 112 | tegra_apb_io_init(); |
73625e3e | 113 | tegra_init_fuse(); |
d065ab71 | 114 | tegra_init_cache(); |
65fe31da | 115 | tegra_powergate_init(); |
7469688e | 116 | tegra_hotplug_init(); |
d2ffb918 OJ |
117 | } |
118 | ||
390e0cfd SG |
119 | void __init tegra_init_late(void) |
120 | { | |
c8c2e606 | 121 | tegra_init_suspend(); |
390e0cfd SG |
122 | tegra_powergate_debugfs_init(); |
123 | } |