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bc4e814e VK |
1 | /* |
2 | * arch/arm/mach-spear3xx/spear3xx.c | |
3 | * | |
4 | * SPEAr3XX machines common source file | |
5 | * | |
6 | * Copyright (C) 2009 ST Microelectronics | |
7 | * Viresh Kumar<viresh.kumar@st.com> | |
8 | * | |
9 | * This file is licensed under the terms of the GNU General Public | |
10 | * License version 2. This program is licensed "as is" without any | |
11 | * warranty of any kind, whether express or implied. | |
12 | */ | |
13 | ||
14 | #include <linux/types.h> | |
15 | #include <linux/amba/pl061.h> | |
16 | #include <linux/ptrace.h> | |
17 | #include <linux/io.h> | |
18 | #include <asm/hardware/vic.h> | |
19 | #include <asm/irq.h> | |
20 | #include <asm/mach/arch.h> | |
21 | #include <mach/generic.h> | |
22 | #include <mach/spear.h> | |
23 | ||
24 | /* Add spear3xx machines common devices here */ | |
b595076a | 25 | /* gpio device registration */ |
bc4e814e VK |
26 | static struct pl061_platform_data gpio_plat_data = { |
27 | .gpio_base = 0, | |
28 | .irq_base = SPEAR_GPIO_INT_BASE, | |
29 | }; | |
30 | ||
31 | struct amba_device gpio_device = { | |
32 | .dev = { | |
33 | .init_name = "gpio", | |
34 | .platform_data = &gpio_plat_data, | |
35 | }, | |
36 | .res = { | |
37 | .start = SPEAR3XX_ICM3_GPIO_BASE, | |
38 | .end = SPEAR3XX_ICM3_GPIO_BASE + SPEAR3XX_ICM3_GPIO_SIZE - 1, | |
39 | .flags = IORESOURCE_MEM, | |
40 | }, | |
41 | .irq = {IRQ_BASIC_GPIO, NO_IRQ}, | |
42 | }; | |
43 | ||
b595076a | 44 | /* uart device registration */ |
bc4e814e VK |
45 | struct amba_device uart_device = { |
46 | .dev = { | |
47 | .init_name = "uart", | |
48 | }, | |
49 | .res = { | |
50 | .start = SPEAR3XX_ICM1_UART_BASE, | |
51 | .end = SPEAR3XX_ICM1_UART_BASE + SPEAR3XX_ICM1_UART_SIZE - 1, | |
52 | .flags = IORESOURCE_MEM, | |
53 | }, | |
54 | .irq = {IRQ_UART, NO_IRQ}, | |
55 | }; | |
56 | ||
57 | /* Do spear3xx familiy common initialization part here */ | |
58 | void __init spear3xx_init(void) | |
59 | { | |
60 | /* nothing to do for now */ | |
61 | } | |
62 | ||
63 | /* This will initialize vic */ | |
64 | void __init spear3xx_init_irq(void) | |
65 | { | |
66 | vic_init((void __iomem *)VA_SPEAR3XX_ML1_VIC_BASE, 0, ~0, 0); | |
67 | } | |
68 | ||
69 | /* Following will create static virtual/physical mappings */ | |
70 | struct map_desc spear3xx_io_desc[] __initdata = { | |
71 | { | |
72 | .virtual = VA_SPEAR3XX_ICM1_UART_BASE, | |
73 | .pfn = __phys_to_pfn(SPEAR3XX_ICM1_UART_BASE), | |
74 | .length = SPEAR3XX_ICM1_UART_SIZE, | |
75 | .type = MT_DEVICE | |
76 | }, { | |
77 | .virtual = VA_SPEAR3XX_ML1_VIC_BASE, | |
78 | .pfn = __phys_to_pfn(SPEAR3XX_ML1_VIC_BASE), | |
79 | .length = SPEAR3XX_ML1_VIC_SIZE, | |
80 | .type = MT_DEVICE | |
81 | }, { | |
82 | .virtual = VA_SPEAR3XX_ICM3_SYS_CTRL_BASE, | |
83 | .pfn = __phys_to_pfn(SPEAR3XX_ICM3_SYS_CTRL_BASE), | |
84 | .length = SPEAR3XX_ICM3_SYS_CTRL_SIZE, | |
85 | .type = MT_DEVICE | |
86 | }, { | |
87 | .virtual = VA_SPEAR3XX_ICM3_MISC_REG_BASE, | |
88 | .pfn = __phys_to_pfn(SPEAR3XX_ICM3_MISC_REG_BASE), | |
89 | .length = SPEAR3XX_ICM3_MISC_REG_SIZE, | |
90 | .type = MT_DEVICE | |
91 | }, | |
92 | }; | |
93 | ||
94 | /* This will create static memory mapping for selected devices */ | |
95 | void __init spear3xx_map_io(void) | |
96 | { | |
97 | iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc)); | |
98 | ||
99 | /* This will initialize clock framework */ | |
100 | clk_init(); | |
101 | } | |
70f4c0bf VK |
102 | |
103 | /* pad multiplexing support */ | |
104 | /* devices */ | |
105 | struct pmx_dev_mode pmx_firda_modes[] = { | |
106 | { | |
107 | .ids = 0xffffffff, | |
108 | .mask = PMX_FIRDA_MASK, | |
109 | }, | |
110 | }; | |
111 | ||
112 | struct pmx_dev pmx_firda = { | |
113 | .name = "firda", | |
114 | .modes = pmx_firda_modes, | |
115 | .mode_count = ARRAY_SIZE(pmx_firda_modes), | |
116 | .enb_on_reset = 0, | |
117 | }; | |
118 | ||
119 | struct pmx_dev_mode pmx_i2c_modes[] = { | |
120 | { | |
121 | .ids = 0xffffffff, | |
122 | .mask = PMX_I2C_MASK, | |
123 | }, | |
124 | }; | |
125 | ||
126 | struct pmx_dev pmx_i2c = { | |
127 | .name = "i2c", | |
128 | .modes = pmx_i2c_modes, | |
129 | .mode_count = ARRAY_SIZE(pmx_i2c_modes), | |
130 | .enb_on_reset = 0, | |
131 | }; | |
132 | ||
133 | struct pmx_dev_mode pmx_ssp_cs_modes[] = { | |
134 | { | |
135 | .ids = 0xffffffff, | |
136 | .mask = PMX_SSP_CS_MASK, | |
137 | }, | |
138 | }; | |
139 | ||
140 | struct pmx_dev pmx_ssp_cs = { | |
141 | .name = "ssp_chip_selects", | |
142 | .modes = pmx_ssp_cs_modes, | |
143 | .mode_count = ARRAY_SIZE(pmx_ssp_cs_modes), | |
144 | .enb_on_reset = 0, | |
145 | }; | |
146 | ||
147 | struct pmx_dev_mode pmx_ssp_modes[] = { | |
148 | { | |
149 | .ids = 0xffffffff, | |
150 | .mask = PMX_SSP_MASK, | |
151 | }, | |
152 | }; | |
153 | ||
154 | struct pmx_dev pmx_ssp = { | |
155 | .name = "ssp", | |
156 | .modes = pmx_ssp_modes, | |
157 | .mode_count = ARRAY_SIZE(pmx_ssp_modes), | |
158 | .enb_on_reset = 0, | |
159 | }; | |
160 | ||
161 | struct pmx_dev_mode pmx_mii_modes[] = { | |
162 | { | |
163 | .ids = 0xffffffff, | |
164 | .mask = PMX_MII_MASK, | |
165 | }, | |
166 | }; | |
167 | ||
168 | struct pmx_dev pmx_mii = { | |
169 | .name = "mii", | |
170 | .modes = pmx_mii_modes, | |
171 | .mode_count = ARRAY_SIZE(pmx_mii_modes), | |
172 | .enb_on_reset = 0, | |
173 | }; | |
174 | ||
175 | struct pmx_dev_mode pmx_gpio_pin0_modes[] = { | |
176 | { | |
177 | .ids = 0xffffffff, | |
178 | .mask = PMX_GPIO_PIN0_MASK, | |
179 | }, | |
180 | }; | |
181 | ||
182 | struct pmx_dev pmx_gpio_pin0 = { | |
183 | .name = "gpio_pin0", | |
184 | .modes = pmx_gpio_pin0_modes, | |
185 | .mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes), | |
186 | .enb_on_reset = 0, | |
187 | }; | |
188 | ||
189 | struct pmx_dev_mode pmx_gpio_pin1_modes[] = { | |
190 | { | |
191 | .ids = 0xffffffff, | |
192 | .mask = PMX_GPIO_PIN1_MASK, | |
193 | }, | |
194 | }; | |
195 | ||
196 | struct pmx_dev pmx_gpio_pin1 = { | |
197 | .name = "gpio_pin1", | |
198 | .modes = pmx_gpio_pin1_modes, | |
199 | .mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes), | |
200 | .enb_on_reset = 0, | |
201 | }; | |
202 | ||
203 | struct pmx_dev_mode pmx_gpio_pin2_modes[] = { | |
204 | { | |
205 | .ids = 0xffffffff, | |
206 | .mask = PMX_GPIO_PIN2_MASK, | |
207 | }, | |
208 | }; | |
209 | ||
210 | struct pmx_dev pmx_gpio_pin2 = { | |
211 | .name = "gpio_pin2", | |
212 | .modes = pmx_gpio_pin2_modes, | |
213 | .mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes), | |
214 | .enb_on_reset = 0, | |
215 | }; | |
216 | ||
217 | struct pmx_dev_mode pmx_gpio_pin3_modes[] = { | |
218 | { | |
219 | .ids = 0xffffffff, | |
220 | .mask = PMX_GPIO_PIN3_MASK, | |
221 | }, | |
222 | }; | |
223 | ||
224 | struct pmx_dev pmx_gpio_pin3 = { | |
225 | .name = "gpio_pin3", | |
226 | .modes = pmx_gpio_pin3_modes, | |
227 | .mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes), | |
228 | .enb_on_reset = 0, | |
229 | }; | |
230 | ||
231 | struct pmx_dev_mode pmx_gpio_pin4_modes[] = { | |
232 | { | |
233 | .ids = 0xffffffff, | |
234 | .mask = PMX_GPIO_PIN4_MASK, | |
235 | }, | |
236 | }; | |
237 | ||
238 | struct pmx_dev pmx_gpio_pin4 = { | |
239 | .name = "gpio_pin4", | |
240 | .modes = pmx_gpio_pin4_modes, | |
241 | .mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes), | |
242 | .enb_on_reset = 0, | |
243 | }; | |
244 | ||
245 | struct pmx_dev_mode pmx_gpio_pin5_modes[] = { | |
246 | { | |
247 | .ids = 0xffffffff, | |
248 | .mask = PMX_GPIO_PIN5_MASK, | |
249 | }, | |
250 | }; | |
251 | ||
252 | struct pmx_dev pmx_gpio_pin5 = { | |
253 | .name = "gpio_pin5", | |
254 | .modes = pmx_gpio_pin5_modes, | |
255 | .mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes), | |
256 | .enb_on_reset = 0, | |
257 | }; | |
258 | ||
259 | struct pmx_dev_mode pmx_uart0_modem_modes[] = { | |
260 | { | |
261 | .ids = 0xffffffff, | |
262 | .mask = PMX_UART0_MODEM_MASK, | |
263 | }, | |
264 | }; | |
265 | ||
266 | struct pmx_dev pmx_uart0_modem = { | |
267 | .name = "uart0_modem", | |
268 | .modes = pmx_uart0_modem_modes, | |
269 | .mode_count = ARRAY_SIZE(pmx_uart0_modem_modes), | |
270 | .enb_on_reset = 0, | |
271 | }; | |
272 | ||
273 | struct pmx_dev_mode pmx_uart0_modes[] = { | |
274 | { | |
275 | .ids = 0xffffffff, | |
276 | .mask = PMX_UART0_MASK, | |
277 | }, | |
278 | }; | |
279 | ||
280 | struct pmx_dev pmx_uart0 = { | |
281 | .name = "uart0", | |
282 | .modes = pmx_uart0_modes, | |
283 | .mode_count = ARRAY_SIZE(pmx_uart0_modes), | |
284 | .enb_on_reset = 0, | |
285 | }; | |
286 | ||
287 | struct pmx_dev_mode pmx_timer_3_4_modes[] = { | |
288 | { | |
289 | .ids = 0xffffffff, | |
290 | .mask = PMX_TIMER_3_4_MASK, | |
291 | }, | |
292 | }; | |
293 | ||
294 | struct pmx_dev pmx_timer_3_4 = { | |
295 | .name = "timer_3_4", | |
296 | .modes = pmx_timer_3_4_modes, | |
297 | .mode_count = ARRAY_SIZE(pmx_timer_3_4_modes), | |
298 | .enb_on_reset = 0, | |
299 | }; | |
300 | ||
301 | struct pmx_dev_mode pmx_timer_1_2_modes[] = { | |
302 | { | |
303 | .ids = 0xffffffff, | |
304 | .mask = PMX_TIMER_1_2_MASK, | |
305 | }, | |
306 | }; | |
307 | ||
308 | struct pmx_dev pmx_timer_1_2 = { | |
309 | .name = "timer_1_2", | |
310 | .modes = pmx_timer_1_2_modes, | |
311 | .mode_count = ARRAY_SIZE(pmx_timer_1_2_modes), | |
312 | .enb_on_reset = 0, | |
313 | }; | |
314 | ||
315 | #if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) | |
316 | /* plgpios devices */ | |
317 | struct pmx_dev_mode pmx_plgpio_0_1_modes[] = { | |
318 | { | |
319 | .ids = 0x00, | |
320 | .mask = PMX_FIRDA_MASK, | |
321 | }, | |
322 | }; | |
323 | ||
324 | struct pmx_dev pmx_plgpio_0_1 = { | |
325 | .name = "plgpio 0 and 1", | |
326 | .modes = pmx_plgpio_0_1_modes, | |
327 | .mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes), | |
328 | .enb_on_reset = 1, | |
329 | }; | |
330 | ||
331 | struct pmx_dev_mode pmx_plgpio_2_3_modes[] = { | |
332 | { | |
333 | .ids = 0x00, | |
334 | .mask = PMX_UART0_MASK, | |
335 | }, | |
336 | }; | |
337 | ||
338 | struct pmx_dev pmx_plgpio_2_3 = { | |
339 | .name = "plgpio 2 and 3", | |
340 | .modes = pmx_plgpio_2_3_modes, | |
341 | .mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes), | |
342 | .enb_on_reset = 1, | |
343 | }; | |
344 | ||
345 | struct pmx_dev_mode pmx_plgpio_4_5_modes[] = { | |
346 | { | |
347 | .ids = 0x00, | |
348 | .mask = PMX_I2C_MASK, | |
349 | }, | |
350 | }; | |
351 | ||
352 | struct pmx_dev pmx_plgpio_4_5 = { | |
353 | .name = "plgpio 4 and 5", | |
354 | .modes = pmx_plgpio_4_5_modes, | |
355 | .mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes), | |
356 | .enb_on_reset = 1, | |
357 | }; | |
358 | ||
359 | struct pmx_dev_mode pmx_plgpio_6_9_modes[] = { | |
360 | { | |
361 | .ids = 0x00, | |
362 | .mask = PMX_SSP_MASK, | |
363 | }, | |
364 | }; | |
365 | ||
366 | struct pmx_dev pmx_plgpio_6_9 = { | |
367 | .name = "plgpio 6 to 9", | |
368 | .modes = pmx_plgpio_6_9_modes, | |
369 | .mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes), | |
370 | .enb_on_reset = 1, | |
371 | }; | |
372 | ||
373 | struct pmx_dev_mode pmx_plgpio_10_27_modes[] = { | |
374 | { | |
375 | .ids = 0x00, | |
376 | .mask = PMX_MII_MASK, | |
377 | }, | |
378 | }; | |
379 | ||
380 | struct pmx_dev pmx_plgpio_10_27 = { | |
381 | .name = "plgpio 10 to 27", | |
382 | .modes = pmx_plgpio_10_27_modes, | |
383 | .mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes), | |
384 | .enb_on_reset = 1, | |
385 | }; | |
386 | ||
387 | struct pmx_dev_mode pmx_plgpio_28_modes[] = { | |
388 | { | |
389 | .ids = 0x00, | |
390 | .mask = PMX_GPIO_PIN0_MASK, | |
391 | }, | |
392 | }; | |
393 | ||
394 | struct pmx_dev pmx_plgpio_28 = { | |
395 | .name = "plgpio 28", | |
396 | .modes = pmx_plgpio_28_modes, | |
397 | .mode_count = ARRAY_SIZE(pmx_plgpio_28_modes), | |
398 | .enb_on_reset = 1, | |
399 | }; | |
400 | ||
401 | struct pmx_dev_mode pmx_plgpio_29_modes[] = { | |
402 | { | |
403 | .ids = 0x00, | |
404 | .mask = PMX_GPIO_PIN1_MASK, | |
405 | }, | |
406 | }; | |
407 | ||
408 | struct pmx_dev pmx_plgpio_29 = { | |
409 | .name = "plgpio 29", | |
410 | .modes = pmx_plgpio_29_modes, | |
411 | .mode_count = ARRAY_SIZE(pmx_plgpio_29_modes), | |
412 | .enb_on_reset = 1, | |
413 | }; | |
414 | ||
415 | struct pmx_dev_mode pmx_plgpio_30_modes[] = { | |
416 | { | |
417 | .ids = 0x00, | |
418 | .mask = PMX_GPIO_PIN2_MASK, | |
419 | }, | |
420 | }; | |
421 | ||
422 | struct pmx_dev pmx_plgpio_30 = { | |
423 | .name = "plgpio 30", | |
424 | .modes = pmx_plgpio_30_modes, | |
425 | .mode_count = ARRAY_SIZE(pmx_plgpio_30_modes), | |
426 | .enb_on_reset = 1, | |
427 | }; | |
428 | ||
429 | struct pmx_dev_mode pmx_plgpio_31_modes[] = { | |
430 | { | |
431 | .ids = 0x00, | |
432 | .mask = PMX_GPIO_PIN3_MASK, | |
433 | }, | |
434 | }; | |
435 | ||
436 | struct pmx_dev pmx_plgpio_31 = { | |
437 | .name = "plgpio 31", | |
438 | .modes = pmx_plgpio_31_modes, | |
439 | .mode_count = ARRAY_SIZE(pmx_plgpio_31_modes), | |
440 | .enb_on_reset = 1, | |
441 | }; | |
442 | ||
443 | struct pmx_dev_mode pmx_plgpio_32_modes[] = { | |
444 | { | |
445 | .ids = 0x00, | |
446 | .mask = PMX_GPIO_PIN4_MASK, | |
447 | }, | |
448 | }; | |
449 | ||
450 | struct pmx_dev pmx_plgpio_32 = { | |
451 | .name = "plgpio 32", | |
452 | .modes = pmx_plgpio_32_modes, | |
453 | .mode_count = ARRAY_SIZE(pmx_plgpio_32_modes), | |
454 | .enb_on_reset = 1, | |
455 | }; | |
456 | ||
457 | struct pmx_dev_mode pmx_plgpio_33_modes[] = { | |
458 | { | |
459 | .ids = 0x00, | |
460 | .mask = PMX_GPIO_PIN5_MASK, | |
461 | }, | |
462 | }; | |
463 | ||
464 | struct pmx_dev pmx_plgpio_33 = { | |
465 | .name = "plgpio 33", | |
466 | .modes = pmx_plgpio_33_modes, | |
467 | .mode_count = ARRAY_SIZE(pmx_plgpio_33_modes), | |
468 | .enb_on_reset = 1, | |
469 | }; | |
470 | ||
471 | struct pmx_dev_mode pmx_plgpio_34_36_modes[] = { | |
472 | { | |
473 | .ids = 0x00, | |
474 | .mask = PMX_SSP_CS_MASK, | |
475 | }, | |
476 | }; | |
477 | ||
478 | struct pmx_dev pmx_plgpio_34_36 = { | |
479 | .name = "plgpio 34 to 36", | |
480 | .modes = pmx_plgpio_34_36_modes, | |
481 | .mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes), | |
482 | .enb_on_reset = 1, | |
483 | }; | |
484 | ||
485 | struct pmx_dev_mode pmx_plgpio_37_42_modes[] = { | |
486 | { | |
487 | .ids = 0x00, | |
488 | .mask = PMX_UART0_MODEM_MASK, | |
489 | }, | |
490 | }; | |
491 | ||
492 | struct pmx_dev pmx_plgpio_37_42 = { | |
493 | .name = "plgpio 37 to 42", | |
494 | .modes = pmx_plgpio_37_42_modes, | |
495 | .mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes), | |
496 | .enb_on_reset = 1, | |
497 | }; | |
498 | ||
499 | struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = { | |
500 | { | |
501 | .ids = 0x00, | |
502 | .mask = PMX_TIMER_1_2_MASK, | |
503 | }, | |
504 | }; | |
505 | ||
506 | struct pmx_dev pmx_plgpio_43_44_47_48 = { | |
507 | .name = "plgpio 43, 44, 47 and 48", | |
508 | .modes = pmx_plgpio_43_44_47_48_modes, | |
509 | .mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes), | |
510 | .enb_on_reset = 1, | |
511 | }; | |
512 | ||
513 | struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = { | |
514 | { | |
515 | .ids = 0x00, | |
516 | .mask = PMX_TIMER_3_4_MASK, | |
517 | }, | |
518 | }; | |
519 | ||
520 | struct pmx_dev pmx_plgpio_45_46_49_50 = { | |
521 | .name = "plgpio 45, 46, 49 and 50", | |
522 | .modes = pmx_plgpio_45_46_49_50_modes, | |
523 | .mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes), | |
524 | .enb_on_reset = 1, | |
525 | }; | |
526 | ||
527 | #endif | |
528 | ||
529 | /* spear padmux initialization function */ | |
530 | void spear_pmx_init(struct pmx_driver *pmx_driver, uint base, uint size) | |
531 | { | |
532 | int ret = 0; | |
533 | ||
534 | /* pad mux initialization */ | |
535 | pmx_driver->base = ioremap(base, size); | |
536 | if (!pmx_driver->base) { | |
537 | ret = -ENOMEM; | |
538 | goto pmx_fail; | |
539 | } | |
540 | ||
541 | ret = pmx_register(pmx_driver); | |
542 | iounmap(pmx_driver->base); | |
543 | ||
544 | pmx_fail: | |
545 | if (ret) | |
b595076a | 546 | printk(KERN_ERR "padmux: registration failed. err no: %d\n", |
70f4c0bf VK |
547 | ret); |
548 | } |