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8c0236fc VK |
1 | /* |
2 | * arch/arm/mach-spear3xx/clock.c | |
3 | * | |
4 | * SPEAr3xx machines clock framework source file | |
5 | * | |
6 | * Copyright (C) 2009 ST Microelectronics | |
7 | * Viresh Kumar<viresh.kumar@st.com> | |
8 | * | |
9 | * This file is licensed under the terms of the GNU General Public | |
10 | * License version 2. This program is licensed "as is" without any | |
11 | * warranty of any kind, whether express or implied. | |
12 | */ | |
13 | ||
14 | #include <linux/init.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <mach/misc_regs.h> | |
17 | #include <plat/clock.h> | |
18 | ||
19 | /* root clks */ | |
20 | /* 32 KHz oscillator clock */ | |
21 | static struct clk osc_32k_clk = { | |
22 | .flags = ALWAYS_ENABLED, | |
23 | .rate = 32000, | |
24 | }; | |
25 | ||
26 | /* 24 MHz oscillator clock */ | |
27 | static struct clk osc_24m_clk = { | |
28 | .flags = ALWAYS_ENABLED, | |
29 | .rate = 24000000, | |
30 | }; | |
31 | ||
32 | /* clock derived from 32 KHz osc clk */ | |
33 | /* rtc clock */ | |
34 | static struct clk rtc_clk = { | |
35 | .pclk = &osc_32k_clk, | |
36 | .en_reg = PERIP1_CLK_ENB, | |
37 | .en_reg_bit = RTC_CLK_ENB, | |
38 | .recalc = &follow_parent, | |
39 | }; | |
40 | ||
41 | /* clock derived from 24 MHz osc clk */ | |
42 | /* pll1 configuration structure */ | |
43 | static struct pll_clk_config pll1_config = { | |
44 | .mode_reg = PLL1_CTR, | |
45 | .cfg_reg = PLL1_FRQ, | |
46 | }; | |
47 | ||
48 | /* PLL1 clock */ | |
49 | static struct clk pll1_clk = { | |
50 | .pclk = &osc_24m_clk, | |
51 | .en_reg = PLL1_CTR, | |
52 | .en_reg_bit = PLL_ENABLE, | |
53 | .recalc = &pll1_clk_recalc, | |
54 | .private_data = &pll1_config, | |
55 | }; | |
56 | ||
57 | /* PLL3 48 MHz clock */ | |
58 | static struct clk pll3_48m_clk = { | |
59 | .flags = ALWAYS_ENABLED, | |
60 | .pclk = &osc_24m_clk, | |
61 | .rate = 48000000, | |
62 | }; | |
63 | ||
64 | /* watch dog timer clock */ | |
65 | static struct clk wdt_clk = { | |
66 | .flags = ALWAYS_ENABLED, | |
67 | .pclk = &osc_24m_clk, | |
68 | .recalc = &follow_parent, | |
69 | }; | |
70 | ||
71 | /* clock derived from pll1 clk */ | |
72 | /* cpu clock */ | |
73 | static struct clk cpu_clk = { | |
74 | .flags = ALWAYS_ENABLED, | |
75 | .pclk = &pll1_clk, | |
76 | .recalc = &follow_parent, | |
77 | }; | |
78 | ||
79 | /* ahb configuration structure */ | |
80 | static struct bus_clk_config ahb_config = { | |
81 | .reg = CORE_CLK_CFG, | |
82 | .mask = PLL_HCLK_RATIO_MASK, | |
83 | .shift = PLL_HCLK_RATIO_SHIFT, | |
84 | }; | |
85 | ||
86 | /* ahb clock */ | |
87 | static struct clk ahb_clk = { | |
88 | .flags = ALWAYS_ENABLED, | |
89 | .pclk = &pll1_clk, | |
90 | .recalc = &bus_clk_recalc, | |
91 | .private_data = &ahb_config, | |
92 | }; | |
93 | ||
94 | /* uart configurations */ | |
95 | static struct aux_clk_config uart_config = { | |
96 | .synth_reg = UART_CLK_SYNT, | |
97 | }; | |
98 | ||
99 | /* uart parents */ | |
100 | static struct pclk_info uart_pclk_info[] = { | |
101 | { | |
102 | .pclk = &pll1_clk, | |
103 | .pclk_mask = AUX_CLK_PLL1_MASK, | |
104 | .scalable = 1, | |
105 | }, { | |
106 | .pclk = &pll3_48m_clk, | |
107 | .pclk_mask = AUX_CLK_PLL3_MASK, | |
108 | .scalable = 0, | |
109 | }, | |
110 | }; | |
111 | ||
112 | /* uart parent select structure */ | |
113 | static struct pclk_sel uart_pclk_sel = { | |
114 | .pclk_info = uart_pclk_info, | |
115 | .pclk_count = ARRAY_SIZE(uart_pclk_info), | |
116 | .pclk_sel_reg = PERIP_CLK_CFG, | |
117 | .pclk_sel_mask = UART_CLK_MASK, | |
118 | }; | |
119 | ||
120 | /* uart clock */ | |
121 | static struct clk uart_clk = { | |
122 | .en_reg = PERIP1_CLK_ENB, | |
123 | .en_reg_bit = UART_CLK_ENB, | |
124 | .pclk_sel = &uart_pclk_sel, | |
125 | .pclk_sel_shift = UART_CLK_SHIFT, | |
126 | .recalc = &aux_clk_recalc, | |
127 | .private_data = &uart_config, | |
128 | }; | |
129 | ||
130 | /* firda configurations */ | |
131 | static struct aux_clk_config firda_config = { | |
132 | .synth_reg = FIRDA_CLK_SYNT, | |
133 | }; | |
134 | ||
135 | /* firda parents */ | |
136 | static struct pclk_info firda_pclk_info[] = { | |
137 | { | |
138 | .pclk = &pll1_clk, | |
139 | .pclk_mask = AUX_CLK_PLL1_MASK, | |
140 | .scalable = 1, | |
141 | }, { | |
142 | .pclk = &pll3_48m_clk, | |
143 | .pclk_mask = AUX_CLK_PLL3_MASK, | |
144 | .scalable = 0, | |
145 | }, | |
146 | }; | |
147 | ||
148 | /* firda parent select structure */ | |
149 | static struct pclk_sel firda_pclk_sel = { | |
150 | .pclk_info = firda_pclk_info, | |
151 | .pclk_count = ARRAY_SIZE(firda_pclk_info), | |
152 | .pclk_sel_reg = PERIP_CLK_CFG, | |
153 | .pclk_sel_mask = FIRDA_CLK_MASK, | |
154 | }; | |
155 | ||
156 | /* firda clock */ | |
157 | static struct clk firda_clk = { | |
158 | .en_reg = PERIP1_CLK_ENB, | |
159 | .en_reg_bit = FIRDA_CLK_ENB, | |
160 | .pclk_sel = &firda_pclk_sel, | |
161 | .pclk_sel_shift = FIRDA_CLK_SHIFT, | |
162 | .recalc = &aux_clk_recalc, | |
163 | .private_data = &firda_config, | |
164 | }; | |
165 | ||
166 | /* gpt parents */ | |
167 | static struct pclk_info gpt_pclk_info[] = { | |
168 | { | |
169 | .pclk = &pll1_clk, | |
170 | .pclk_mask = AUX_CLK_PLL1_MASK, | |
171 | .scalable = 1, | |
172 | }, { | |
173 | .pclk = &pll3_48m_clk, | |
174 | .pclk_mask = AUX_CLK_PLL3_MASK, | |
175 | .scalable = 0, | |
176 | }, | |
177 | }; | |
178 | ||
179 | /* gpt parent select structure */ | |
180 | static struct pclk_sel gpt_pclk_sel = { | |
181 | .pclk_info = gpt_pclk_info, | |
182 | .pclk_count = ARRAY_SIZE(gpt_pclk_info), | |
183 | .pclk_sel_reg = PERIP_CLK_CFG, | |
184 | .pclk_sel_mask = GPT_CLK_MASK, | |
185 | }; | |
186 | ||
187 | /* gpt0 configurations */ | |
188 | static struct aux_clk_config gpt0_config = { | |
189 | .synth_reg = PRSC1_CLK_CFG, | |
190 | }; | |
191 | ||
192 | /* gpt0 timer clock */ | |
193 | static struct clk gpt0_clk = { | |
194 | .flags = ALWAYS_ENABLED, | |
195 | .pclk_sel = &gpt_pclk_sel, | |
196 | .pclk_sel_shift = GPT0_CLK_SHIFT, | |
197 | .recalc = &gpt_clk_recalc, | |
198 | .private_data = &gpt0_config, | |
199 | }; | |
200 | ||
201 | /* gpt1 configurations */ | |
202 | static struct aux_clk_config gpt1_config = { | |
203 | .synth_reg = PRSC2_CLK_CFG, | |
204 | }; | |
205 | ||
206 | /* gpt1 timer clock */ | |
207 | static struct clk gpt1_clk = { | |
208 | .en_reg = PERIP1_CLK_ENB, | |
209 | .en_reg_bit = GPT1_CLK_ENB, | |
210 | .pclk_sel = &gpt_pclk_sel, | |
211 | .pclk_sel_shift = GPT1_CLK_SHIFT, | |
212 | .recalc = &gpt_clk_recalc, | |
213 | .private_data = &gpt1_config, | |
214 | }; | |
215 | ||
216 | /* gpt2 configurations */ | |
217 | static struct aux_clk_config gpt2_config = { | |
218 | .synth_reg = PRSC3_CLK_CFG, | |
219 | }; | |
220 | ||
221 | /* gpt2 timer clock */ | |
222 | static struct clk gpt2_clk = { | |
223 | .en_reg = PERIP1_CLK_ENB, | |
224 | .en_reg_bit = GPT2_CLK_ENB, | |
225 | .pclk_sel = &gpt_pclk_sel, | |
226 | .pclk_sel_shift = GPT2_CLK_SHIFT, | |
227 | .recalc = &gpt_clk_recalc, | |
228 | .private_data = &gpt2_config, | |
229 | }; | |
230 | ||
231 | /* clock derived from pll3 clk */ | |
232 | /* usbh clock */ | |
233 | static struct clk usbh_clk = { | |
234 | .pclk = &pll3_48m_clk, | |
235 | .en_reg = PERIP1_CLK_ENB, | |
236 | .en_reg_bit = USBH_CLK_ENB, | |
237 | .recalc = &follow_parent, | |
238 | }; | |
239 | ||
240 | /* usbd clock */ | |
241 | static struct clk usbd_clk = { | |
242 | .pclk = &pll3_48m_clk, | |
243 | .en_reg = PERIP1_CLK_ENB, | |
244 | .en_reg_bit = USBD_CLK_ENB, | |
245 | .recalc = &follow_parent, | |
246 | }; | |
247 | ||
248 | /* clcd clock */ | |
249 | static struct clk clcd_clk = { | |
250 | .flags = ALWAYS_ENABLED, | |
251 | .pclk = &pll3_48m_clk, | |
252 | .recalc = &follow_parent, | |
253 | }; | |
254 | ||
255 | /* clock derived from ahb clk */ | |
256 | /* apb configuration structure */ | |
257 | static struct bus_clk_config apb_config = { | |
258 | .reg = CORE_CLK_CFG, | |
259 | .mask = HCLK_PCLK_RATIO_MASK, | |
260 | .shift = HCLK_PCLK_RATIO_SHIFT, | |
261 | }; | |
262 | ||
263 | /* apb clock */ | |
264 | static struct clk apb_clk = { | |
265 | .flags = ALWAYS_ENABLED, | |
266 | .pclk = &ahb_clk, | |
267 | .recalc = &bus_clk_recalc, | |
268 | .private_data = &apb_config, | |
269 | }; | |
270 | ||
271 | /* i2c clock */ | |
272 | static struct clk i2c_clk = { | |
273 | .pclk = &ahb_clk, | |
274 | .en_reg = PERIP1_CLK_ENB, | |
275 | .en_reg_bit = I2C_CLK_ENB, | |
276 | .recalc = &follow_parent, | |
277 | }; | |
278 | ||
279 | /* dma clock */ | |
280 | static struct clk dma_clk = { | |
281 | .pclk = &ahb_clk, | |
282 | .en_reg = PERIP1_CLK_ENB, | |
283 | .en_reg_bit = DMA_CLK_ENB, | |
284 | .recalc = &follow_parent, | |
285 | }; | |
286 | ||
287 | /* jpeg clock */ | |
288 | static struct clk jpeg_clk = { | |
289 | .pclk = &ahb_clk, | |
290 | .en_reg = PERIP1_CLK_ENB, | |
291 | .en_reg_bit = JPEG_CLK_ENB, | |
292 | .recalc = &follow_parent, | |
293 | }; | |
294 | ||
295 | /* gmac clock */ | |
296 | static struct clk gmac_clk = { | |
297 | .pclk = &ahb_clk, | |
298 | .en_reg = PERIP1_CLK_ENB, | |
299 | .en_reg_bit = GMAC_CLK_ENB, | |
300 | .recalc = &follow_parent, | |
301 | }; | |
302 | ||
303 | /* smi clock */ | |
304 | static struct clk smi_clk = { | |
305 | .pclk = &ahb_clk, | |
306 | .en_reg = PERIP1_CLK_ENB, | |
307 | .en_reg_bit = SMI_CLK_ENB, | |
308 | .recalc = &follow_parent, | |
309 | }; | |
310 | ||
311 | /* c3 clock */ | |
312 | static struct clk c3_clk = { | |
313 | .pclk = &ahb_clk, | |
314 | .en_reg = PERIP1_CLK_ENB, | |
315 | .en_reg_bit = C3_CLK_ENB, | |
316 | .recalc = &follow_parent, | |
317 | }; | |
318 | ||
319 | /* clock derived from apb clk */ | |
320 | /* adc clock */ | |
321 | static struct clk adc_clk = { | |
322 | .pclk = &apb_clk, | |
323 | .en_reg = PERIP1_CLK_ENB, | |
324 | .en_reg_bit = ADC_CLK_ENB, | |
325 | .recalc = &follow_parent, | |
326 | }; | |
327 | ||
328 | /* ssp clock */ | |
329 | static struct clk ssp_clk = { | |
330 | .pclk = &apb_clk, | |
331 | .en_reg = PERIP1_CLK_ENB, | |
332 | .en_reg_bit = SSP_CLK_ENB, | |
333 | .recalc = &follow_parent, | |
334 | }; | |
335 | ||
336 | /* gpio clock */ | |
337 | static struct clk gpio_clk = { | |
338 | .pclk = &apb_clk, | |
339 | .en_reg = PERIP1_CLK_ENB, | |
340 | .en_reg_bit = GPIO_CLK_ENB, | |
341 | .recalc = &follow_parent, | |
342 | }; | |
343 | ||
3126c7bc RK |
344 | static struct clk dummy_apb_pclk; |
345 | ||
8c0236fc VK |
346 | /* array of all spear 3xx clock lookups */ |
347 | static struct clk_lookup spear_clk_lookups[] = { | |
3126c7bc | 348 | { .con_id = "apb_pclk", .clk = &dummy_apb_pclk}, |
8c0236fc VK |
349 | /* root clks */ |
350 | { .con_id = "osc_32k_clk", .clk = &osc_32k_clk}, | |
351 | { .con_id = "osc_24m_clk", .clk = &osc_24m_clk}, | |
352 | /* clock derived from 32 KHz osc clk */ | |
353 | { .dev_id = "rtc", .clk = &rtc_clk}, | |
354 | /* clock derived from 24 MHz osc clk */ | |
355 | { .con_id = "pll1_clk", .clk = &pll1_clk}, | |
356 | { .con_id = "pll3_48m_clk", .clk = &pll3_48m_clk}, | |
357 | { .dev_id = "wdt", .clk = &wdt_clk}, | |
358 | /* clock derived from pll1 clk */ | |
359 | { .con_id = "cpu_clk", .clk = &cpu_clk}, | |
360 | { .con_id = "ahb_clk", .clk = &ahb_clk}, | |
361 | { .dev_id = "uart", .clk = &uart_clk}, | |
362 | { .dev_id = "firda", .clk = &firda_clk}, | |
363 | { .dev_id = "gpt0", .clk = &gpt0_clk}, | |
364 | { .dev_id = "gpt1", .clk = &gpt1_clk}, | |
365 | { .dev_id = "gpt2", .clk = &gpt2_clk}, | |
366 | /* clock derived from pll3 clk */ | |
367 | { .dev_id = "usbh", .clk = &usbh_clk}, | |
368 | { .dev_id = "usbd", .clk = &usbd_clk}, | |
369 | { .dev_id = "clcd", .clk = &clcd_clk}, | |
370 | /* clock derived from ahb clk */ | |
371 | { .con_id = "apb_clk", .clk = &apb_clk}, | |
372 | { .dev_id = "i2c", .clk = &i2c_clk}, | |
373 | { .dev_id = "dma", .clk = &dma_clk}, | |
374 | { .dev_id = "jpeg", .clk = &jpeg_clk}, | |
375 | { .dev_id = "gmac", .clk = &gmac_clk}, | |
376 | { .dev_id = "smi", .clk = &smi_clk}, | |
377 | { .dev_id = "c3", .clk = &c3_clk}, | |
378 | /* clock derived from apb clk */ | |
379 | { .dev_id = "adc", .clk = &adc_clk}, | |
380 | { .dev_id = "ssp", .clk = &ssp_clk}, | |
381 | { .dev_id = "gpio", .clk = &gpio_clk}, | |
382 | }; | |
383 | ||
384 | void __init clk_init(void) | |
385 | { | |
386 | int i; | |
387 | ||
388 | for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++) | |
389 | clk_register(&spear_clk_lookups[i]); | |
390 | ||
391 | recalc_root_clocks(); | |
392 | } |