projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| 97991657 MD |
1 | /* |
| 2 | * sh7372 lowlevel sleep code for "Core Standby Mode" | |
| 3 | * | |
| 4 | * Copyright (C) 2011 Magnus Damm | |
| 5 | * | |
| 6 | * In "Core Standby Mode" the ARM core is off, but L2 cache is still on | |
| 7 | * | |
| 8 | * Based on mach-omap2/sleep34xx.S | |
| 9 | * | |
| 10 | * (C) Copyright 2007 Texas Instruments | |
| 11 | * Karthik Dasu <karthik-dp@ti.com> | |
| 12 | * | |
| 13 | * (C) Copyright 2004 Texas Instruments, <www.ti.com> | |
| 14 | * Richard Woodruff <r-woodruff2@ti.com> | |
| 15 | * | |
| 16 | * This program is free software; you can redistribute it and/or | |
| 17 | * modify it under the terms of the GNU General Public License as | |
| 18 | * published by the Free Software Foundation; either version 2 of | |
| 19 | * the License, or (at your option) any later version. | |
| 20 | * | |
| 21 | * This program is distributed in the hope that it will be useful, | |
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the | |
| 24 | * GNU General Public License for more details. | |
| 25 | * | |
| 26 | * You should have received a copy of the GNU General Public License | |
| 27 | * along with this program; if not, write to the Free Software | |
| 28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 29 | * MA 02111-1307 USA | |
| 30 | */ | |
| 31 | ||
| 32 | #include <linux/linkage.h> | |
| 06b84166 MD |
33 | #include <linux/init.h> |
| 34 | #include <asm/memory.h> | |
| 97991657 MD |
35 | #include <asm/assembler.h> |
| 36 | ||
| a0089bd6 | 37 | #if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE) |
| 97991657 MD |
38 | .align 12 |
| 39 | .text | |
| cf33835c MD |
40 | .global sh7372_resume_core_standby_a3sm |
| 41 | sh7372_resume_core_standby_a3sm: | |
| 06b84166 MD |
42 | ldr pc, 1f |
| 43 | 1: .long cpu_resume - PAGE_OFFSET + PLAT_PHYS_OFFSET | |
| cf33835c MD |
44 | |
| 45 | .global sh7372_do_idle_a3sm | |
| 46 | sh7372_do_idle_a3sm: | |
| 47 | /* | |
| 48 | * Clear the SCTLR.C bit to prevent further data cache | |
| 49 | * allocation. Clearing SCTLR.C would make all the data accesses | |
| 50 | * strongly ordered and would not hit the cache. | |
| 51 | */ | |
| 52 | mrc p15, 0, r0, c1, c0, 0 | |
| 53 | bic r0, r0, #(1 << 2) @ Disable the C bit | |
| 54 | mcr p15, 0, r0, c1, c0, 0 | |
| 55 | isb | |
| 56 | ||
| 57 | /* disable L2 cache in the aux control register */ | |
| 58 | mrc p15, 0, r10, c1, c0, 1 | |
| 59 | bic r10, r10, #2 | |
| 60 | mcr p15, 0, r10, c1, c0, 1 | |
| 61 | ||
| 62 | /* | |
| 63 | * Invalidate data cache again. | |
| 64 | */ | |
| 65 | ldr r1, kernel_flush | |
| 66 | blx r1 | |
| 67 | /* | |
| 68 | * The kernel doesn't interwork: v7_flush_dcache_all in particluar will | |
| 69 | * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled. | |
| 70 | * This sequence switches back to ARM. Note that .align may insert a | |
| 71 | * nop: bx pc needs to be word-aligned in order to work. | |
| 72 | */ | |
| 73 | THUMB( .thumb ) | |
| 74 | THUMB( .align ) | |
| 75 | THUMB( bx pc ) | |
| 76 | THUMB( nop ) | |
| 77 | .arm | |
| 78 | ||
| 79 | /* Data memory barrier and Data sync barrier */ | |
| 80 | dsb | |
| 81 | dmb | |
| 82 | ||
| 83 | #define SPDCR 0xe6180008 | |
| 84 | #define A3SM (1 << 12) | |
| 85 | ||
| 86 | /* A3SM power down */ | |
| 87 | ldr r0, =SPDCR | |
| 88 | ldr r1, =A3SM | |
| 89 | str r1, [r0] | |
| 90 | 1: | |
| 91 | b 1b | |
| 92 | ||
| 93 | kernel_flush: | |
| 94 | .word v7_flush_dcache_all | |
| a0089bd6 | 95 | #endif |