[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-shmobile / headsmp-scu.S

/*
 * Shared SCU setup for mach-shmobile
 *
 * Copyright (C) 2012 Bastian Hecht
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/memory.h>

	__CPUINIT
/*
 * Reset vector for secondary CPUs.
 *
 * First we turn on L1 cache coherency for our CPU. Then we jump to
 * shmobile_invalidate_start that invalidates the cache and hands over control
 * to the common ARM startup code.
 * This function will be mapped to address 0 by the SBAR register.
 * A normal branch is out of range here so we need a long jump. We jump to
 * the physical address as the MMU is still turned off.
 */
	.align	12
ENTRY(shmobile_secondary_vector_scu)
	mrc     p15, 0, r0, c0, c0, 5	@ read MIPDR
	and	r0, r0, #3		@ mask out cpu ID
	lsl	r0, r0, #3		@ we will shift by cpu_id * 8 bits
	ldr	r1, 2f
	ldr	r1, [r1]		@ SCU base address
	ldr	r2, [r1, #8]		@ SCU Power Status Register
	mov	r3, #3
	bic	r2, r2, r3, lsl r0	@ Clear bits of our CPU (Run Mode)
	str	r2, [r1, #8]		@ write back

	ldr	pc, 1f
1:	.long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET
2:	.long shmobile_scu_base - PAGE_OFFSET + PLAT_PHYS_OFFSET
ENDPROC(shmobile_secondary_vector_scu)

	.text
	.globl	shmobile_scu_base
shmobile_scu_base:
	.space	4
Commit	Line	Data
ec0d84a8 MD	1	/*
	2	* Shared SCU setup for mach-shmobile
	3	*
	4	* Copyright (C) 2012 Bastian Hecht
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation; either version 2 of
	9	* the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	19	* MA 02111-1307 USA
	20	*/
	21
	22	#include <linux/linkage.h>
	23	#include <linux/init.h>
	24	#include <asm/memory.h>
	25
	26	__CPUINIT
	27	/*
	28	* Reset vector for secondary CPUs.
	29	*
	30	* First we turn on L1 cache coherency for our CPU. Then we jump to
	31	* shmobile_invalidate_start that invalidates the cache and hands over control
	32	* to the common ARM startup code.
	33	* This function will be mapped to address 0 by the SBAR register.
	34	* A normal branch is out of range here so we need a long jump. We jump to
	35	* the physical address as the MMU is still turned off.
	36	*/
	37	.align 12
	38	ENTRY(shmobile_secondary_vector_scu)
	39	mrc p15, 0, r0, c0, c0, 5 @ read MIPDR
	40	and r0, r0, #3 @ mask out cpu ID
	41	lsl r0, r0, #3 @ we will shift by cpu_id * 8 bits
73e57098	42	ldr r1, 2f
4c822845	43	ldr r1, [r1] @ SCU base address
ec0d84a8 MD	44	ldr r2, [r1, #8] @ SCU Power Status Register
	45	mov r3, #3
	46	bic r2, r2, r3, lsl r0 @ Clear bits of our CPU (Run Mode)
	47	str r2, [r1, #8] @ write back
	48
	49	ldr pc, 1f
	50	1: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET
73e57098	51	2: .long shmobile_scu_base - PAGE_OFFSET + PLAT_PHYS_OFFSET
ec0d84a8	52	ENDPROC(shmobile_secondary_vector_scu)
4c822845 MD	53
	54	.text
	55	.globl shmobile_scu_base
	56	shmobile_scu_base:
	57	.space 4