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ARM: shmobile: force enable of r8a7790 arch timer
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-shmobile / board-ap4evb.c
CommitLineData
2b7eda63
MD		 1/*
2 * AP4EVB board support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
8eda2f21 20#include <linux/clk.h>
2b7eda63
MD		 21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/platform_device.h>
26#include <linux/delay.h>
410d878b 27#include <linux/mfd/tmio.h>
341291a6 28#include <linux/mmc/host.h>
17e75d82 29#include <linux/mmc/sh_mobile_sdhi.h>
2b7eda63
MD		 30#include <linux/mtd/mtd.h>
31#include <linux/mtd/partitions.h>
32#include <linux/mtd/physmap.h>
c8ee3d4b 33#include <linux/mmc/sh_mmcif.h>
91cf5082
KM		 34#include <linux/i2c.h>
35#include <linux/i2c/tsc2007.h>
2b7eda63 36#include <linux/io.h>
8778b8f4
GL		 37#include <linux/regulator/fixed.h>
38#include <linux/regulator/machine.h>
1b7e0677 39#include <linux/smsc911x.h>
cb9215e1
KM		 40#include <linux/sh_intc.h>
41#include <linux/sh_clk.h>
1b7e0677 42#include <linux/gpio.h>
17ccb834 43#include <linux/input.h>
2863e935 44#include <linux/leds.h>
17ccb834 45#include <linux/input/sh_keysc.h>
fb54d268 46#include <linux/usb/r8a66597.h>
b5e8d269 47#include <linux/pm_clock.h>
9b742024 48#include <linux/dma-mapping.h>
8eda2f21 49
1a0b1eac
GL		 50#include <media/sh_mobile_ceu.h>
51#include <media/sh_mobile_csi2.h>
52#include <media/soc_camera.h>
53
cb9215e1 54#include <sound/sh_fsi.h>
af8a2fe1 55#include <sound/simple_card.h>
cb9215e1 56
dfbcdf64 57#include <video/sh_mobile_hdmi.h>
8eda2f21
GL		 58#include <video/sh_mobile_lcdc.h>
59#include <video/sh_mipi_dsi.h>
60
2b7eda63 61#include <mach/common.h>
8eda2f21 62#include <mach/irqs.h>
1b7e0677 63#include <mach/sh7372.h>
8eda2f21 64
2b7eda63
MD		 65#include <asm/mach-types.h>
66#include <asm/mach/arch.h>
3d09fbcd 67#include <asm/setup.h>
2b7eda63 68
66791859
RH		 69#include "sh-gpio.h"
70
02624a17
KM		 71/*
72 * Address Interface BusWidth note
73 * ------------------------------------------------------------------
74 * 0x0000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = ON
75 * 0x0800_0000 user area -
76 * 0x1000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = OFF
77 * 0x1400_0000 Ether (LAN9220) 16bit
78 * 0x1600_0000 user area - cannot use with NAND
79 * 0x1800_0000 user area -
80 * 0x1A00_0000 -
81 * 0x4000_0000 LPDDR2-SDRAM (POP) 32bit
82 */
83
84/*
85 * NOR Flash ROM
86 *
87 * SW1 | SW2 | SW7 | NOR Flash ROM
88 * bit1 | bit1 bit2 | bit1 | Memory allocation
89 * ------+------------+------+------------------
90 * OFF | ON OFF | ON | Area 0
91 * OFF | ON OFF | OFF | Area 4
92 */
93
94/*
95 * NAND Flash ROM
96 *
97 * SW1 | SW2 | SW7 | NAND Flash ROM
98 * bit1 | bit1 bit2 | bit2 | Memory allocation
99 * ------+------------+------+------------------
100 * OFF | ON OFF | ON | FCE 0
101 * OFF | ON OFF | OFF | FCE 1
102 */
103
104/*
105 * SMSC 9220
106 *
107 * SW1 SMSC 9220
108 * -----------------------
109 * ON access disable
110 * OFF access enable
111 */
112
17ccb834 113/*
dda128dc 114 * LCD / IRQ / KEYSC / IrDA
17ccb834 115 *
9fa1b7fe
KM		 116 * IRQ = IRQ26 (TS), IRQ27 (VIO), IRQ28 (QHD-TouchScreen)
117 * LCD = 2nd LCDC (WVGA)
dda128dc
KM		 118 *
119 * | SW43 |
120 * SW3 | ON | OFF |
121 * -------------+-----------------------+---------------+
122 * ON | KEY / IrDA | LCD |
123 * OFF | KEY / IrDA / IRQ | IRQ |
9fa1b7fe
KM		 124 *
125 *
126 * QHD / WVGA display
127 *
128 * You can choice display type on menuconfig.
129 * Then, check above dip-switch.
17ccb834
KM		 130 */
131
fb54d268
KM		 132/*
133 * USB
134 *
135 * J7 : 1-2 MAX3355E VBUS
136 * 2-3 DC 5.0V
137 *
138 * S39: bit2: off
139 */
140
cb9215e1
KM		 141/*
142 * FSI/FSMI
143 *
144 * SW41 : ON : SH-Mobile AP4 Audio Mode
145 * : OFF : Bluetooth Audio Mode
d2b0812d
KM		 146 *
147 * it needs amixer settings for playing
148 *
149 * amixer set "Headphone Enable" on
cb9215e1
KM		 150 */
151
c8ee3d4b 152/*
d3d03e48 153 * MMC0/SDHI1 (CN7)
c8ee3d4b 154 *
d3d03e48
KM		 155 * J22 : select card voltage
156 * 1-2 pin : 1.8v
157 * 2-3 pin : 3.3v
158 *
159 * SW1 | SW33
160 * | bit1 | bit2 | bit3 | bit4
161 * ------------+------+------+------+-------
162 * MMC0 OFF | OFF | ON | ON | X
163 * SDHI1 OFF | ON | X | OFF | ON
164 *
165 * voltage lebel
166 * CN7 : 1.8v
167 * CN12: 3.3v
c8ee3d4b
KM		 168 */
169
8778b8f4
GL		 170/* Dummy supplies, where voltage doesn't matter */
171static struct regulator_consumer_supply fixed1v8_power_consumers[] =
172{
173 /* J22 default position: 1.8V */
174 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
175 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
176 REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"),
177 REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"),
178};
179
180static struct regulator_consumer_supply fixed3v3_power_consumers[] =
181{
182 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
183 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
184};
185
186static struct regulator_consumer_supply dummy_supplies[] = {
187 REGULATOR_SUPPLY("vddvario", "smsc911x"),
188 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
189};
190
1b7e0677 191/* MTD */
2b7eda63
MD		 192static struct mtd_partition nor_flash_partitions[] = {
193 {
194 .name = "loader",
195 .offset = 0x00000000,
196 .size = 512 * 1024,
2e351ec6 197 .mask_flags = MTD_WRITEABLE,
2b7eda63
MD		 198 },
199 {
200 .name = "bootenv",
201 .offset = MTDPART_OFS_APPEND,
202 .size = 512 * 1024,
2e351ec6 203 .mask_flags = MTD_WRITEABLE,
2b7eda63
MD		 204 },
205 {
206 .name = "kernel_ro",
207 .offset = MTDPART_OFS_APPEND,
208 .size = 8 * 1024 * 1024,
209 .mask_flags = MTD_WRITEABLE,
210 },
211 {
212 .name = "kernel",
213 .offset = MTDPART_OFS_APPEND,
214 .size = 8 * 1024 * 1024,
215 },
216 {
217 .name = "data",
218 .offset = MTDPART_OFS_APPEND,
219 .size = MTDPART_SIZ_FULL,
220 },
221};
222
223static struct physmap_flash_data nor_flash_data = {
224 .width = 2,
225 .parts = nor_flash_partitions,
226 .nr_parts = ARRAY_SIZE(nor_flash_partitions),
227};
228
229static struct resource nor_flash_resources[] = {
230 [0] = {
832217da 231 .start = 0x20000000, /* CS0 shadow instead of regular CS0 */
8e6a4675 232 .end = 0x28000000 - 1, /* needed by USB MASK ROM boot */
2b7eda63
MD		 233 .flags = IORESOURCE_MEM,
234 }
235};
236
237static struct platform_device nor_flash_device = {
238 .name = "physmap-flash",
239 .dev = {
240 .platform_data = &nor_flash_data,
241 },
242 .num_resources = ARRAY_SIZE(nor_flash_resources),
243 .resource = nor_flash_resources,
244};
245
1b7e0677
KM		 246/* SMSC 9220 */
247static struct resource smc911x_resources[] = {
248 {
249 .start = 0x14000000,
250 .end = 0x16000000 - 1,
251 .flags = IORESOURCE_MEM,
252 }, {
33c9607a 253 .start = evt2irq(0x02c0) /* IRQ6A */,
1b7e0677
KM		 254 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
255 },
256};
257
258static struct smsc911x_platform_config smsc911x_info = {
259 .flags = SMSC911X_USE_16BIT | SMSC911X_SAVE_MAC_ADDRESS,
260 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
261 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
262};
263
264static struct platform_device smc911x_device = {
265 .name = "smsc911x",
266 .id = -1,
267 .num_resources = ARRAY_SIZE(smc911x_resources),
268 .resource = smc911x_resources,
269 .dev = {
270 .platform_data = &smsc911x_info,
271 },
272};
2b7eda63 273
68accd73
AH		 274/*
275 * The card detect pin of the top SD/MMC slot (CN7) is active low and is
276 * connected to GPIO A22 of SH7372 (GPIO_PORT41).
277 */
278static int slot_cn7_get_cd(struct platform_device *pdev)
279{
ceb50f33 280 return !gpio_get_value(GPIO_PORT41);
68accd73 281}
1c7fcbed
DHG		 282/* MERAM */
283static struct sh_mobile_meram_info meram_info = {
284 .addr_mode = SH_MOBILE_MERAM_MODE1,
285};
286
287static struct resource meram_resources[] = {
288 [0] = {
e71504d5
LP		 289 .name = "regs",
290 .start = 0xe8000000,
291 .end = 0xe807ffff,
292 .flags = IORESOURCE_MEM,
293 },
294 [1] = {
295 .name = "meram",
296 .start = 0xe8080000,
297 .end = 0xe81fffff,
298 .flags = IORESOURCE_MEM,
1c7fcbed
DHG		 299 },
300};
301
302static struct platform_device meram_device = {
303 .name = "sh_mobile_meram",
304 .id = 0,
305 .num_resources = ARRAY_SIZE(meram_resources),
306 .resource = meram_resources,
307 .dev = {
308 .platform_data = &meram_info,
309 },
310};
68accd73 311
c8ee3d4b
KM		 312/* SH_MMCIF */
313static struct resource sh_mmcif_resources[] = {
314 [0] = {
0fb0834b 315 .name = "MMCIF",
c8ee3d4b
KM		 316 .start = 0xE6BD0000,
317 .end = 0xE6BD00FF,
318 .flags = IORESOURCE_MEM,
319 },
320 [1] = {
321 /* MMC ERR */
8d569341 322 .start = evt2irq(0x1ac0),
c8ee3d4b
KM		 323 .flags = IORESOURCE_IRQ,
324 },
325 [2] = {
326 /* MMC NOR */
8d569341 327 .start = evt2irq(0x1ae0),
c8ee3d4b
KM		 328 .flags = IORESOURCE_IRQ,
329 },
330};
331
bb04e197 332static struct sh_mmcif_plat_data sh_mmcif_plat = {
c8ee3d4b
KM		 333 .sup_pclk = 0,
334 .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
335 .caps = MMC_CAP_4_BIT_DATA |
336 MMC_CAP_8_BIT_DATA |
337 MMC_CAP_NEEDS_POLL,
68accd73 338 .get_cd = slot_cn7_get_cd,
d5bb386d
GL		 339 .slave_id_tx = SHDMA_SLAVE_MMCIF_TX,
340 .slave_id_rx = SHDMA_SLAVE_MMCIF_RX,
c8ee3d4b
KM		 341};
342
343static struct platform_device sh_mmcif_device = {
344 .name = "sh_mmcif",
345 .id = 0,
346 .dev = {
347 .dma_mask = NULL,
348 .coherent_dma_mask = 0xffffffff,
349 .platform_data = &sh_mmcif_plat,
350 },
351 .num_resources = ARRAY_SIZE(sh_mmcif_resources),
352 .resource = sh_mmcif_resources,
353};
354
3a14d039 355/* SDHI0 */
69bf6f45 356static struct sh_mobile_sdhi_info sdhi0_info = {
341291a6
GL		 357 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
358 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
330e4e71 359 .tmio_caps = MMC_CAP_SDIO_IRQ,
69bf6f45
GL		 360};
361
3a14d039
MD		 362static struct resource sdhi0_resources[] = {
363 [0] = {
364 .name = "SDHI0",
365 .start = 0xe6850000,
31d31fe7 366 .end = 0xe68500ff,
3a14d039
MD		 367 .flags = IORESOURCE_MEM,
368 },
369 [1] = {
2007aea1
SH		 370 .start = evt2irq(0x0e00) /* SDHI0_SDHI0I0 */,
371 .flags = IORESOURCE_IRQ,
372 },
373 [2] = {
374 .start = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */,
375 .flags = IORESOURCE_IRQ,
376 },
377 [3] = {
378 .start = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */,
379 .flags = IORESOURCE_IRQ,
3a14d039
MD		 380 },
381};
382
383static struct platform_device sdhi0_device = {
384 .name = "sh_mobile_sdhi",
385 .num_resources = ARRAY_SIZE(sdhi0_resources),
386 .resource = sdhi0_resources,
387 .id = 0,
69bf6f45
GL		 388 .dev = {
389 .platform_data = &sdhi0_info,
390 },
3a14d039
MD		 391};
392
341291a6
GL		 393/* SDHI1 */
394static struct sh_mobile_sdhi_info sdhi1_info = {
395 .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX,
396 .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
397 .tmio_ocr_mask = MMC_VDD_165_195,
410d878b 398 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE,
330e4e71 399 .tmio_caps = MMC_CAP_NEEDS_POLL | MMC_CAP_SDIO_IRQ,
68accd73 400 .get_cd = slot_cn7_get_cd,
341291a6
GL		 401};
402
403static struct resource sdhi1_resources[] = {
404 [0] = {
405 .name = "SDHI1",
406 .start = 0xe6860000,
31d31fe7 407 .end = 0xe68600ff,
341291a6
GL		 408 .flags = IORESOURCE_MEM,
409 },
410 [1] = {
2007aea1
SH		 411 .start = evt2irq(0x0e80), /* SDHI1_SDHI1I0 */
412 .flags = IORESOURCE_IRQ,
413 },
414 [2] = {
415 .start = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */
416 .flags = IORESOURCE_IRQ,
417 },
418 [3] = {
419 .start = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */
420 .flags = IORESOURCE_IRQ,
341291a6
GL		 421 },
422};
423
424static struct platform_device sdhi1_device = {
425 .name = "sh_mobile_sdhi",
426 .num_resources = ARRAY_SIZE(sdhi1_resources),
427 .resource = sdhi1_resources,
428 .id = 1,
429 .dev = {
430 .platform_data = &sdhi1_info,
431 },
432};
433
fb54d268 434/* USB1 */
bb04e197 435static void usb1_host_port_power(int port, int power)
fb54d268
KM		 436{
437 if (!power) /* only power-on supported for now */
438 return;
439
440 /* set VBOUT/PWEN and EXTLP1 in DVSTCTR */
0a4b04dc 441 __raw_writew(__raw_readw(IOMEM(0xE68B0008)) | 0x600, IOMEM(0xE68B0008));
fb54d268
KM		 442}
443
444static struct r8a66597_platdata usb1_host_data = {
445 .on_chip = 1,
446 .port_power = usb1_host_port_power,
447};
448
449static struct resource usb1_host_resources[] = {
450 [0] = {
451 .name = "USBHS",
452 .start = 0xE68B0000,
453 .end = 0xE68B00E6 - 1,
454 .flags = IORESOURCE_MEM,
455 },
456 [1] = {
33c9607a 457 .start = evt2irq(0x1ce0) /* USB1_USB1I0 */,
fb54d268
KM		 458 .flags = IORESOURCE_IRQ,
459 },
460};
461
462static struct platform_device usb1_host_device = {
463 .name = "r8a66597_hcd",
464 .id = 1,
465 .dev = {
466 .dma_mask = NULL, /* not use dma */
467 .coherent_dma_mask = 0xffffffff,
468 .platform_data = &usb1_host_data,
469 },
470 .num_resources = ARRAY_SIZE(usb1_host_resources),
471 .resource = usb1_host_resources,
472};
473
9fa1b7fe
KM		 474/*
475 * QHD display
476 */
477#ifdef CONFIG_AP4EVB_QHD
478
479/* KEYSC (Needs SW43 set to ON) */
480static struct sh_keysc_info keysc_info = {
481 .mode = SH_KEYSC_MODE_1,
482 .scan_timing = 3,
483 .delay = 2500,
484 .keycodes = {
485 KEY_0, KEY_1, KEY_2, KEY_3, KEY_4,
486 KEY_5, KEY_6, KEY_7, KEY_8, KEY_9,
487 KEY_A, KEY_B, KEY_C, KEY_D, KEY_E,
488 KEY_F, KEY_G, KEY_H, KEY_I, KEY_J,
489 KEY_K, KEY_L, KEY_M, KEY_N, KEY_O,
490 },
491};
492
493static struct resource keysc_resources[] = {
494 [0] = {
495 .name = "KEYSC",
496 .start = 0xe61b0000,
497 .end = 0xe61b0063,
498 .flags = IORESOURCE_MEM,
499 },
500 [1] = {
501 .start = evt2irq(0x0be0), /* KEYSC_KEY */
502 .flags = IORESOURCE_IRQ,
503 },
504};
505
506static struct platform_device keysc_device = {
507 .name = "sh_keysc",
508 .id = 0, /* "keysc0" clock */
509 .num_resources = ARRAY_SIZE(keysc_resources),
510 .resource = keysc_resources,
511 .dev = {
512 .platform_data = &keysc_info,
513 },
514};
515
516/* MIPI-DSI */
5e47431a
KM		 517static int sh_mipi_set_dot_clock(struct platform_device *pdev,
518 void __iomem *base,
519 int enable)
520{
521 struct clk *pck = clk_get(&pdev->dev, "dsip_clk");
5e47431a
KM		 522
523 if (IS_ERR(pck))
524 return PTR_ERR(pck);
525
526 if (enable) {
8f9c60f2
KM		 527 /*
528 * DSIPCLK = 24MHz
529 * D-PHY = DSIPCLK * ((0x6*2)+1) = 312MHz (see .phyctrl)
530 * HsByteCLK = D-PHY/8 = 39MHz
531 *
532 * X * Y * FPS =
533 * (544+72+600+16) * (961+8+8+2) * 30 = 36.1MHz
534 */
5e47431a 535 clk_set_rate(pck, clk_round_rate(pck, 24000000));
5e47431a
KM		 536 clk_enable(pck);
537 } else {
538 clk_disable(pck);
539 }
540
541 clk_put(pck);
542
543 return 0;
544}
545
8eda2f21
GL		 546static struct resource mipidsi0_resources[] = {
547 [0] = {
548 .start = 0xffc60000,
5958d58a
MD		 549 .end = 0xffc63073,
550 .flags = IORESOURCE_MEM,
551 },
552 [1] = {
553 .start = 0xffc68000,
554 .end = 0xffc680ef,
8eda2f21
GL		 555 .flags = IORESOURCE_MEM,
556 },
557};
558
559static struct sh_mipi_dsi_info mipidsi0_info = {
560 .data_format = MIPI_RGB888,
772f5d1b 561 .channel = LCDC_CHAN_MAINLCD,
26c3d7ac 562 .lane = 2,
6fd46595 563 .vsynw_offset = 17,
8f9c60f2 564 .phyctrl = 0x6 << 8,
a2e62971
KM		 565 .flags = SH_MIPI_DSI_SYNC_PULSES_MODE |
566 SH_MIPI_DSI_HSbyteCLK,
5e47431a 567 .set_dot_clock = sh_mipi_set_dot_clock,
8eda2f21
GL		 568};
569
570static struct platform_device mipidsi0_device = {
571 .name = "sh-mipi-dsi",
572 .num_resources = ARRAY_SIZE(mipidsi0_resources),
573 .resource = mipidsi0_resources,
574 .id = 0,
575 .dev = {
576 .platform_data = &mipidsi0_info,
577 },
578};
579
9fa1b7fe
KM		 580static struct platform_device *qhd_devices[] __initdata = {
581 &mipidsi0_device,
582 &keysc_device,
583};
584#endif /* CONFIG_AP4EVB_QHD */
585
a1022adb
LP		 586/* LCDC0 */
587static const struct fb_videomode ap4evb_lcdc_modes[] = {
588 {
589#ifdef CONFIG_AP4EVB_QHD
590 .name = "R63302(QHD)",
591 .xres = 544,
592 .yres = 961,
593 .left_margin = 72,
594 .right_margin = 600,
595 .hsync_len = 16,
596 .upper_margin = 8,
597 .lower_margin = 8,
598 .vsync_len = 2,
599 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
600#else
601 .name = "WVGA Panel",
602 .xres = 800,
603 .yres = 480,
604 .left_margin = 220,
605 .right_margin = 110,
606 .hsync_len = 70,
607 .upper_margin = 20,
608 .lower_margin = 5,
609 .vsync_len = 5,
610 .sync = 0,
611#endif
612 },
613};
c241a0e0
LP		 614
615static const struct sh_mobile_meram_cfg lcd_meram_cfg = {
a1022adb 616 .icb[0] = {
a1022adb
LP		 617 .meram_size = 0x40,
618 },
619 .icb[1] = {
a1022adb
LP		 620 .meram_size = 0x40,
621 },
622};
623
624static struct sh_mobile_lcdc_info lcdc_info = {
625 .meram_dev = &meram_info,
626 .ch[0] = {
627 .chan = LCDC_CHAN_MAINLCD,
628 .fourcc = V4L2_PIX_FMT_RGB565,
93ff2598
LP		 629 .lcd_modes = ap4evb_lcdc_modes,
630 .num_modes = ARRAY_SIZE(ap4evb_lcdc_modes),
a1022adb
LP		 631 .meram_cfg = &lcd_meram_cfg,
632#ifdef CONFIG_AP4EVB_QHD
633 .tx_dev = &mipidsi0_device,
634#endif
635 }
636};
637
638static struct resource lcdc_resources[] = {
639 [0] = {
640 .name = "LCDC",
641 .start = 0xfe940000, /* P4-only space */
642 .end = 0xfe943fff,
643 .flags = IORESOURCE_MEM,
644 },
645 [1] = {
646 .start = intcs_evt2irq(0x580),
647 .flags = IORESOURCE_IRQ,
648 },
649};
650
651static struct platform_device lcdc_device = {
652 .name = "sh_mobile_lcdc_fb",
653 .num_resources = ARRAY_SIZE(lcdc_resources),
654 .resource = lcdc_resources,
655 .dev = {
656 .platform_data = &lcdc_info,
657 .coherent_dma_mask = ~0,
658 },
659};
660
cb9215e1
KM		 661/* FSI */
662#define IRQ_FSI evt2irq(0x1840)
bb04e197 663static struct sh_fsi_platform_info fsi_info = {
fec691e7 664 .port_b = {
abca7581 665 .flags = SH_FSI_CLK_CPG |
fec691e7 666 SH_FSI_FMT_SPDIF,
fec691e7 667 },
cb9215e1
KM		 668};
669
670static struct resource fsi_resources[] = {
671 [0] = {
672 .name = "FSI",
673 .start = 0xFE3C0000,
674 .end = 0xFE3C0400 - 1,
675 .flags = IORESOURCE_MEM,
676 },
677 [1] = {
678 .start = IRQ_FSI,
679 .flags = IORESOURCE_IRQ,
680 },
681};
682
683static struct platform_device fsi_device = {
684 .name = "sh_fsi2",
9f6f11b6 685 .id = -1,
cb9215e1
KM		 686 .num_resources = ARRAY_SIZE(fsi_resources),
687 .resource = fsi_resources,
688 .dev = {
689 .platform_data = &fsi_info,
690 },
691};
692
af8a2fe1 693static struct asoc_simple_card_info fsi2_ak4643_info = {
45f31216
KM		 694 .name = "AK4643",
695 .card = "FSI2A-AK4643",
45f31216
KM		 696 .codec = "ak4642-codec.0-0013",
697 .platform = "sh_fsi2",
a4a2992c
KM		 698 .daifmt = SND_SOC_DAIFMT_LEFT_J,
699 .cpu_dai = {
700 .name = "fsia-dai",
701 .fmt = SND_SOC_DAIFMT_CBS_CFS,
702 },
703 .codec_dai = {
704 .name = "ak4642-hifi",
705 .fmt = SND_SOC_DAIFMT_CBM_CFM,
706 .sysclk = 11289600,
707 },
45f31216
KM		 708};
709
c8d6bf9a 710static struct platform_device fsi_ak4643_device = {
af8a2fe1 711 .name = "asoc-simple-card",
45f31216 712 .dev = {
e49d603c 713 .platform_data = &fsi2_ak4643_info,
45f31216 714 },
c8d6bf9a 715};
45f31216 716
a1022adb 717/* LCDC1 */
640dcfa0
GL		 718static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
719 unsigned long *parent_freq);
720
dfbcdf64 721static struct sh_mobile_hdmi_info hdmi_info = {
2669efec 722 .flags = HDMI_SND_SRC_SPDIF,
640dcfa0 723 .clk_optimize_parent = ap4evb_clk_optimize,
dfbcdf64
GL		 724};
725
726static struct resource hdmi_resources[] = {
727 [0] = {
728 .name = "HDMI",
729 .start = 0xe6be0000,
730 .end = 0xe6be00ff,
731 .flags = IORESOURCE_MEM,
732 },
733 [1] = {
734 /* There's also an HDMI interrupt on INTCS @ 0x18e0 */
735 .start = evt2irq(0x17e0),
736 .flags = IORESOURCE_IRQ,
737 },
738};
739
740static struct platform_device hdmi_device = {
741 .name = "sh-mobile-hdmi",
742 .num_resources = ARRAY_SIZE(hdmi_resources),
743 .resource = hdmi_resources,
744 .id = -1,
745 .dev = {
746 .platform_data = &hdmi_info,
747 },
748};
749
640dcfa0
GL		 750static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
751 unsigned long *parent_freq)
752{
753 struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
754 long error;
755
756 if (IS_ERR(hdmi_ick)) {
757 int ret = PTR_ERR(hdmi_ick);
758 pr_err("Cannot get HDMI ICK: %d\n", ret);
759 return ret;
760 }
761
762 error = clk_round_parent(hdmi_ick, target, best_freq, parent_freq, 1, 64);
763
764 clk_put(hdmi_ick);
765
766 return error;
767}
768
c241a0e0 769static const struct sh_mobile_meram_cfg hdmi_meram_cfg = {
1c7fcbed 770 .icb[0] = {
1c7fcbed
DHG		 771 .meram_size = 0x100,
772 },
773 .icb[1] = {
1c7fcbed
DHG		 774 .meram_size = 0x100,
775 },
776};
c8d6bf9a 777
dfbcdf64
GL		 778static struct sh_mobile_lcdc_info sh_mobile_lcdc1_info = {
779 .clock_source = LCDC_CLK_EXTERNAL,
1c7fcbed 780 .meram_dev = &meram_info,
dfbcdf64
GL		 781 .ch[0] = {
782 .chan = LCDC_CHAN_MAINLCD,
edd153a3 783 .fourcc = V4L2_PIX_FMT_RGB565,
dfbcdf64
GL		 784 .interface_type = RGB24,
785 .clock_divider = 1,
786 .flags = LCDC_FLAGS_DWPOL,
1c7fcbed 787 .meram_cfg = &hdmi_meram_cfg,
a1022adb 788 .tx_dev = &hdmi_device,
dfbcdf64
GL		 789 }
790};
791
792static struct resource lcdc1_resources[] = {
793 [0] = {
794 .name = "LCDC1",
795 .start = 0xfe944000,
796 .end = 0xfe947fff,
797 .flags = IORESOURCE_MEM,
798 },
799 [1] = {
88c759a2 800 .start = intcs_evt2irq(0x1780),
dfbcdf64
GL		 801 .flags = IORESOURCE_IRQ,
802 },
803};
804
805static struct platform_device lcdc1_device = {
806 .name = "sh_mobile_lcdc_fb",
807 .num_resources = ARRAY_SIZE(lcdc1_resources),
808 .resource = lcdc1_resources,
809 .id = 1,
810 .dev = {
811 .platform_data = &sh_mobile_lcdc1_info,
812 .coherent_dma_mask = ~0,
813 },
814};
815
fa063b48
KM		 816static struct asoc_simple_card_info fsi2_hdmi_info = {
817 .name = "HDMI",
818 .card = "FSI2B-HDMI",
fa063b48
KM		 819 .codec = "sh-mobile-hdmi",
820 .platform = "sh_fsi2",
a4a2992c
KM		 821 .cpu_dai = {
822 .name = "fsib-dai",
823 .fmt = SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_IB_NF,
824 },
825 .codec_dai = {
826 .name = "sh_mobile_hdmi-hifi",
827 },
fa063b48
KM		 828};
829
3f25c9cc 830static struct platform_device fsi_hdmi_device = {
fa063b48
KM		 831 .name = "asoc-simple-card",
832 .id = 1,
833 .dev = {
834 .platform_data = &fsi2_hdmi_info,
835 },
3f25c9cc
KM		 836};
837
2863e935
AH		 838static struct gpio_led ap4evb_leds[] = {
839 {
840 .name = "led4",
841 .gpio = GPIO_PORT185,
842 .default_state = LEDS_GPIO_DEFSTATE_ON,
843 },
844 {
845 .name = "led2",
846 .gpio = GPIO_PORT186,
847 .default_state = LEDS_GPIO_DEFSTATE_ON,
848 },
849 {
850 .name = "led3",
851 .gpio = GPIO_PORT187,
852 .default_state = LEDS_GPIO_DEFSTATE_ON,
853 },
854 {
855 .name = "led1",
856 .gpio = GPIO_PORT188,
857 .default_state = LEDS_GPIO_DEFSTATE_ON,
858 }
859};
860
861static struct gpio_led_platform_data ap4evb_leds_pdata = {
862 .num_leds = ARRAY_SIZE(ap4evb_leds),
8050fbf2 863 .leds = ap4evb_leds,
2863e935
AH		 864};
865
866static struct platform_device leds_device = {
867 .name = "leds-gpio",
868 .id = 0,
869 .dev = {
870 .platform_data = &ap4evb_leds_pdata,
871 },
872};
873
1a0b1eac
GL		 874static struct i2c_board_info imx074_info = {
875 I2C_BOARD_INFO("imx074", 0x1a),
876};
877
4d4d6fbb 878static struct soc_camera_link imx074_link = {
1a0b1eac
GL		 879 .bus_id = 0,
880 .board_info = &imx074_info,
881 .i2c_adapter_id = 0,
882 .module_name = "imx074",
883};
884
885static struct platform_device ap4evb_camera = {
886 .name = "soc-camera-pdrv",
887 .id = 0,
888 .dev = {
889 .platform_data = &imx074_link,
890 },
891};
892
893static struct sh_csi2_client_config csi2_clients[] = {
894 {
895 .phy = SH_CSI2_PHY_MAIN,
19a1780b 896 .lanes = 0, /* default: 2 lanes */
1a0b1eac
GL		 897 .channel = 0,
898 .pdev = &ap4evb_camera,
899 },
900};
901
902static struct sh_csi2_pdata csi2_info = {
903 .type = SH_CSI2C,
904 .clients = csi2_clients,
905 .num_clients = ARRAY_SIZE(csi2_clients),
906 .flags = SH_CSI2_ECC | SH_CSI2_CRC,
907};
908
909static struct resource csi2_resources[] = {
910 [0] = {
911 .name = "CSI2",
912 .start = 0xffc90000,
913 .end = 0xffc90fff,
914 .flags = IORESOURCE_MEM,
915 },
916 [1] = {
917 .start = intcs_evt2irq(0x17a0),
918 .flags = IORESOURCE_IRQ,
919 },
920};
921
6b526fed
GL		 922static struct sh_mobile_ceu_companion csi2 = {
923 .id = 0,
1a0b1eac
GL		 924 .num_resources = ARRAY_SIZE(csi2_resources),
925 .resource = csi2_resources,
6b526fed 926 .platform_data = &csi2_info,
1a0b1eac
GL		 927};
928
929static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
930 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
ef8f41ff
GL		 931 .max_width = 8188,
932 .max_height = 8188,
6b526fed 933 .csi2 = &csi2,
1a0b1eac
GL		 934};
935
936static struct resource ceu_resources[] = {
937 [0] = {
938 .name = "CEU",
939 .start = 0xfe910000,
940 .end = 0xfe91009f,
941 .flags = IORESOURCE_MEM,
942 },
943 [1] = {
944 .start = intcs_evt2irq(0x880),
945 .flags = IORESOURCE_IRQ,
946 },
947 [2] = {
948 /* place holder for contiguous memory */
949 },
950};
951
952static struct platform_device ceu_device = {
953 .name = "sh_mobile_ceu",
954 .id = 0, /* "ceu0" clock */
955 .num_resources = ARRAY_SIZE(ceu_resources),
956 .resource = ceu_resources,
957 .dev = {
05a5f01c
GL		 958 .platform_data = &sh_mobile_ceu_info,
959 .coherent_dma_mask = 0xffffffff,
1a0b1eac
GL		 960 },
961};
962
2b7eda63 963static struct platform_device *ap4evb_devices[] __initdata = {
2863e935 964 &leds_device,
2b7eda63 965 &nor_flash_device,
1b7e0677 966 &smc911x_device,
3a14d039 967 &sdhi0_device,
341291a6 968 &sdhi1_device,
fb54d268 969 &usb1_host_device,
cb9215e1 970 &fsi_device,
c8d6bf9a 971 &fsi_ak4643_device,
3f25c9cc 972 &fsi_hdmi_device,
beccb12f 973 &sh_mmcif_device,
dfbcdf64 974 &hdmi_device,
a1022adb
LP		 975 &lcdc_device,
976 &lcdc1_device,
1a0b1eac
GL		 977 &ceu_device,
978 &ap4evb_camera,
1c7fcbed 979 &meram_device,
2b7eda63
MD		 980};
981
2ce51f8b 982static void __init hdmi_init_pm_clock(void)
dfbcdf64
GL		 983{
984 struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
985 int ret;
986 long rate;
987
988 if (IS_ERR(hdmi_ick)) {
989 ret = PTR_ERR(hdmi_ick);
990 pr_err("Cannot get HDMI ICK: %d\n", ret);
991 goto out;
992 }
993
685e4080 994 ret = clk_set_parent(&sh7372_pllc2_clk, &sh7372_dv_clki_div2_clk);
dfbcdf64 995 if (ret < 0) {
685e4080 996 pr_err("Cannot set PLLC2 parent: %d, %d users\n", ret, sh7372_pllc2_clk.usecount);
dfbcdf64
GL		 997 goto out;
998 }
999
685e4080 1000 pr_debug("PLLC2 initial frequency %lu\n", clk_get_rate(&sh7372_pllc2_clk));
dfbcdf64 1001
685e4080 1002 rate = clk_round_rate(&sh7372_pllc2_clk, 594000000);
dfbcdf64
GL		 1003 if (rate < 0) {
1004 pr_err("Cannot get suitable rate: %ld\n", rate);
1005 ret = rate;
1006 goto out;
1007 }
1008
685e4080 1009 ret = clk_set_rate(&sh7372_pllc2_clk, rate);
dfbcdf64
GL		 1010 if (ret < 0) {
1011 pr_err("Cannot set rate %ld: %d\n", rate, ret);
1012 goto out;
1013 }
1014
1015 pr_debug("PLLC2 set frequency %lu\n", rate);
1016
685e4080 1017 ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk);
2ce51f8b 1018 if (ret < 0)
dfbcdf64 1019 pr_err("Cannot set HDMI parent: %d\n", ret);
dfbcdf64
GL		 1020
1021out:
1022 if (!IS_ERR(hdmi_ick))
1023 clk_put(hdmi_ick);
dfbcdf64
GL		 1024}
1025
9fa1b7fe 1026/* TouchScreen */
52d5ac00
KM		 1027#ifdef CONFIG_AP4EVB_QHD
1028# define GPIO_TSC_IRQ GPIO_FN_IRQ28_123
1029# define GPIO_TSC_PORT GPIO_PORT123
1030#else /* WVGA */
1031# define GPIO_TSC_IRQ GPIO_FN_IRQ7_40
1032# define GPIO_TSC_PORT GPIO_PORT40
1033#endif
1034
33c9607a 1035#define IRQ28 evt2irq(0x3380) /* IRQ28A */
9fa1b7fe 1036#define IRQ7 evt2irq(0x02e0) /* IRQ7A */
71c3ba9a
KM		 1037static int ts_get_pendown_state(void)
1038{
52d5ac00 1039 int val;
71c3ba9a 1040
52d5ac00 1041 gpio_free(GPIO_TSC_IRQ);
71c3ba9a 1042
5683eafd 1043 gpio_request_one(GPIO_TSC_PORT, GPIOF_IN, NULL);
71c3ba9a 1044
52d5ac00 1045 val = gpio_get_value(GPIO_TSC_PORT);
71c3ba9a 1046
52d5ac00 1047 gpio_request(GPIO_TSC_IRQ, NULL);
71c3ba9a 1048
52d5ac00 1049 return !val;
71c3ba9a
KM		 1050}
1051
71c3ba9a
KM		 1052static int ts_init(void)
1053{
52d5ac00 1054 gpio_request(GPIO_TSC_IRQ, NULL);
71c3ba9a
KM		 1055
1056 return 0;
1057}
1058
bb04e197 1059static struct tsc2007_platform_data tsc2007_info = {
91cf5082
KM		 1060 .model = 2007,
1061 .x_plate_ohms = 180,
71c3ba9a
KM		 1062 .get_pendown_state = ts_get_pendown_state,
1063 .init_platform_hw = ts_init,
91cf5082
KM		 1064};
1065
9fa1b7fe
KM		 1066static struct i2c_board_info tsc_device = {
1067 I2C_BOARD_INFO("tsc2007", 0x48),
1068 .type = "tsc2007",
1069 .platform_data = &tsc2007_info,
1070 /*.irq is selected on ap4evb_init */
1071};
1072
91cf5082 1073/* I2C */
cb9215e1
KM		 1074static struct i2c_board_info i2c0_devices[] = {
1075 {
1076 I2C_BOARD_INFO("ak4643", 0x13),
1077 },
1078};
1079
91cf5082 1080static struct i2c_board_info i2c1_devices[] = {
8fc883c2
KM		 1081 {
1082 I2C_BOARD_INFO("r2025sd", 0x32),
1083 },
91cf5082
KM		 1084};
1085
2b7eda63 1086
0a4b04dc
AB		 1087#define GPIO_PORT9CR IOMEM(0xE6051009)
1088#define GPIO_PORT10CR IOMEM(0xE605100A)
1089#define USCCR1 IOMEM(0xE6058144)
2b7eda63
MD		 1090static void __init ap4evb_init(void)
1091{
201dbd81
RW		 1092 struct pm_domain_device domain_devices[] = {
1093 { "A4LC", &lcdc1_device, },
1094 { "A4LC", &lcdc_device, },
1095 { "A4MP", &fsi_device, },
1096 { "A3SP", &sh_mmcif_device, },
1097 { "A3SP", &sdhi0_device, },
1098 { "A3SP", &sdhi1_device, },
1099 { "A4R", &ceu_device, },
1100 };
dfbcdf64 1101 u32 srcr4;
cb9215e1
KM		 1102 struct clk *clk;
1103
8778b8f4
GL		 1104 regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
1105 ARRAY_SIZE(fixed1v8_power_consumers), 1800000);
1106 regulator_register_always_on(1, "fixed-3.3V", fixed3v3_power_consumers,
1107 ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
1108 regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies));
1109
e3b0161b
MD		 1110 /* External clock source */
1111 clk_set_rate(&sh7372_dv_clki_clk, 27000000);
1112
1b7e0677
KM		 1113 sh7372_pinmux_init();
1114
b228b48e
KM		 1115 /* enable SCIFA0 */
1116 gpio_request(GPIO_FN_SCIFA0_TXD, NULL);
1117 gpio_request(GPIO_FN_SCIFA0_RXD, NULL);
1118
1b7e0677
KM		 1119 /* enable SMSC911X */
1120 gpio_request(GPIO_FN_CS5A, NULL);
1121 gpio_request(GPIO_FN_IRQ6_39, NULL);
1122
8cb3a2eb 1123 /* enable Debug switch (S6) */
5683eafd
LP		 1124 gpio_request_one(GPIO_PORT32, GPIOF_IN | GPIOF_EXPORT, NULL);
1125 gpio_request_one(GPIO_PORT33, GPIOF_IN | GPIOF_EXPORT, NULL);
1126 gpio_request_one(GPIO_PORT34, GPIOF_IN | GPIOF_EXPORT, NULL);
1127 gpio_request_one(GPIO_PORT35, GPIOF_IN | GPIOF_EXPORT, NULL);
8cb3a2eb 1128
3a14d039
MD		 1129 /* SDHI0 */
1130 gpio_request(GPIO_FN_SDHICD0, NULL);
1131 gpio_request(GPIO_FN_SDHIWP0, NULL);
1132 gpio_request(GPIO_FN_SDHICMD0, NULL);
1133 gpio_request(GPIO_FN_SDHICLK0, NULL);
1134 gpio_request(GPIO_FN_SDHID0_3, NULL);
1135 gpio_request(GPIO_FN_SDHID0_2, NULL);
1136 gpio_request(GPIO_FN_SDHID0_1, NULL);
1137 gpio_request(GPIO_FN_SDHID0_0, NULL);
1138
9fa1b7fe
KM		 1139 /* SDHI1 */
1140 gpio_request(GPIO_FN_SDHICMD1, NULL);
1141 gpio_request(GPIO_FN_SDHICLK1, NULL);
1142 gpio_request(GPIO_FN_SDHID1_3, NULL);
1143 gpio_request(GPIO_FN_SDHID1_2, NULL);
1144 gpio_request(GPIO_FN_SDHID1_1, NULL);
1145 gpio_request(GPIO_FN_SDHID1_0, NULL);
91cf5082 1146
c8ee3d4b
KM		 1147 /* MMCIF */
1148 gpio_request(GPIO_FN_MMCD0_0, NULL);
1149 gpio_request(GPIO_FN_MMCD0_1, NULL);
1150 gpio_request(GPIO_FN_MMCD0_2, NULL);
1151 gpio_request(GPIO_FN_MMCD0_3, NULL);
1152 gpio_request(GPIO_FN_MMCD0_4, NULL);
1153 gpio_request(GPIO_FN_MMCD0_5, NULL);
1154 gpio_request(GPIO_FN_MMCD0_6, NULL);
1155 gpio_request(GPIO_FN_MMCD0_7, NULL);
1156 gpio_request(GPIO_FN_MMCCMD0, NULL);
1157 gpio_request(GPIO_FN_MMCCLK0, NULL);
1158
fb54d268
KM		 1159 /* USB enable */
1160 gpio_request(GPIO_FN_VBUS0_1, NULL);
1161 gpio_request(GPIO_FN_IDIN_1_18, NULL);
1162 gpio_request(GPIO_FN_PWEN_1_115, NULL);
1163 gpio_request(GPIO_FN_OVCN_1_114, NULL);
1164 gpio_request(GPIO_FN_EXTLP_1, NULL);
1165 gpio_request(GPIO_FN_OVCN2_1, NULL);
1166
1167 /* setup USB phy */
0a4b04dc 1168 __raw_writew(0x8a0a, IOMEM(0xE6058130)); /* USBCR4 */
fb54d268 1169
2669efec 1170 /* enable FSI2 port A (ak4643) */
cb9215e1
KM		 1171 gpio_request(GPIO_FN_FSIAIBT, NULL);
1172 gpio_request(GPIO_FN_FSIAILR, NULL);
1173 gpio_request(GPIO_FN_FSIAISLD, NULL);
1174 gpio_request(GPIO_FN_FSIAOSLD, NULL);
5683eafd 1175 gpio_request_one(GPIO_PORT161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
cb9215e1
KM		 1176
1177 gpio_request(GPIO_PORT9, NULL);
1178 gpio_request(GPIO_PORT10, NULL);
6a6196af
KM		 1179 gpio_direction_none(GPIO_PORT9CR); /* FSIAOBT needs no direction */
1180 gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */
cb9215e1 1181
68accd73 1182 /* card detect pin for MMC slot (CN7) */
5683eafd 1183 gpio_request_one(GPIO_PORT41, GPIOF_IN, NULL);
68accd73 1184
2669efec
KM		 1185 /* setup FSI2 port B (HDMI) */
1186 gpio_request(GPIO_FN_FSIBCK, NULL);
1187 __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */
1188
cb9215e1
KM		 1189 /* set SPU2 clock to 119.6 MHz */
1190 clk = clk_get(NULL, "spu_clk");
2ae2b766 1191 if (!IS_ERR(clk)) {
cb9215e1
KM		 1192 clk_set_rate(clk, clk_round_rate(clk, 119600000));
1193 clk_put(clk);
1194 }
1195
cb9215e1
KM		 1196 /*
1197 * set irq priority, to avoid sound chopping
1198 * when NFS rootfs is used
1199 * FSI(3) > SMSC911X(2)
1200 */
1201 intc_set_priority(IRQ_FSI, 3);
1202
1203 i2c_register_board_info(0, i2c0_devices,
1204 ARRAY_SIZE(i2c0_devices));
1205
1206 i2c_register_board_info(1, i2c1_devices,
1207 ARRAY_SIZE(i2c1_devices));
1208
9fa1b7fe 1209#ifdef CONFIG_AP4EVB_QHD
dd8a61a7 1210
9fa1b7fe 1211 /*
dd8a61a7
MD		 1212 * For QHD Panel (MIPI-DSI, CONFIG_AP4EVB_QHD=y) and
1213 * IRQ28 for Touch Panel, set dip switches S3, S43 as OFF, ON.
9fa1b7fe
KM		 1214 */
1215
1216 /* enable KEYSC */
1217 gpio_request(GPIO_FN_KEYOUT0, NULL);
1218 gpio_request(GPIO_FN_KEYOUT1, NULL);
1219 gpio_request(GPIO_FN_KEYOUT2, NULL);
1220 gpio_request(GPIO_FN_KEYOUT3, NULL);
1221 gpio_request(GPIO_FN_KEYOUT4, NULL);
1222 gpio_request(GPIO_FN_KEYIN0_136, NULL);
1223 gpio_request(GPIO_FN_KEYIN1_135, NULL);
1224 gpio_request(GPIO_FN_KEYIN2_134, NULL);
1225 gpio_request(GPIO_FN_KEYIN3_133, NULL);
1226 gpio_request(GPIO_FN_KEYIN4, NULL);
1227
1228 /* enable TouchScreen */
6845664a 1229 irq_set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW);
9fa1b7fe
KM		 1230
1231 tsc_device.irq = IRQ28;
1232 i2c_register_board_info(1, &tsc_device, 1);
1233
1234 /* LCDC0 */
1235 lcdc_info.clock_source = LCDC_CLK_PERIPHERAL;
1236 lcdc_info.ch[0].interface_type = RGB24;
1237 lcdc_info.ch[0].clock_divider = 1;
1238 lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL;
afaad83b
LP		 1239 lcdc_info.ch[0].panel_cfg.width = 44;
1240 lcdc_info.ch[0].panel_cfg.height = 79;
9fa1b7fe
KM		 1241
1242 platform_add_devices(qhd_devices, ARRAY_SIZE(qhd_devices));
1243
1244#else
1245 /*
dd8a61a7
MD		 1246 * For WVGA Panel (18-bit RGB, CONFIG_AP4EVB_WVGA=y) and
1247 * IRQ7 for Touch Panel, set dip switches S3, S43 to ON, OFF.
9fa1b7fe 1248 */
dd8a61a7 1249
9fa1b7fe
KM		 1250 gpio_request(GPIO_FN_LCDD17, NULL);
1251 gpio_request(GPIO_FN_LCDD16, NULL);
1252 gpio_request(GPIO_FN_LCDD15, NULL);
1253 gpio_request(GPIO_FN_LCDD14, NULL);
1254 gpio_request(GPIO_FN_LCDD13, NULL);
1255 gpio_request(GPIO_FN_LCDD12, NULL);
1256 gpio_request(GPIO_FN_LCDD11, NULL);
1257 gpio_request(GPIO_FN_LCDD10, NULL);
1258 gpio_request(GPIO_FN_LCDD9, NULL);
1259 gpio_request(GPIO_FN_LCDD8, NULL);
1260 gpio_request(GPIO_FN_LCDD7, NULL);
1261 gpio_request(GPIO_FN_LCDD6, NULL);
1262 gpio_request(GPIO_FN_LCDD5, NULL);
1263 gpio_request(GPIO_FN_LCDD4, NULL);
1264 gpio_request(GPIO_FN_LCDD3, NULL);
1265 gpio_request(GPIO_FN_LCDD2, NULL);
1266 gpio_request(GPIO_FN_LCDD1, NULL);
1267 gpio_request(GPIO_FN_LCDD0, NULL);
1268 gpio_request(GPIO_FN_LCDDISP, NULL);
1269 gpio_request(GPIO_FN_LCDDCK, NULL);
1270
5683eafd
LP		 1271 gpio_request_one(GPIO_PORT189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */
1272 gpio_request_one(GPIO_PORT151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
9fa1b7fe
KM		 1273
1274 lcdc_info.clock_source = LCDC_CLK_BUS;
1275 lcdc_info.ch[0].interface_type = RGB18;
f60cb470 1276 lcdc_info.ch[0].clock_divider = 3;
9fa1b7fe 1277 lcdc_info.ch[0].flags = 0;
afaad83b
LP		 1278 lcdc_info.ch[0].panel_cfg.width = 152;
1279 lcdc_info.ch[0].panel_cfg.height = 91;
9fa1b7fe
KM		 1280
1281 /* enable TouchScreen */
6845664a 1282 irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);
9fa1b7fe
KM		 1283
1284 tsc_device.irq = IRQ7;
1285 i2c_register_board_info(0, &tsc_device, 1);
1286#endif /* CONFIG_AP4EVB_QHD */
341291a6 1287
1a0b1eac
GL		 1288 /* CEU */
1289
1290 /*
1291 * TODO: reserve memory for V4L2 DMA buffers, when a suitable API
1292 * becomes available
1293 */
1294
1295 /* MIPI-CSI stuff */
1296 gpio_request(GPIO_FN_VIO_CKO, NULL);
1297
1298 clk = clk_get(NULL, "vck1_clk");
1299 if (!IS_ERR(clk)) {
1300 clk_set_rate(clk, clk_round_rate(clk, 13000000));
1301 clk_enable(clk);
1302 clk_put(clk);
1303 }
1304
2b7eda63
MD		 1305 sh7372_add_standard_devices();
1306
dfbcdf64
GL		 1307 /* HDMI */
1308 gpio_request(GPIO_FN_HDMI_HPD, NULL);
1309 gpio_request(GPIO_FN_HDMI_CEC, NULL);
1310
1311 /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
0a4b04dc 1312#define SRCR4 IOMEM(0xe61580bc)
dfbcdf64
GL		 1313 srcr4 = __raw_readl(SRCR4);
1314 __raw_writel(srcr4 | (1 << 13), SRCR4);
1315 udelay(50);
1316 __raw_writel(srcr4 & ~(1 << 13), SRCR4);
1317
2b7eda63 1318 platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices));
2ce51f8b 1319
201dbd81
RW		 1320 rmobile_add_devices_to_domains(domain_devices,
1321 ARRAY_SIZE(domain_devices));
d93f5cde 1322
2ce51f8b 1323 hdmi_init_pm_clock();
97991657 1324 sh7372_pm_init();
a41b6466 1325 pm_clk_add(&fsi_device.dev, "spu2");
d0168fdc 1326 pm_clk_add(&lcdc1_device.dev, "hdmi");
2b7eda63
MD		 1327}
1328
1329MACHINE_START(AP4EVB, "ap4evb")
5d7220ec
MD		 1330 .map_io = sh7372_map_io,
1331 .init_early = sh7372_add_early_devices,
2b7eda63 1332 .init_irq = sh7372_init_irq,
863b1719 1333 .handle_irq = shmobile_handle_irq_intc,
2b7eda63 1334 .init_machine = ap4evb_init,
caaca999 1335 .init_late = sh7372_pm_init_late,
6bb27d73 1336 .init_time = sh7372_earlytimer_init,
2b7eda63 1337MACHINE_END
kernel source for telekom puls (alcatel/mediatek)