Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mach-sa1100/time.c | |
3 | * | |
4 | * Copyright (C) 1998 Deborah Wallach. | |
93982535 KE |
5 | * Twiddles (C) 1999 Hugo Fiennes <hugo@empeg.com> |
6 | * | |
2f82af08 | 7 | * 2000/03/29 (C) Nicolas Pitre <nico@fluxnic.net> |
1da177e4 LT |
8 | * Rewritten: big cleanup, much simpler, better HZ accuracy. |
9 | * | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/errno.h> | |
13 | #include <linux/interrupt.h> | |
119c641c | 14 | #include <linux/irq.h> |
5094b92f | 15 | #include <linux/sched.h> /* just for sched_clock() - funny that */ |
1da177e4 | 16 | #include <linux/timex.h> |
3e238be2 | 17 | #include <linux/clockchips.h> |
1da177e4 LT |
18 | |
19 | #include <asm/mach/time.h> | |
5094b92f | 20 | #include <asm/sched_clock.h> |
a09e64fb | 21 | #include <mach/hardware.h> |
1da177e4 | 22 | |
5094b92f RK |
23 | /* |
24 | * This is the SA11x0 sched_clock implementation. | |
25 | */ | |
26 | static DEFINE_CLOCK_DATA(cd); | |
27 | ||
28 | /* | |
29 | * Constants generated by clocks_calc_mult_shift(m, s, 3.6864MHz, | |
30 | * NSEC_PER_SEC, 60). | |
31 | * This gives a resolution of about 271ns and a wrap period of about 19min. | |
32 | */ | |
33 | #define SC_MULT 2275555556u | |
34 | #define SC_SHIFT 23 | |
35 | ||
36 | unsigned long long notrace sched_clock(void) | |
37 | { | |
38 | u32 cyc = OSCR; | |
39 | return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT); | |
40 | } | |
41 | ||
42 | static void notrace sa1100_update_sched_clock(void) | |
43 | { | |
44 | u32 cyc = OSCR; | |
45 | update_sched_clock(&cd, cyc, (u32)~0); | |
46 | } | |
47 | ||
3e238be2 | 48 | #define MIN_OSCR_DELTA 2 |
1da177e4 | 49 | |
3e238be2 | 50 | static irqreturn_t sa1100_ost0_interrupt(int irq, void *dev_id) |
1da177e4 | 51 | { |
3e238be2 | 52 | struct clock_event_device *c = dev_id; |
1da177e4 | 53 | |
3e238be2 RK |
54 | /* Disarm the compare/match, signal the event. */ |
55 | OIER &= ~OIER_E0; | |
56 | OSSR = OSSR_M0; | |
57 | c->event_handler(c); | |
1da177e4 | 58 | |
3e238be2 RK |
59 | return IRQ_HANDLED; |
60 | } | |
569d2c34 | 61 | |
3e238be2 RK |
62 | static int |
63 | sa1100_osmr0_set_next_event(unsigned long delta, struct clock_event_device *c) | |
1da177e4 | 64 | { |
a602f0f2 | 65 | unsigned long next, oscr; |
1da177e4 | 66 | |
3e238be2 RK |
67 | OIER |= OIER_E0; |
68 | next = OSCR + delta; | |
69 | OSMR0 = next; | |
70 | oscr = OSCR; | |
569d2c34 | 71 | |
3e238be2 RK |
72 | return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0; |
73 | } | |
1da177e4 | 74 | |
3e238be2 RK |
75 | static void |
76 | sa1100_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *c) | |
77 | { | |
3e238be2 RK |
78 | switch (mode) { |
79 | case CLOCK_EVT_MODE_ONESHOT: | |
80 | case CLOCK_EVT_MODE_UNUSED: | |
81 | case CLOCK_EVT_MODE_SHUTDOWN: | |
3e238be2 RK |
82 | OIER &= ~OIER_E0; |
83 | OSSR = OSSR_M0; | |
3e238be2 RK |
84 | break; |
85 | ||
86 | case CLOCK_EVT_MODE_RESUME: | |
87 | case CLOCK_EVT_MODE_PERIODIC: | |
88 | break; | |
89 | } | |
1da177e4 LT |
90 | } |
91 | ||
3e238be2 RK |
92 | static struct clock_event_device ckevt_sa1100_osmr0 = { |
93 | .name = "osmr0", | |
94 | .features = CLOCK_EVT_FEAT_ONESHOT, | |
95 | .shift = 32, | |
96 | .rating = 200, | |
3e238be2 RK |
97 | .set_next_event = sa1100_osmr0_set_next_event, |
98 | .set_mode = sa1100_osmr0_set_mode, | |
1da177e4 LT |
99 | }; |
100 | ||
fac28e6d | 101 | static cycle_t sa1100_read_oscr(struct clocksource *s) |
d142b6e7 RK |
102 | { |
103 | return OSCR; | |
104 | } | |
105 | ||
106 | static struct clocksource cksrc_sa1100_oscr = { | |
107 | .name = "oscr", | |
108 | .rating = 200, | |
109 | .read = sa1100_read_oscr, | |
110 | .mask = CLOCKSOURCE_MASK(32), | |
d142b6e7 RK |
111 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
112 | }; | |
113 | ||
3e238be2 RK |
114 | static struct irqaction sa1100_timer_irq = { |
115 | .name = "ost0", | |
116 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | |
117 | .handler = sa1100_ost0_interrupt, | |
118 | .dev_id = &ckevt_sa1100_osmr0, | |
119 | }; | |
120 | ||
1da177e4 LT |
121 | static void __init sa1100_timer_init(void) |
122 | { | |
5285eb57 | 123 | OIER = 0; /* disable any timer interrupts */ |
1da177e4 | 124 | OSSR = 0xf; /* clear status on all timers */ |
3e238be2 | 125 | |
5094b92f RK |
126 | init_fixed_sched_clock(&cd, sa1100_update_sched_clock, 32, |
127 | 3686400, SC_MULT, SC_SHIFT); | |
128 | ||
3e238be2 RK |
129 | ckevt_sa1100_osmr0.mult = |
130 | div_sc(3686400, NSEC_PER_SEC, ckevt_sa1100_osmr0.shift); | |
131 | ckevt_sa1100_osmr0.max_delta_ns = | |
132 | clockevent_delta2ns(0x7fffffff, &ckevt_sa1100_osmr0); | |
133 | ckevt_sa1100_osmr0.min_delta_ns = | |
134 | clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_sa1100_osmr0) + 1; | |
320ab2b0 | 135 | ckevt_sa1100_osmr0.cpumask = cpumask_of(0); |
d142b6e7 | 136 | |
3e238be2 | 137 | setup_irq(IRQ_OST0, &sa1100_timer_irq); |
569d2c34 | 138 | |
2c760b5b | 139 | clocksource_register_hz(&cksrc_sa1100_oscr, CLOCK_TICK_RATE); |
3e238be2 | 140 | clockevents_register_device(&ckevt_sa1100_osmr0); |
569d2c34 NP |
141 | } |
142 | ||
1da177e4 LT |
143 | #ifdef CONFIG_PM |
144 | unsigned long osmr[4], oier; | |
145 | ||
146 | static void sa1100_timer_suspend(void) | |
147 | { | |
148 | osmr[0] = OSMR0; | |
149 | osmr[1] = OSMR1; | |
150 | osmr[2] = OSMR2; | |
151 | osmr[3] = OSMR3; | |
152 | oier = OIER; | |
153 | } | |
154 | ||
155 | static void sa1100_timer_resume(void) | |
156 | { | |
157 | OSSR = 0x0f; | |
158 | OSMR0 = osmr[0]; | |
159 | OSMR1 = osmr[1]; | |
160 | OSMR2 = osmr[2]; | |
161 | OSMR3 = osmr[3]; | |
162 | OIER = oier; | |
163 | ||
164 | /* | |
165 | * OSMR0 is the system timer: make sure OSCR is sufficiently behind | |
166 | */ | |
167 | OSCR = OSMR0 - LATCH; | |
168 | } | |
169 | #else | |
170 | #define sa1100_timer_suspend NULL | |
171 | #define sa1100_timer_resume NULL | |
172 | #endif | |
173 | ||
174 | struct sys_timer sa1100_timer = { | |
175 | .init = sa1100_timer_init, | |
176 | .suspend = sa1100_timer_suspend, | |
177 | .resume = sa1100_timer_resume, | |
1da177e4 | 178 | }; |