[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-sa1100 / time.c

/*
 * linux/arch/arm/mach-sa1100/time.c
 *
 * Copyright (C) 1998 Deborah Wallach.
 * Twiddles  (C) 1999 Hugo Fiennes <hugo@empeg.com>
 *
 * 2000/03/29 (C) Nicolas Pitre <nico@fluxnic.net>
 *	Rewritten: big cleanup, much simpler, better HZ accuracy.
 *
 */
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/timex.h>
#include <linux/clockchips.h>

#include <asm/mach/time.h>
#include <mach/hardware.h>

#define MIN_OSCR_DELTA 2

static irqreturn_t sa1100_ost0_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *c = dev_id;

	/* Disarm the compare/match, signal the event. */
	OIER &= ~OIER_E0;
	OSSR = OSSR_M0;
	c->event_handler(c);

	return IRQ_HANDLED;
}

static int
sa1100_osmr0_set_next_event(unsigned long delta, struct clock_event_device *c)
{
	unsigned long next, oscr;

	OIER |= OIER_E0;
	next = OSCR + delta;
	OSMR0 = next;
	oscr = OSCR;

	return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
}

static void
sa1100_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *c)
{
	switch (mode) {
	case CLOCK_EVT_MODE_ONESHOT:
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		OIER &= ~OIER_E0;
		OSSR = OSSR_M0;
		break;

	case CLOCK_EVT_MODE_RESUME:
	case CLOCK_EVT_MODE_PERIODIC:
		break;
	}
}

static struct clock_event_device ckevt_sa1100_osmr0 = {
	.name		= "osmr0",
	.features	= CLOCK_EVT_FEAT_ONESHOT,
	.shift		= 32,
	.rating		= 200,
	.set_next_event	= sa1100_osmr0_set_next_event,
	.set_mode	= sa1100_osmr0_set_mode,
};

static cycle_t sa1100_read_oscr(struct clocksource *s)
{
	return OSCR;
}

static struct clocksource cksrc_sa1100_oscr = {
	.name		= "oscr",
	.rating		= 200,
	.read		= sa1100_read_oscr,
	.mask		= CLOCKSOURCE_MASK(32),
	.shift		= 20,
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

static struct irqaction sa1100_timer_irq = {
	.name		= "ost0",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= sa1100_ost0_interrupt,
	.dev_id		= &ckevt_sa1100_osmr0,
};

static void __init sa1100_timer_init(void)
{
	OIER = 0;		/* disable any timer interrupts */
	OSSR = 0xf;		/* clear status on all timers */

	ckevt_sa1100_osmr0.mult =
		div_sc(3686400, NSEC_PER_SEC, ckevt_sa1100_osmr0.shift);
	ckevt_sa1100_osmr0.max_delta_ns =
		clockevent_delta2ns(0x7fffffff, &ckevt_sa1100_osmr0);
	ckevt_sa1100_osmr0.min_delta_ns =
		clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_sa1100_osmr0) + 1;
	ckevt_sa1100_osmr0.cpumask = cpumask_of(0);

	cksrc_sa1100_oscr.mult =
		clocksource_hz2mult(CLOCK_TICK_RATE, cksrc_sa1100_oscr.shift);

	setup_irq(IRQ_OST0, &sa1100_timer_irq);

	clocksource_register(&cksrc_sa1100_oscr);
	clockevents_register_device(&ckevt_sa1100_osmr0);
}

#ifdef CONFIG_PM
unsigned long osmr[4], oier;

static void sa1100_timer_suspend(void)
{
	osmr[0] = OSMR0;
	osmr[1] = OSMR1;
	osmr[2] = OSMR2;
	osmr[3] = OSMR3;
	oier = OIER;
}

static void sa1100_timer_resume(void)
{
	OSSR = 0x0f;
	OSMR0 = osmr[0];
	OSMR1 = osmr[1];
	OSMR2 = osmr[2];
	OSMR3 = osmr[3];
	OIER = oier;

	/*
	 * OSMR0 is the system timer: make sure OSCR is sufficiently behind
	 */
	OSCR = OSMR0 - LATCH;
}
#else
#define sa1100_timer_suspend NULL
#define sa1100_timer_resume NULL
#endif

struct sys_timer sa1100_timer = {
	.init		= sa1100_timer_init,
	.suspend	= sa1100_timer_suspend,
	.resume		= sa1100_timer_resume,
};
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-sa1100/time.c
	3	*
	4	* Copyright (C) 1998 Deborah Wallach.
93982535 KE	5	* Twiddles (C) 1999 Hugo Fiennes <hugo@empeg.com>
93982535 KE	6	*
2f82af08	7	* 2000/03/29 (C) Nicolas Pitre <nico@fluxnic.net>
1da177e4 LT	8	* Rewritten: big cleanup, much simpler, better HZ accuracy.
	9	*
	10	*/
	11	#include <linux/init.h>
	12	#include <linux/errno.h>
	13	#include <linux/interrupt.h>
119c641c	14	#include <linux/irq.h>
1da177e4	15	#include <linux/timex.h>
3e238be2	16	#include <linux/clockchips.h>
1da177e4 LT	17
1da177e4 LT	18	#include <asm/mach/time.h>
a09e64fb	19	#include <mach/hardware.h>
1da177e4	20
3e238be2	21	#define MIN_OSCR_DELTA 2
1da177e4	22
3e238be2	23	static irqreturn_t sa1100_ost0_interrupt(int irq, void *dev_id)
1da177e4	24	{
3e238be2	25	struct clock_event_device *c = dev_id;
1da177e4	26
3e238be2 RK	27	/* Disarm the compare/match, signal the event. */
	28	OIER &= ~OIER_E0;
	29	OSSR = OSSR_M0;
	30	c->event_handler(c);
1da177e4	31
3e238be2 RK	32	return IRQ_HANDLED;
3e238be2 RK	33	}
569d2c34	34
3e238be2 RK	35	static int
3e238be2 RK	36	sa1100_osmr0_set_next_event(unsigned long delta, struct clock_event_device *c)
1da177e4	37	{
a602f0f2	38	unsigned long next, oscr;
1da177e4	39
3e238be2 RK	40	OIER \|= OIER_E0;
	41	next = OSCR + delta;
	42	OSMR0 = next;
	43	oscr = OSCR;
569d2c34	44
3e238be2 RK	45	return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
3e238be2 RK	46	}
1da177e4	47
3e238be2 RK	48	static void
	49	sa1100_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *c)
	50	{
3e238be2 RK	51	switch (mode) {
	52	case CLOCK_EVT_MODE_ONESHOT:
	53	case CLOCK_EVT_MODE_UNUSED:
	54	case CLOCK_EVT_MODE_SHUTDOWN:
3e238be2 RK	55	OIER &= ~OIER_E0;
3e238be2 RK	56	OSSR = OSSR_M0;
3e238be2 RK	57	break;
	58
	59	case CLOCK_EVT_MODE_RESUME:
	60	case CLOCK_EVT_MODE_PERIODIC:
	61	break;
	62	}
1da177e4 LT	63	}
1da177e4 LT	64
3e238be2 RK	65	static struct clock_event_device ckevt_sa1100_osmr0 = {
	66	.name = "osmr0",
	67	.features = CLOCK_EVT_FEAT_ONESHOT,
	68	.shift = 32,
	69	.rating = 200,
3e238be2 RK	70	.set_next_event = sa1100_osmr0_set_next_event,
3e238be2 RK	71	.set_mode = sa1100_osmr0_set_mode,
1da177e4 LT	72	};
1da177e4 LT	73
fac28e6d	74	static cycle_t sa1100_read_oscr(struct clocksource *s)
d142b6e7 RK	75	{
	76	return OSCR;
	77	}
	78
	79	static struct clocksource cksrc_sa1100_oscr = {
	80	.name = "oscr",
	81	.rating = 200,
	82	.read = sa1100_read_oscr,
	83	.mask = CLOCKSOURCE_MASK(32),
	84	.shift = 20,
	85	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	86	};
	87
3e238be2 RK	88	static struct irqaction sa1100_timer_irq = {
	89	.name = "ost0",
	90	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
	91	.handler = sa1100_ost0_interrupt,
	92	.dev_id = &ckevt_sa1100_osmr0,
	93	};
	94
1da177e4 LT	95	static void __init sa1100_timer_init(void)
1da177e4 LT	96	{
5285eb57	97	OIER = 0; /* disable any timer interrupts */
1da177e4	98	OSSR = 0xf; /* clear status on all timers */
3e238be2 RK	99
	100	ckevt_sa1100_osmr0.mult =
	101	div_sc(3686400, NSEC_PER_SEC, ckevt_sa1100_osmr0.shift);
	102	ckevt_sa1100_osmr0.max_delta_ns =
	103	clockevent_delta2ns(0x7fffffff, &ckevt_sa1100_osmr0);
	104	ckevt_sa1100_osmr0.min_delta_ns =
	105	clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_sa1100_osmr0) + 1;
320ab2b0	106	ckevt_sa1100_osmr0.cpumask = cpumask_of(0);
d142b6e7 RK	107
	108	cksrc_sa1100_oscr.mult =
	109	clocksource_hz2mult(CLOCK_TICK_RATE, cksrc_sa1100_oscr.shift);
	110
3e238be2	111	setup_irq(IRQ_OST0, &sa1100_timer_irq);
569d2c34	112
3e238be2 RK	113	clocksource_register(&cksrc_sa1100_oscr);
3e238be2 RK	114	clockevents_register_device(&ckevt_sa1100_osmr0);
569d2c34 NP	115	}
569d2c34 NP	116
1da177e4 LT	117	#ifdef CONFIG_PM
	118	unsigned long osmr[4], oier;
	119
	120	static void sa1100_timer_suspend(void)
	121	{
	122	osmr[0] = OSMR0;
	123	osmr[1] = OSMR1;
	124	osmr[2] = OSMR2;
	125	osmr[3] = OSMR3;
	126	oier = OIER;
	127	}
	128
	129	static void sa1100_timer_resume(void)
	130	{
	131	OSSR = 0x0f;
	132	OSMR0 = osmr[0];
	133	OSMR1 = osmr[1];
	134	OSMR2 = osmr[2];
	135	OSMR3 = osmr[3];
	136	OIER = oier;
	137
	138	/*
	139	* OSMR0 is the system timer: make sure OSCR is sufficiently behind
	140	*/
	141	OSCR = OSMR0 - LATCH;
	142	}
	143	#else
	144	#define sa1100_timer_suspend NULL
	145	#define sa1100_timer_resume NULL
	146	#endif
	147
	148	struct sys_timer sa1100_timer = {
	149	.init = sa1100_timer_init,
	150	.suspend = sa1100_timer_suspend,
	151	.resume = sa1100_timer_resume,
1da177e4	152	};