[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-sa1100 / neponset.c

/*
 * linux/arch/arm/mach-sa1100/neponset.c
 */
#include <linux/err.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_data/sa11x0-serial.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/serial_core.h>
#include <linux/slab.h>

#include <asm/mach-types.h>
#include <asm/mach/map.h>
#include <asm/hardware/sa1111.h>
#include <asm/sizes.h>

#include <mach/hardware.h>
#include <mach/assabet.h>
#include <mach/neponset.h>
#include <mach/irqs.h>

#define NEP_IRQ_SMC91X	0
#define NEP_IRQ_USAR	1
#define NEP_IRQ_SA1111	2
#define NEP_IRQ_NR	3

#define WHOAMI		0x00
#define LEDS		0x10
#define SWPK		0x20
#define IRR		0x24
#define KP_Y_IN		0x80
#define KP_X_OUT	0x90
#define NCR_0		0xa0
#define MDM_CTL_0	0xb0
#define MDM_CTL_1	0xb4
#define AUD_CTL		0xc0

#define IRR_ETHERNET	(1 << 0)
#define IRR_USAR	(1 << 1)
#define IRR_SA1111	(1 << 2)

#define MDM_CTL0_RTS1	(1 << 0)
#define MDM_CTL0_DTR1	(1 << 1)
#define MDM_CTL0_RTS2	(1 << 2)
#define MDM_CTL0_DTR2	(1 << 3)

#define MDM_CTL1_CTS1	(1 << 0)
#define MDM_CTL1_DSR1	(1 << 1)
#define MDM_CTL1_DCD1	(1 << 2)
#define MDM_CTL1_CTS2	(1 << 3)
#define MDM_CTL1_DSR2	(1 << 4)
#define MDM_CTL1_DCD2	(1 << 5)

#define AUD_SEL_1341	(1 << 0)
#define AUD_MUTE_1341	(1 << 1)

extern void sa1110_mb_disable(void);

struct neponset_drvdata {
	void __iomem *base;
	struct platform_device *sa1111;
	struct platform_device *smc91x;
	unsigned irq_base;
#ifdef CONFIG_PM_SLEEP
	u32 ncr0;
	u32 mdm_ctl_0;
#endif
};

static void __iomem *nep_base;

void neponset_ncr_frob(unsigned int mask, unsigned int val)
{
	void __iomem *base = nep_base;

	if (base) {
		unsigned long flags;
		unsigned v;

		local_irq_save(flags);
		v = readb_relaxed(base + NCR_0);
		writeb_relaxed((v & ~mask) | val, base + NCR_0);
		local_irq_restore(flags);
	} else {
		WARN(1, "nep_base unset\n");
	}
}
EXPORT_SYMBOL(neponset_ncr_frob);

static void neponset_set_mctrl(struct uart_port *port, u_int mctrl)
{
	void __iomem *base = nep_base;
	u_int mdm_ctl0;

	if (!base)
		return;

	mdm_ctl0 = readb_relaxed(base + MDM_CTL_0);
	if (port->mapbase == _Ser1UTCR0) {
		if (mctrl & TIOCM_RTS)
			mdm_ctl0 &= ~MDM_CTL0_RTS2;
		else
			mdm_ctl0 |= MDM_CTL0_RTS2;

		if (mctrl & TIOCM_DTR)
			mdm_ctl0 &= ~MDM_CTL0_DTR2;
		else
			mdm_ctl0 |= MDM_CTL0_DTR2;
	} else if (port->mapbase == _Ser3UTCR0) {
		if (mctrl & TIOCM_RTS)
			mdm_ctl0 &= ~MDM_CTL0_RTS1;
		else
			mdm_ctl0 |= MDM_CTL0_RTS1;

		if (mctrl & TIOCM_DTR)
			mdm_ctl0 &= ~MDM_CTL0_DTR1;
		else
			mdm_ctl0 |= MDM_CTL0_DTR1;
	}

	writeb_relaxed(mdm_ctl0, base + MDM_CTL_0);
}

static u_int neponset_get_mctrl(struct uart_port *port)
{
	void __iomem *base = nep_base;
	u_int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR;
	u_int mdm_ctl1;

	if (!base)
		return ret;

	mdm_ctl1 = readb_relaxed(base + MDM_CTL_1);
	if (port->mapbase == _Ser1UTCR0) {
		if (mdm_ctl1 & MDM_CTL1_DCD2)
			ret &= ~TIOCM_CD;
		if (mdm_ctl1 & MDM_CTL1_CTS2)
			ret &= ~TIOCM_CTS;
		if (mdm_ctl1 & MDM_CTL1_DSR2)
			ret &= ~TIOCM_DSR;
	} else if (port->mapbase == _Ser3UTCR0) {
		if (mdm_ctl1 & MDM_CTL1_DCD1)
			ret &= ~TIOCM_CD;
		if (mdm_ctl1 & MDM_CTL1_CTS1)
			ret &= ~TIOCM_CTS;
		if (mdm_ctl1 & MDM_CTL1_DSR1)
			ret &= ~TIOCM_DSR;
	}

	return ret;
}

static struct sa1100_port_fns neponset_port_fns = {
	.set_mctrl	= neponset_set_mctrl,
	.get_mctrl	= neponset_get_mctrl,
};

/*
 * Install handler for Neponset IRQ.  Note that we have to loop here
 * since the ETHERNET and USAR IRQs are level based, and we need to
 * ensure that the IRQ signal is deasserted before returning.  This
 * is rather unfortunate.
 */
static void neponset_irq_handler(unsigned int irq, struct irq_desc *desc)
{
	struct neponset_drvdata *d = irq_desc_get_handler_data(desc);
	unsigned int irr;

	while (1) {
		/*
		 * Acknowledge the parent IRQ.
		 */
		desc->irq_data.chip->irq_ack(&desc->irq_data);

		/*
		 * Read the interrupt reason register.  Let's have all
		 * active IRQ bits high.  Note: there is a typo in the
		 * Neponset user's guide for the SA1111 IRR level.
		 */
		irr = readb_relaxed(d->base + IRR);
		irr ^= IRR_ETHERNET | IRR_USAR;

		if ((irr & (IRR_ETHERNET | IRR_USAR | IRR_SA1111)) == 0)
			break;

		/*
		 * Since there is no individual mask, we have to
		 * mask the parent IRQ.  This is safe, since we'll
		 * recheck the register for any pending IRQs.
		 */
		if (irr & (IRR_ETHERNET | IRR_USAR)) {
			desc->irq_data.chip->irq_mask(&desc->irq_data);

			/*
			 * Ack the interrupt now to prevent re-entering
			 * this neponset handler.  Again, this is safe
			 * since we'll check the IRR register prior to
			 * leaving.
			 */
			desc->irq_data.chip->irq_ack(&desc->irq_data);

			if (irr & IRR_ETHERNET)
				generic_handle_irq(d->irq_base + NEP_IRQ_SMC91X);

			if (irr & IRR_USAR)
				generic_handle_irq(d->irq_base + NEP_IRQ_USAR);

			desc->irq_data.chip->irq_unmask(&desc->irq_data);
		}

		if (irr & IRR_SA1111)
			generic_handle_irq(d->irq_base + NEP_IRQ_SA1111);
	}
}

/* Yes, we really do not have any kind of masking or unmasking */
static void nochip_noop(struct irq_data *irq)
{
}

static struct irq_chip nochip = {
	.name = "neponset",
	.irq_ack = nochip_noop,
	.irq_mask = nochip_noop,
	.irq_unmask = nochip_noop,
};

static struct sa1111_platform_data sa1111_info = {
	.disable_devs	= SA1111_DEVID_PS2_MSE,
};

static int neponset_probe(struct platform_device *dev)
{
	struct neponset_drvdata *d;
	struct resource *nep_res, *sa1111_res, *smc91x_res;
	struct resource sa1111_resources[] = {
		DEFINE_RES_MEM(0x40000000, SZ_8K),
		{ .flags = IORESOURCE_IRQ },
	};
	struct platform_device_info sa1111_devinfo = {
		.parent = &dev->dev,
		.name = "sa1111",
		.id = 0,
		.res = sa1111_resources,
		.num_res = ARRAY_SIZE(sa1111_resources),
		.data = &sa1111_info,
		.size_data = sizeof(sa1111_info),
		.dma_mask = 0xffffffffUL,
	};
	struct resource smc91x_resources[] = {
		DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS,
			0x02000000, "smc91x-regs"),
		DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS + 0x02000000,
			0x02000000, "smc91x-attrib"),
		{ .flags = IORESOURCE_IRQ },
	};
	struct platform_device_info smc91x_devinfo = {
		.parent = &dev->dev,
		.name = "smc91x",
		.id = 0,
		.res = smc91x_resources,
		.num_res = ARRAY_SIZE(smc91x_resources),
	};
	int ret, irq;

	if (nep_base)
		return -EBUSY;

	irq = ret = platform_get_irq(dev, 0);
	if (ret < 0)
		goto err_alloc;

	nep_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
	smc91x_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
	sa1111_res = platform_get_resource(dev, IORESOURCE_MEM, 2);
	if (!nep_res || !smc91x_res || !sa1111_res) {
		ret = -ENXIO;
		goto err_alloc;
	}

	d = kzalloc(sizeof(*d), GFP_KERNEL);
	if (!d) {
		ret = -ENOMEM;
		goto err_alloc;
	}

	d->base = ioremap(nep_res->start, SZ_4K);
	if (!d->base) {
		ret = -ENOMEM;
		goto err_ioremap;
	}

	if (readb_relaxed(d->base + WHOAMI) != 0x11) {
		dev_warn(&dev->dev, "Neponset board detected, but wrong ID: %02x\n",
			 readb_relaxed(d->base + WHOAMI));
		ret = -ENODEV;
		goto err_id;
	}

	ret = irq_alloc_descs(-1, IRQ_BOARD_START, NEP_IRQ_NR, -1);
	if (ret <= 0) {
		dev_err(&dev->dev, "unable to allocate %u irqs: %d\n",
			NEP_IRQ_NR, ret);
		if (ret == 0)
			ret = -ENOMEM;
		goto err_irq_alloc;
	}

	d->irq_base = ret;

	irq_set_chip_and_handler(d->irq_base + NEP_IRQ_SMC91X, &nochip,
		handle_simple_irq);
	set_irq_flags(d->irq_base + NEP_IRQ_SMC91X, IRQF_VALID | IRQF_PROBE);
	irq_set_chip_and_handler(d->irq_base + NEP_IRQ_USAR, &nochip,
		handle_simple_irq);
	set_irq_flags(d->irq_base + NEP_IRQ_USAR, IRQF_VALID | IRQF_PROBE);
	irq_set_chip(d->irq_base + NEP_IRQ_SA1111, &nochip);

	irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
	irq_set_handler_data(irq, d);
	irq_set_chained_handler(irq, neponset_irq_handler);

	/*
	 * We would set IRQ_GPIO25 to be a wake-up IRQ, but unfortunately
	 * something on the Neponset activates this IRQ on sleep (eth?)
	 */
#if 0
	enable_irq_wake(irq);
#endif

	dev_info(&dev->dev, "Neponset daughter board, providing IRQ%u-%u\n",
		 d->irq_base, d->irq_base + NEP_IRQ_NR - 1);
	nep_base = d->base;

	sa1100_register_uart_fns(&neponset_port_fns);

	/* Ensure that the memory bus request/grant signals are setup */
	sa1110_mb_disable();

	/* Disable GPIO 0/1 drivers so the buttons work on the Assabet */
	writeb_relaxed(NCR_GP01_OFF, d->base + NCR_0);

	sa1111_resources[0].parent = sa1111_res;
	sa1111_resources[1].start = d->irq_base + NEP_IRQ_SA1111;
	sa1111_resources[1].end = d->irq_base + NEP_IRQ_SA1111;
	d->sa1111 = platform_device_register_full(&sa1111_devinfo);

	smc91x_resources[0].parent = smc91x_res;
	smc91x_resources[1].parent = smc91x_res;
	smc91x_resources[2].start = d->irq_base + NEP_IRQ_SMC91X;
	smc91x_resources[2].end = d->irq_base + NEP_IRQ_SMC91X;
	d->smc91x = platform_device_register_full(&smc91x_devinfo);

	platform_set_drvdata(dev, d);

	return 0;

 err_irq_alloc:
 err_id:
	iounmap(d->base);
 err_ioremap:
	kfree(d);
 err_alloc:
	return ret;
}

static int neponset_remove(struct platform_device *dev)
{
	struct neponset_drvdata *d = platform_get_drvdata(dev);
	int irq = platform_get_irq(dev, 0);

	if (!IS_ERR(d->sa1111))
		platform_device_unregister(d->sa1111);
	if (!IS_ERR(d->smc91x))
		platform_device_unregister(d->smc91x);
	irq_set_chained_handler(irq, NULL);
	irq_free_descs(d->irq_base, NEP_IRQ_NR);
	nep_base = NULL;
	iounmap(d->base);
	kfree(d);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int neponset_suspend(struct device *dev)
{
	struct neponset_drvdata *d = dev_get_drvdata(dev);

	d->ncr0 = readb_relaxed(d->base + NCR_0);
	d->mdm_ctl_0 = readb_relaxed(d->base + MDM_CTL_0);

	return 0;
}

static int neponset_resume(struct device *dev)
{
	struct neponset_drvdata *d = dev_get_drvdata(dev);

	writeb_relaxed(d->ncr0, d->base + NCR_0);
	writeb_relaxed(d->mdm_ctl_0, d->base + MDM_CTL_0);

	return 0;
}

static const struct dev_pm_ops neponset_pm_ops = {
	.suspend_noirq = neponset_suspend,
	.resume_noirq = neponset_resume,
	.freeze_noirq = neponset_suspend,
	.restore_noirq = neponset_resume,
};
#define PM_OPS &neponset_pm_ops
#else
#define PM_OPS NULL
#endif

static struct platform_driver neponset_device_driver = {
	.probe		= neponset_probe,
	.remove		= neponset_remove,
	.driver		= {
		.name	= "neponset",
		.owner	= THIS_MODULE,
		.pm	= PM_OPS,
	},
};

static int __init neponset_init(void)
{
	return platform_driver_register(&neponset_device_driver);
}

subsys_initcall(neponset_init);
Commit	Line	Data
1da177e4 LT	1	/*
1da177e4 LT	2	* linux/arch/arm/mach-sa1100/neponset.c
1da177e4	3	*/
9590e898	4	#include <linux/err.h>
1da177e4	5	#include <linux/init.h>
1da177e4	6	#include <linux/ioport.h>
ced8d21c	7	#include <linux/irq.h>
92e617d9	8	#include <linux/kernel.h>
ae14c2e2	9	#include <linux/module.h>
6920b5a7	10	#include <linux/platform_data/sa11x0-serial.h>
d052d1be	11	#include <linux/platform_device.h>
51f93390	12	#include <linux/pm.h>
92e617d9	13	#include <linux/serial_core.h>
ae14c2e2	14	#include <linux/slab.h>
1da177e4	15
1da177e4	16	#include <asm/mach-types.h>
1da177e4	17	#include <asm/mach/map.h>
1da177e4 LT	18	#include <asm/hardware/sa1111.h>
	19	#include <asm/sizes.h>
	20
92e617d9 RK	21	#include <mach/hardware.h>
	22	#include <mach/assabet.h>
	23	#include <mach/neponset.h>
f314f33b	24	#include <mach/irqs.h>
92e617d9	25
ced8d21c RK	26	#define NEP_IRQ_SMC91X 0
	27	#define NEP_IRQ_USAR 1
	28	#define NEP_IRQ_SA1111 2
	29	#define NEP_IRQ_NR 3
	30
f942b0fd RK	31	#define WHOAMI 0x00
	32	#define LEDS 0x10
	33	#define SWPK 0x20
	34	#define IRR 0x24
	35	#define KP_Y_IN 0x80
	36	#define KP_X_OUT 0x90
	37	#define NCR_0 0xa0
	38	#define MDM_CTL_0 0xb0
	39	#define MDM_CTL_1 0xb4
	40	#define AUD_CTL 0xc0
	41
	42	#define IRR_ETHERNET (1 << 0)
	43	#define IRR_USAR (1 << 1)
	44	#define IRR_SA1111 (1 << 2)
	45
	46	#define MDM_CTL0_RTS1 (1 << 0)
	47	#define MDM_CTL0_DTR1 (1 << 1)
	48	#define MDM_CTL0_RTS2 (1 << 2)
	49	#define MDM_CTL0_DTR2 (1 << 3)
	50
	51	#define MDM_CTL1_CTS1 (1 << 0)
	52	#define MDM_CTL1_DSR1 (1 << 1)
	53	#define MDM_CTL1_DCD1 (1 << 2)
	54	#define MDM_CTL1_CTS2 (1 << 3)
	55	#define MDM_CTL1_DSR2 (1 << 4)
	56	#define MDM_CTL1_DCD2 (1 << 5)
	57
	58	#define AUD_SEL_1341 (1 << 0)
	59	#define AUD_MUTE_1341 (1 << 1)
	60
bab50a35 RK	61	extern void sa1110_mb_disable(void);
bab50a35 RK	62
ae14c2e2	63	struct neponset_drvdata {
f942b0fd	64	void __iomem *base;
9590e898 RK	65	struct platform_device *sa1111;
9590e898 RK	66	struct platform_device *smc91x;
ced8d21c	67	unsigned irq_base;
ae14c2e2 RK	68	#ifdef CONFIG_PM_SLEEP
	69	u32 ncr0;
	70	u32 mdm_ctl_0;
	71	#endif
	72	};
	73
f942b0fd RK	74	static void __iomem *nep_base;
f942b0fd RK	75
6ad1b614 RK	76	void neponset_ncr_frob(unsigned int mask, unsigned int val)
6ad1b614 RK	77	{
f942b0fd RK	78	void __iomem *base = nep_base;
	79
	80	if (base) {
	81	unsigned long flags;
	82	unsigned v;
	83
	84	local_irq_save(flags);
	85	v = readb_relaxed(base + NCR_0);
	86	writeb_relaxed((v & ~mask) \| val, base + NCR_0);
	87	local_irq_restore(flags);
	88	} else {
	89	WARN(1, "nep_base unset\n");
	90	}
6ad1b614	91	}
ef0c1484	92	EXPORT_SYMBOL(neponset_ncr_frob);
6ad1b614	93
92e617d9 RK	94	static void neponset_set_mctrl(struct uart_port *port, u_int mctrl)
92e617d9 RK	95	{
f942b0fd RK	96	void __iomem *base = nep_base;
	97	u_int mdm_ctl0;
	98
	99	if (!base)
	100	return;
92e617d9	101
f942b0fd	102	mdm_ctl0 = readb_relaxed(base + MDM_CTL_0);
92e617d9 RK	103	if (port->mapbase == _Ser1UTCR0) {
	104	if (mctrl & TIOCM_RTS)
	105	mdm_ctl0 &= ~MDM_CTL0_RTS2;
	106	else
	107	mdm_ctl0 \|= MDM_CTL0_RTS2;
	108
	109	if (mctrl & TIOCM_DTR)
	110	mdm_ctl0 &= ~MDM_CTL0_DTR2;
	111	else
	112	mdm_ctl0 \|= MDM_CTL0_DTR2;
	113	} else if (port->mapbase == _Ser3UTCR0) {
	114	if (mctrl & TIOCM_RTS)
	115	mdm_ctl0 &= ~MDM_CTL0_RTS1;
	116	else
	117	mdm_ctl0 \|= MDM_CTL0_RTS1;
	118
	119	if (mctrl & TIOCM_DTR)
	120	mdm_ctl0 &= ~MDM_CTL0_DTR1;
	121	else
	122	mdm_ctl0 \|= MDM_CTL0_DTR1;
	123	}
	124
f942b0fd	125	writeb_relaxed(mdm_ctl0, base + MDM_CTL_0);
92e617d9 RK	126	}
	127
	128	static u_int neponset_get_mctrl(struct uart_port *port)
	129	{
f942b0fd	130	void __iomem *base = nep_base;
92e617d9	131	u_int ret = TIOCM_CD \| TIOCM_CTS \| TIOCM_DSR;
f942b0fd	132	u_int mdm_ctl1;
92e617d9	133
f942b0fd RK	134	if (!base)
	135	return ret;
	136
	137	mdm_ctl1 = readb_relaxed(base + MDM_CTL_1);
92e617d9 RK	138	if (port->mapbase == _Ser1UTCR0) {
	139	if (mdm_ctl1 & MDM_CTL1_DCD2)
	140	ret &= ~TIOCM_CD;
	141	if (mdm_ctl1 & MDM_CTL1_CTS2)
	142	ret &= ~TIOCM_CTS;
	143	if (mdm_ctl1 & MDM_CTL1_DSR2)
	144	ret &= ~TIOCM_DSR;
	145	} else if (port->mapbase == _Ser3UTCR0) {
	146	if (mdm_ctl1 & MDM_CTL1_DCD1)
	147	ret &= ~TIOCM_CD;
	148	if (mdm_ctl1 & MDM_CTL1_CTS1)
	149	ret &= ~TIOCM_CTS;
	150	if (mdm_ctl1 & MDM_CTL1_DSR1)
	151	ret &= ~TIOCM_DSR;
	152	}
	153
	154	return ret;
	155	}
	156
351a102d	157	static struct sa1100_port_fns neponset_port_fns = {
92e617d9 RK	158	.set_mctrl = neponset_set_mctrl,
	159	.get_mctrl = neponset_get_mctrl,
	160	};
	161
1da177e4 LT	162	/*
	163	* Install handler for Neponset IRQ. Note that we have to loop here
	164	* since the ETHERNET and USAR IRQs are level based, and we need to
	165	* ensure that the IRQ signal is deasserted before returning. This
	166	* is rather unfortunate.
	167	*/
ced8d21c	168	static void neponset_irq_handler(unsigned int irq, struct irq_desc *desc)
1da177e4	169	{
ced8d21c	170	struct neponset_drvdata *d = irq_desc_get_handler_data(desc);
1da177e4 LT	171	unsigned int irr;
	172
	173	while (1) {
1da177e4 LT	174	/*
	175	* Acknowledge the parent IRQ.
	176	*/
c4e8964e	177	desc->irq_data.chip->irq_ack(&desc->irq_data);
1da177e4 LT	178
	179	/*
	180	* Read the interrupt reason register. Let's have all
	181	* active IRQ bits high. Note: there is a typo in the
	182	* Neponset user's guide for the SA1111 IRR level.
	183	*/
f942b0fd RK	184	irr = readb_relaxed(d->base + IRR);
f942b0fd RK	185	irr ^= IRR_ETHERNET \| IRR_USAR;
1da177e4 LT	186
	187	if ((irr & (IRR_ETHERNET \| IRR_USAR \| IRR_SA1111)) == 0)
	188	break;
	189
	190	/*
	191	* Since there is no individual mask, we have to
	192	* mask the parent IRQ. This is safe, since we'll
	193	* recheck the register for any pending IRQs.
	194	*/
	195	if (irr & (IRR_ETHERNET \| IRR_USAR)) {
c4e8964e	196	desc->irq_data.chip->irq_mask(&desc->irq_data);
1da177e4	197
d782f33d RK	198	/*
	199	* Ack the interrupt now to prevent re-entering
	200	* this neponset handler. Again, this is safe
	201	* since we'll check the IRR register prior to
	202	* leaving.
	203	*/
c4e8964e	204	desc->irq_data.chip->irq_ack(&desc->irq_data);
d782f33d	205
ced8d21c RK	206	if (irr & IRR_ETHERNET)
ced8d21c RK	207	generic_handle_irq(d->irq_base + NEP_IRQ_SMC91X);
1da177e4	208
ced8d21c RK	209	if (irr & IRR_USAR)
ced8d21c RK	210	generic_handle_irq(d->irq_base + NEP_IRQ_USAR);
1da177e4	211
c4e8964e	212	desc->irq_data.chip->irq_unmask(&desc->irq_data);
1da177e4 LT	213	}
1da177e4 LT	214
ced8d21c RK	215	if (irr & IRR_SA1111)
ced8d21c RK	216	generic_handle_irq(d->irq_base + NEP_IRQ_SA1111);
1da177e4 LT	217	}
	218	}
	219
ced8d21c	220	/* Yes, we really do not have any kind of masking or unmasking */
71045520 RK	221	static void nochip_noop(struct irq_data *irq)
	222	{
	223	}
	224
	225	static struct irq_chip nochip = {
	226	.name = "neponset",
	227	.irq_ack = nochip_noop,
	228	.irq_mask = nochip_noop,
	229	.irq_unmask = nochip_noop,
	230	};
	231
92e617d9	232	static struct sa1111_platform_data sa1111_info = {
07be45f5	233	.disable_devs = SA1111_DEVID_PS2_MSE,
92e617d9 RK	234	};
92e617d9 RK	235
351a102d	236	static int neponset_probe(struct platform_device *dev)
1da177e4	237	{
ae14c2e2	238	struct neponset_drvdata *d;
f942b0fd	239	struct resource nep_res, sa1111_res, *smc91x_res;
ced8d21c RK	240	struct resource sa1111_resources[] = {
	241	DEFINE_RES_MEM(0x40000000, SZ_8K),
	242	{ .flags = IORESOURCE_IRQ },
	243	};
9590e898 RK	244	struct platform_device_info sa1111_devinfo = {
	245	.parent = &dev->dev,
	246	.name = "sa1111",
	247	.id = 0,
	248	.res = sa1111_resources,
	249	.num_res = ARRAY_SIZE(sa1111_resources),
	250	.data = &sa1111_info,
	251	.size_data = sizeof(sa1111_info),
	252	.dma_mask = 0xffffffffUL,
	253	};
ced8d21c RK	254	struct resource smc91x_resources[] = {
	255	DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS,
	256	0x02000000, "smc91x-regs"),
	257	DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS + 0x02000000,
	258	0x02000000, "smc91x-attrib"),
	259	{ .flags = IORESOURCE_IRQ },
	260	};
9590e898 RK	261	struct platform_device_info smc91x_devinfo = {
	262	.parent = &dev->dev,
	263	.name = "smc91x",
	264	.id = 0,
	265	.res = smc91x_resources,
	266	.num_res = ARRAY_SIZE(smc91x_resources),
	267	};
b6bdfcf5 RK	268	int ret, irq;
b6bdfcf5 RK	269
f942b0fd RK	270	if (nep_base)
	271	return -EBUSY;
	272
b6bdfcf5 RK	273	irq = ret = platform_get_irq(dev, 0);
	274	if (ret < 0)
	275	goto err_alloc;
ae14c2e2	276
f942b0fd	277	nep_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
d2e539a5 RK	278	smc91x_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
d2e539a5 RK	279	sa1111_res = platform_get_resource(dev, IORESOURCE_MEM, 2);
f942b0fd	280	if (!nep_res \|\| !smc91x_res \|\| !sa1111_res) {
d2e539a5 RK	281	ret = -ENXIO;
	282	goto err_alloc;
	283	}
	284
ae14c2e2 RK	285	d = kzalloc(sizeof(*d), GFP_KERNEL);
	286	if (!d) {
	287	ret = -ENOMEM;
	288	goto err_alloc;
	289	}
	290
f942b0fd RK	291	d->base = ioremap(nep_res->start, SZ_4K);
	292	if (!d->base) {
	293	ret = -ENOMEM;
	294	goto err_ioremap;
	295	}
	296
	297	if (readb_relaxed(d->base + WHOAMI) != 0x11) {
	298	dev_warn(&dev->dev, "Neponset board detected, but wrong ID: %02x\n",
	299	readb_relaxed(d->base + WHOAMI));
	300	ret = -ENODEV;
	301	goto err_id;
	302	}
	303
ced8d21c RK	304	ret = irq_alloc_descs(-1, IRQ_BOARD_START, NEP_IRQ_NR, -1);
	305	if (ret <= 0) {
	306	dev_err(&dev->dev, "unable to allocate %u irqs: %d\n",
	307	NEP_IRQ_NR, ret);
	308	if (ret == 0)
	309	ret = -ENOMEM;
	310	goto err_irq_alloc;
	311	}
	312
	313	d->irq_base = ret;
	314
	315	irq_set_chip_and_handler(d->irq_base + NEP_IRQ_SMC91X, &nochip,
	316	handle_simple_irq);
	317	set_irq_flags(d->irq_base + NEP_IRQ_SMC91X, IRQF_VALID \| IRQF_PROBE);
	318	irq_set_chip_and_handler(d->irq_base + NEP_IRQ_USAR, &nochip,
	319	handle_simple_irq);
	320	set_irq_flags(d->irq_base + NEP_IRQ_USAR, IRQF_VALID \| IRQF_PROBE);
	321	irq_set_chip(d->irq_base + NEP_IRQ_SA1111, &nochip);
1da177e4	322
b6bdfcf5 RK	323	irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
	324	irq_set_handler_data(irq, d);
	325	irq_set_chained_handler(irq, neponset_irq_handler);
1da177e4 LT	326
1da177e4 LT	327	/*
ced8d21c RK	328	* We would set IRQ_GPIO25 to be a wake-up IRQ, but unfortunately
ced8d21c RK	329	* something on the Neponset activates this IRQ on sleep (eth?)
1da177e4 LT	330	*/
1da177e4 LT	331	#if 0
b6bdfcf5	332	enable_irq_wake(irq);
1da177e4 LT	333	#endif
1da177e4 LT	334
ced8d21c RK	335	dev_info(&dev->dev, "Neponset daughter board, providing IRQ%u-%u\n",
ced8d21c RK	336	d->irq_base, d->irq_base + NEP_IRQ_NR - 1);
f942b0fd	337	nep_base = d->base;
1da177e4	338
ced8d21c RK	339	sa1100_register_uart_fns(&neponset_port_fns);
ced8d21c RK	340
bab50a35 RK	341	/* Ensure that the memory bus request/grant signals are setup */
	342	sa1110_mb_disable();
	343
ced8d21c	344	/* Disable GPIO 0/1 drivers so the buttons work on the Assabet */
f942b0fd	345	writeb_relaxed(NCR_GP01_OFF, d->base + NCR_0);
1da177e4	346
d2e539a5	347	sa1111_resources[0].parent = sa1111_res;
ced8d21c RK	348	sa1111_resources[1].start = d->irq_base + NEP_IRQ_SA1111;
ced8d21c RK	349	sa1111_resources[1].end = d->irq_base + NEP_IRQ_SA1111;
9590e898	350	d->sa1111 = platform_device_register_full(&sa1111_devinfo);
ced8d21c	351
d2e539a5 RK	352	smc91x_resources[0].parent = smc91x_res;
d2e539a5 RK	353	smc91x_resources[1].parent = smc91x_res;
ced8d21c RK	354	smc91x_resources[2].start = d->irq_base + NEP_IRQ_SMC91X;
ced8d21c RK	355	smc91x_resources[2].end = d->irq_base + NEP_IRQ_SMC91X;
9590e898 RK	356	d->smc91x = platform_device_register_full(&smc91x_devinfo);
9590e898 RK	357
ae14c2e2 RK	358	platform_set_drvdata(dev, d);
ae14c2e2 RK	359
1da177e4	360	return 0;
ae14c2e2	361
ced8d21c	362	err_irq_alloc:
f942b0fd RK	363	err_id:
	364	iounmap(d->base);
	365	err_ioremap:
ced8d21c	366	kfree(d);
ae14c2e2 RK	367	err_alloc:
ae14c2e2 RK	368	return ret;
1da177e4 LT	369	}
1da177e4 LT	370
351a102d	371	static int neponset_remove(struct platform_device *dev)
ae14c2e2 RK	372	{
ae14c2e2 RK	373	struct neponset_drvdata *d = platform_get_drvdata(dev);
b6bdfcf5	374	int irq = platform_get_irq(dev, 0);
1da177e4	375
9590e898 RK	376	if (!IS_ERR(d->sa1111))
	377	platform_device_unregister(d->sa1111);
	378	if (!IS_ERR(d->smc91x))
	379	platform_device_unregister(d->smc91x);
b6bdfcf5	380	irq_set_chained_handler(irq, NULL);
ced8d21c	381	irq_free_descs(d->irq_base, NEP_IRQ_NR);
f942b0fd RK	382	nep_base = NULL;
f942b0fd RK	383	iounmap(d->base);
ae14c2e2 RK	384	kfree(d);
	385
	386	return 0;
	387	}
93160c63	388
51f93390 RK	389	#ifdef CONFIG_PM_SLEEP
51f93390 RK	390	static int neponset_suspend(struct device *dev)
1da177e4	391	{
51f93390	392	struct neponset_drvdata *d = dev_get_drvdata(dev);
ae14c2e2	393
f942b0fd RK	394	d->ncr0 = readb_relaxed(d->base + NCR_0);
f942b0fd RK	395	d->mdm_ctl_0 = readb_relaxed(d->base + MDM_CTL_0);
1da177e4 LT	396
	397	return 0;
	398	}
	399
51f93390	400	static int neponset_resume(struct device *dev)
1da177e4	401	{
51f93390	402	struct neponset_drvdata *d = dev_get_drvdata(dev);
ae14c2e2	403
f942b0fd RK	404	writeb_relaxed(d->ncr0, d->base + NCR_0);
f942b0fd RK	405	writeb_relaxed(d->mdm_ctl_0, d->base + MDM_CTL_0);
1da177e4 LT	406
	407	return 0;
	408	}
	409
51f93390 RK	410	static const struct dev_pm_ops neponset_pm_ops = {
	411	.suspend_noirq = neponset_suspend,
	412	.resume_noirq = neponset_resume,
	413	.freeze_noirq = neponset_suspend,
	414	.restore_noirq = neponset_resume,
	415	};
	416	#define PM_OPS &neponset_pm_ops
1da177e4	417	#else
51f93390	418	#define PM_OPS NULL
1da177e4 LT	419	#endif
1da177e4 LT	420
3ae5eaec	421	static struct platform_driver neponset_device_driver = {
1da177e4	422	.probe = neponset_probe,
351a102d	423	.remove = neponset_remove,
3ae5eaec RK	424	.driver = {
3ae5eaec RK	425	.name = "neponset",
398e58d0	426	.owner = THIS_MODULE,
51f93390	427	.pm = PM_OPS,
3ae5eaec	428	},
1da177e4 LT	429	};
1da177e4 LT	430
1da177e4 LT	431	static int __init neponset_init(void)
1da177e4 LT	432	{
bab50a35	433	return platform_driver_register(&neponset_device_driver);
1da177e4 LT	434	}
	435
	436	subsys_initcall(neponset_init);