[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-sa1100 / generic.c

/*
 * linux/arch/arm/mach-sa1100/generic.c
 *
 * Author: Nicolas Pitre
 *
 * Code common to all SA11x0 machines.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/gpio.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/pm.h>
#include <linux/cpufreq.h>
#include <linux/ioport.h>
#include <linux/platform_device.h>

#include <video/sa1100fb.h>

#include <asm/div64.h>
#include <asm/mach/map.h>
#include <asm/mach/flash.h>
#include <asm/irq.h>
#include <asm/system_misc.h>

#include <mach/hardware.h>
#include <mach/irqs.h>
#include <mach/reset.h>

#include "generic.h"

unsigned int reset_status;
EXPORT_SYMBOL(reset_status);

#define NR_FREQS	16

/*
 * This table is setup for a 3.6864MHz Crystal.
 */
static const unsigned short cclk_frequency_100khz[NR_FREQS] = {
	 590,	/*  59.0 MHz */
	 737,	/*  73.7 MHz */
	 885,	/*  88.5 MHz */
	1032,	/* 103.2 MHz */
	1180,	/* 118.0 MHz */
	1327,	/* 132.7 MHz */
	1475,	/* 147.5 MHz */
	1622,	/* 162.2 MHz */
	1769,	/* 176.9 MHz */
	1917,	/* 191.7 MHz */
	2064,	/* 206.4 MHz */
	2212,	/* 221.2 MHz */
	2359,	/* 235.9 MHz */
	2507,	/* 250.7 MHz */
	2654,	/* 265.4 MHz */
	2802	/* 280.2 MHz */
};

/* rounds up(!)  */
unsigned int sa11x0_freq_to_ppcr(unsigned int khz)
{
	int i;

	khz /= 100;

	for (i = 0; i < NR_FREQS; i++)
		if (cclk_frequency_100khz[i] >= khz)
			break;

	return i;
}

unsigned int sa11x0_ppcr_to_freq(unsigned int idx)
{
	unsigned int freq = 0;
	if (idx < NR_FREQS)
		freq = cclk_frequency_100khz[idx] * 100;
	return freq;
}


/* make sure that only the "userspace" governor is run -- anything else wouldn't make sense on
 * this platform, anyway.
 */
int sa11x0_verify_speed(struct cpufreq_policy *policy)
{
	unsigned int tmp;
	if (policy->cpu)
		return -EINVAL;

	cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq);

	/* make sure that at least one frequency is within the policy */
	tmp = cclk_frequency_100khz[sa11x0_freq_to_ppcr(policy->min)] * 100;
	if (tmp > policy->max)
		policy->max = tmp;

	cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq);

	return 0;
}

unsigned int sa11x0_getspeed(unsigned int cpu)
{
	if (cpu)
		return 0;
	return cclk_frequency_100khz[PPCR & 0xf] * 100;
}

/*
 * Default power-off for SA1100
 */
static void sa1100_power_off(void)
{
	mdelay(100);
	local_irq_disable();
	/* disable internal oscillator, float CS lines */
	PCFR = (PCFR_OPDE | PCFR_FP | PCFR_FS);
	/* enable wake-up on GPIO0 (Assabet...) */
	PWER = GFER = GRER = 1;
	/*
	 * set scratchpad to zero, just in case it is used as a
	 * restart address by the bootloader.
	 */
	PSPR = 0;
	/* enter sleep mode */
	PMCR = PMCR_SF;
}

void sa11x0_restart(char mode, const char *cmd)
{
	clear_reset_status(RESET_STATUS_ALL);
	if (mode == 's') {
		/* Jump into ROM at address 0 */
		soft_restart(0);
	} else {
		/* Use on-chip reset capability */
		RSRR = RSRR_SWR;
	}
}

static void sa11x0_register_device(struct platform_device *dev, void *data)
{
	int err;
	dev->dev.platform_data = data;
	err = platform_device_register(dev);
	if (err)
		printk(KERN_ERR "Unable to register device %s: %d\n",
			dev->name, err);
}


static struct resource sa11x0udc_resources[] = {
	[0] = DEFINE_RES_MEM(__PREG(Ser0UDCCR), SZ_64K),
	[1] = DEFINE_RES_IRQ(IRQ_Ser0UDC),
};

static u64 sa11x0udc_dma_mask = 0xffffffffUL;

static struct platform_device sa11x0udc_device = {
	.name		= "sa11x0-udc",
	.id		= -1,
	.dev		= {
		.dma_mask = &sa11x0udc_dma_mask,
		.coherent_dma_mask = 0xffffffff,
	},
	.num_resources	= ARRAY_SIZE(sa11x0udc_resources),
	.resource	= sa11x0udc_resources,
};

static struct resource sa11x0uart1_resources[] = {
	[0] = DEFINE_RES_MEM(__PREG(Ser1UTCR0), SZ_64K),
	[1] = DEFINE_RES_IRQ(IRQ_Ser1UART),
};

static struct platform_device sa11x0uart1_device = {
	.name		= "sa11x0-uart",
	.id		= 1,
	.num_resources	= ARRAY_SIZE(sa11x0uart1_resources),
	.resource	= sa11x0uart1_resources,
};

static struct resource sa11x0uart3_resources[] = {
	[0] = DEFINE_RES_MEM(__PREG(Ser3UTCR0), SZ_64K),
	[1] = DEFINE_RES_IRQ(IRQ_Ser3UART),
};

static struct platform_device sa11x0uart3_device = {
	.name		= "sa11x0-uart",
	.id		= 3,
	.num_resources	= ARRAY_SIZE(sa11x0uart3_resources),
	.resource	= sa11x0uart3_resources,
};

static struct resource sa11x0mcp_resources[] = {
	[0] = DEFINE_RES_MEM(__PREG(Ser4MCCR0), SZ_64K),
	[1] = DEFINE_RES_MEM(__PREG(Ser4MCCR1), 4),
	[2] = DEFINE_RES_IRQ(IRQ_Ser4MCP),
};

static u64 sa11x0mcp_dma_mask = 0xffffffffUL;

static struct platform_device sa11x0mcp_device = {
	.name		= "sa11x0-mcp",
	.id		= -1,
	.dev = {
		.dma_mask = &sa11x0mcp_dma_mask,
		.coherent_dma_mask = 0xffffffff,
	},
	.num_resources	= ARRAY_SIZE(sa11x0mcp_resources),
	.resource	= sa11x0mcp_resources,
};

void __init sa11x0_ppc_configure_mcp(void)
{
	/* Setup the PPC unit for the MCP */
	PPDR &= ~PPC_RXD4;
	PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
	PSDR |= PPC_RXD4;
	PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
	PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
}

void sa11x0_register_mcp(struct mcp_plat_data *data)
{
	sa11x0_register_device(&sa11x0mcp_device, data);
}

static struct resource sa11x0ssp_resources[] = {
	[0] = DEFINE_RES_MEM(0x80070000, SZ_64K),
	[1] = DEFINE_RES_IRQ(IRQ_Ser4SSP),
};

static u64 sa11x0ssp_dma_mask = 0xffffffffUL;

static struct platform_device sa11x0ssp_device = {
	.name		= "sa11x0-ssp",
	.id		= -1,
	.dev = {
		.dma_mask = &sa11x0ssp_dma_mask,
		.coherent_dma_mask = 0xffffffff,
	},
	.num_resources	= ARRAY_SIZE(sa11x0ssp_resources),
	.resource	= sa11x0ssp_resources,
};

static struct resource sa11x0fb_resources[] = {
	[0] = DEFINE_RES_MEM(0xb0100000, SZ_64K),
	[1] = DEFINE_RES_IRQ(IRQ_LCD),
};

static struct platform_device sa11x0fb_device = {
	.name		= "sa11x0-fb",
	.id		= -1,
	.dev = {
		.coherent_dma_mask = 0xffffffff,
	},
	.num_resources	= ARRAY_SIZE(sa11x0fb_resources),
	.resource	= sa11x0fb_resources,
};

void sa11x0_register_lcd(struct sa1100fb_mach_info *inf)
{
	sa11x0_register_device(&sa11x0fb_device, inf);
}

static struct platform_device sa11x0pcmcia_device = {
	.name		= "sa11x0-pcmcia",
	.id		= -1,
};

static struct platform_device sa11x0mtd_device = {
	.name		= "sa1100-mtd",
	.id		= -1,
};

void sa11x0_register_mtd(struct flash_platform_data *flash,
			 struct resource *res, int nr)
{
	flash->name = "sa1100";
	sa11x0mtd_device.resource = res;
	sa11x0mtd_device.num_resources = nr;
	sa11x0_register_device(&sa11x0mtd_device, flash);
}

static struct resource sa11x0ir_resources[] = {
	DEFINE_RES_MEM(__PREG(Ser2UTCR0), 0x24),
	DEFINE_RES_MEM(__PREG(Ser2HSCR0), 0x1c),
	DEFINE_RES_MEM(__PREG(Ser2HSCR2), 0x04),
	DEFINE_RES_IRQ(IRQ_Ser2ICP),
};

static struct platform_device sa11x0ir_device = {
	.name		= "sa11x0-ir",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(sa11x0ir_resources),
	.resource	= sa11x0ir_resources,
};

void sa11x0_register_irda(struct irda_platform_data *irda)
{
	sa11x0_register_device(&sa11x0ir_device, irda);
}

static struct resource sa1100_rtc_resources[] = {
	DEFINE_RES_MEM(0x90010000, 0x40),
	DEFINE_RES_IRQ_NAMED(IRQ_RTC1Hz, "rtc 1Hz"),
	DEFINE_RES_IRQ_NAMED(IRQ_RTCAlrm, "rtc alarm"),
};

static struct platform_device sa11x0rtc_device = {
	.name		= "sa1100-rtc",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(sa1100_rtc_resources),
	.resource	= sa1100_rtc_resources,
};

static struct resource sa11x0dma_resources[] = {
	DEFINE_RES_MEM(DMA_PHYS, DMA_SIZE),
	DEFINE_RES_IRQ(IRQ_DMA0),
	DEFINE_RES_IRQ(IRQ_DMA1),
	DEFINE_RES_IRQ(IRQ_DMA2),
	DEFINE_RES_IRQ(IRQ_DMA3),
	DEFINE_RES_IRQ(IRQ_DMA4),
	DEFINE_RES_IRQ(IRQ_DMA5),
};

static u64 sa11x0dma_dma_mask = DMA_BIT_MASK(32);

static struct platform_device sa11x0dma_device = {
	.name		= "sa11x0-dma",
	.id		= -1,
	.dev = {
		.dma_mask = &sa11x0dma_dma_mask,
		.coherent_dma_mask = 0xffffffff,
	},
	.num_resources	= ARRAY_SIZE(sa11x0dma_resources),
	.resource	= sa11x0dma_resources,
};

static struct platform_device *sa11x0_devices[] __initdata = {
	&sa11x0udc_device,
	&sa11x0uart1_device,
	&sa11x0uart3_device,
	&sa11x0ssp_device,
	&sa11x0pcmcia_device,
	&sa11x0rtc_device,
	&sa11x0dma_device,
};

static int __init sa1100_init(void)
{
	pm_power_off = sa1100_power_off;
	return platform_add_devices(sa11x0_devices, ARRAY_SIZE(sa11x0_devices));
}

arch_initcall(sa1100_init);

void __init sa11x0_init_late(void)
{
	sa11x0_pm_init();
}

/*
 * Common I/O mapping:
 *
 * Typically, static virtual address mappings are as follow:
 *
 * 0xf0000000-0xf3ffffff:	miscellaneous stuff (CPLDs, etc.)
 * 0xf4000000-0xf4ffffff:	SA-1111
 * 0xf5000000-0xf5ffffff:	reserved (used by cache flushing area)
 * 0xf6000000-0xfffeffff:	reserved (internal SA1100 IO defined above)
 * 0xffff0000-0xffff0fff:	SA1100 exception vectors
 * 0xffff2000-0xffff2fff:	Minicache copy_user_page area
 *
 * Below 0xe8000000 is reserved for vm allocation.
 *
 * The machine specific code must provide the extra mapping beside the
 * default mapping provided here.
 */

static struct map_desc standard_io_desc[] __initdata = {
	{	/* PCM */
		.virtual	=  0xf8000000,
		.pfn		= __phys_to_pfn(0x80000000),
		.length		= 0x00100000,
		.type		= MT_DEVICE
	}, {	/* SCM */
		.virtual	=  0xfa000000,
		.pfn		= __phys_to_pfn(0x90000000),
		.length		= 0x00100000,
		.type		= MT_DEVICE
	}, {	/* MER */
		.virtual	=  0xfc000000,
		.pfn		= __phys_to_pfn(0xa0000000),
		.length		= 0x00100000,
		.type		= MT_DEVICE
	}, {	/* LCD + DMA */
		.virtual	=  0xfe000000,
		.pfn		= __phys_to_pfn(0xb0000000),
		.length		= 0x00200000,
		.type		= MT_DEVICE
	},
};

void __init sa1100_map_io(void)
{
	iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
}

/*
 * Disable the memory bus request/grant signals on the SA1110 to
 * ensure that we don't receive spurious memory requests.  We set
 * the MBGNT signal false to ensure the SA1111 doesn't own the
 * SDRAM bus.
 */
void sa1110_mb_disable(void)
{
	unsigned long flags;

	local_irq_save(flags);
	
	PGSR &= ~GPIO_MBGNT;
	GPCR = GPIO_MBGNT;
	GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;

	GAFR &= ~(GPIO_MBGNT | GPIO_MBREQ);

	local_irq_restore(flags);
}

/*
 * If the system is going to use the SA-1111 DMA engines, set up
 * the memory bus request/grant pins.
 */
void sa1110_mb_enable(void)
{
	unsigned long flags;

	local_irq_save(flags);

	PGSR &= ~GPIO_MBGNT;
	GPCR = GPIO_MBGNT;
	GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;

	GAFR |= (GPIO_MBGNT | GPIO_MBREQ);
	TUCR |= TUCR_MR;

	local_irq_restore(flags);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-sa1100/generic.c
	3	*
	4	* Author: Nicolas Pitre
	5	*
	6	* Code common to all SA11x0 machines.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
2f8163ba	12	#include <linux/gpio.h>
1da177e4 LT	13	#include <linux/module.h>
	14	#include <linux/kernel.h>
	15	#include <linux/init.h>
	16	#include <linux/delay.h>
7931d92f	17	#include <linux/dma-mapping.h>
1da177e4 LT	18	#include <linux/pm.h>
	19	#include <linux/cpufreq.h>
	20	#include <linux/ioport.h>
d052d1be	21	#include <linux/platform_device.h>
1da177e4	22
e1b7a72a RK	23	#include <video/sa1100fb.h>
e1b7a72a RK	24
1da177e4	25	#include <asm/div64.h>
1da177e4	26	#include <asm/mach/map.h>
14e66f76	27	#include <asm/mach/flash.h>
1da177e4	28	#include <asm/irq.h>
9f97da78	29	#include <asm/system_misc.h>
1da177e4	30
f314f33b RH	31	#include <mach/hardware.h>
f314f33b RH	32	#include <mach/irqs.h>
5b4918cc	33	#include <mach/reset.h>
f314f33b	34
1da177e4 LT	35	#include "generic.h"
1da177e4 LT	36
04fef228 EM	37	unsigned int reset_status;
	38	EXPORT_SYMBOL(reset_status);
	39
1da177e4 LT	40	#define NR_FREQS 16
	41
	42	/*
	43	* This table is setup for a 3.6864MHz Crystal.
	44	*/
	45	static const unsigned short cclk_frequency_100khz[NR_FREQS] = {
	46	590, /* 59.0 MHz */
	47	737, /* 73.7 MHz */
bda03086	48	885, /* 88.5 MHz */
1da177e4 LT	49	1032, /* 103.2 MHz */
	50	1180, /* 118.0 MHz */
	51	1327, /* 132.7 MHz */
	52	1475, /* 147.5 MHz */
	53	1622, /* 162.2 MHz */
	54	1769, /* 176.9 MHz */
	55	1917, /* 191.7 MHz */
	56	2064, /* 206.4 MHz */
	57	2212, /* 221.2 MHz */
bda03086 KE	58	2359, /* 235.9 MHz */
	59	2507, /* 250.7 MHz */
	60	2654, /* 265.4 MHz */
	61	2802 /* 280.2 MHz */
1da177e4 LT	62	};
1da177e4 LT	63
1da177e4 LT	64	/* rounds up(!) */
	65	unsigned int sa11x0_freq_to_ppcr(unsigned int khz)
	66	{
	67	int i;
	68
	69	khz /= 100;
	70
	71	for (i = 0; i < NR_FREQS; i++)
	72	if (cclk_frequency_100khz[i] >= khz)
	73	break;
	74
	75	return i;
	76	}
	77
	78	unsigned int sa11x0_ppcr_to_freq(unsigned int idx)
	79	{
	80	unsigned int freq = 0;
	81	if (idx < NR_FREQS)
	82	freq = cclk_frequency_100khz[idx] * 100;
	83	return freq;
	84	}
	85
	86
	87	/* make sure that only the "userspace" governor is run -- anything else wouldn't make sense on
	88	* this platform, anyway.
	89	*/
	90	int sa11x0_verify_speed(struct cpufreq_policy *policy)
	91	{
	92	unsigned int tmp;
	93	if (policy->cpu)
	94	return -EINVAL;
	95
	96	cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq);
	97
	98	/* make sure that at least one frequency is within the policy */
	99	tmp = cclk_frequency_100khz[sa11x0_freq_to_ppcr(policy->min)] * 100;
	100	if (tmp > policy->max)
	101	policy->max = tmp;
	102
	103	cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq);
	104
	105	return 0;
	106	}
	107
	108	unsigned int sa11x0_getspeed(unsigned int cpu)
	109	{
	110	if (cpu)
	111	return 0;
	112	return cclk_frequency_100khz[PPCR & 0xf] * 100;
	113	}
	114
1da177e4 LT	115	/*
	116	* Default power-off for SA1100
	117	*/
	118	static void sa1100_power_off(void)
	119	{
	120	mdelay(100);
	121	local_irq_disable();
	122	/* disable internal oscillator, float CS lines */
	123	PCFR = (PCFR_OPDE \| PCFR_FP \| PCFR_FS);
	124	/* enable wake-up on GPIO0 (Assabet...) */
	125	PWER = GFER = GRER = 1;
	126	/*
	127	* set scratchpad to zero, just in case it is used as a
	128	* restart address by the bootloader.
	129	*/
	130	PSPR = 0;
	131	/* enter sleep mode */
	132	PMCR = PMCR_SF;
	133	}
	134
d9ca5839 RK	135	void sa11x0_restart(char mode, const char *cmd)
d9ca5839 RK	136	{
5b4918cc	137	clear_reset_status(RESET_STATUS_ALL);
d9ca5839 RK	138	if (mode == 's') {
	139	/* Jump into ROM at address 0 */
	140	soft_restart(0);
	141	} else {
	142	/* Use on-chip reset capability */
	143	RSRR = RSRR_SWR;
	144	}
	145	}
	146
7a5b4e16 RK	147	static void sa11x0_register_device(struct platform_device dev, void data)
	148	{
	149	int err;
	150	dev->dev.platform_data = data;
	151	err = platform_device_register(dev);
	152	if (err)
	153	printk(KERN_ERR "Unable to register device %s: %d\n",
	154	dev->name, err);
	155	}
	156
	157
1da177e4	158	static struct resource sa11x0udc_resources[] = {
a181099e RK	159	[0] = DEFINE_RES_MEM(__PREG(Ser0UDCCR), SZ_64K),
a181099e RK	160	[1] = DEFINE_RES_IRQ(IRQ_Ser0UDC),
1da177e4 LT	161	};
	162
	163	static u64 sa11x0udc_dma_mask = 0xffffffffUL;
	164
	165	static struct platform_device sa11x0udc_device = {
	166	.name = "sa11x0-udc",
	167	.id = -1,
	168	.dev = {
	169	.dma_mask = &sa11x0udc_dma_mask,
	170	.coherent_dma_mask = 0xffffffff,
	171	},
	172	.num_resources = ARRAY_SIZE(sa11x0udc_resources),
	173	.resource = sa11x0udc_resources,
	174	};
	175
	176	static struct resource sa11x0uart1_resources[] = {
a181099e RK	177	[0] = DEFINE_RES_MEM(__PREG(Ser1UTCR0), SZ_64K),
a181099e RK	178	[1] = DEFINE_RES_IRQ(IRQ_Ser1UART),
1da177e4 LT	179	};
	180
	181	static struct platform_device sa11x0uart1_device = {
	182	.name = "sa11x0-uart",
	183	.id = 1,
	184	.num_resources = ARRAY_SIZE(sa11x0uart1_resources),
	185	.resource = sa11x0uart1_resources,
	186	};
	187
	188	static struct resource sa11x0uart3_resources[] = {
a181099e RK	189	[0] = DEFINE_RES_MEM(__PREG(Ser3UTCR0), SZ_64K),
a181099e RK	190	[1] = DEFINE_RES_IRQ(IRQ_Ser3UART),
1da177e4 LT	191	};
	192
	193	static struct platform_device sa11x0uart3_device = {
	194	.name = "sa11x0-uart",
	195	.id = 3,
	196	.num_resources = ARRAY_SIZE(sa11x0uart3_resources),
	197	.resource = sa11x0uart3_resources,
	198	};
	199
	200	static struct resource sa11x0mcp_resources[] = {
a181099e	201	[0] = DEFINE_RES_MEM(__PREG(Ser4MCCR0), SZ_64K),
7256ecc2 RK	202	[1] = DEFINE_RES_MEM(__PREG(Ser4MCCR1), 4),
7256ecc2 RK	203	[2] = DEFINE_RES_IRQ(IRQ_Ser4MCP),
1da177e4 LT	204	};
	205
	206	static u64 sa11x0mcp_dma_mask = 0xffffffffUL;
	207
	208	static struct platform_device sa11x0mcp_device = {
	209	.name = "sa11x0-mcp",
	210	.id = -1,
	211	.dev = {
	212	.dma_mask = &sa11x0mcp_dma_mask,
	213	.coherent_dma_mask = 0xffffffff,
	214	},
	215	.num_resources = ARRAY_SIZE(sa11x0mcp_resources),
	216	.resource = sa11x0mcp_resources,
	217	};
	218
e36e26a8 RK	219	void __init sa11x0_ppc_configure_mcp(void)
	220	{
	221	/* Setup the PPC unit for the MCP */
	222	PPDR &= ~PPC_RXD4;
	223	PPDR \|= PPC_TXD4 \| PPC_SCLK \| PPC_SFRM;
	224	PSDR \|= PPC_RXD4;
	225	PSDR &= ~(PPC_TXD4 \| PPC_SCLK \| PPC_SFRM);
	226	PPSR &= ~(PPC_TXD4 \| PPC_SCLK \| PPC_SFRM);
	227	}
	228
7a5b4e16	229	void sa11x0_register_mcp(struct mcp_plat_data *data)
323cdfc1	230	{
7a5b4e16	231	sa11x0_register_device(&sa11x0mcp_device, data);
323cdfc1 RK	232	}
323cdfc1 RK	233
1da177e4	234	static struct resource sa11x0ssp_resources[] = {
a181099e RK	235	[0] = DEFINE_RES_MEM(0x80070000, SZ_64K),
a181099e RK	236	[1] = DEFINE_RES_IRQ(IRQ_Ser4SSP),
1da177e4 LT	237	};
	238
	239	static u64 sa11x0ssp_dma_mask = 0xffffffffUL;
	240
	241	static struct platform_device sa11x0ssp_device = {
	242	.name = "sa11x0-ssp",
	243	.id = -1,
	244	.dev = {
	245	.dma_mask = &sa11x0ssp_dma_mask,
	246	.coherent_dma_mask = 0xffffffff,
	247	},
	248	.num_resources = ARRAY_SIZE(sa11x0ssp_resources),
	249	.resource = sa11x0ssp_resources,
	250	};
	251
	252	static struct resource sa11x0fb_resources[] = {
a181099e RK	253	[0] = DEFINE_RES_MEM(0xb0100000, SZ_64K),
a181099e RK	254	[1] = DEFINE_RES_IRQ(IRQ_LCD),
1da177e4 LT	255	};
	256
	257	static struct platform_device sa11x0fb_device = {
	258	.name = "sa11x0-fb",
	259	.id = -1,
	260	.dev = {
	261	.coherent_dma_mask = 0xffffffff,
	262	},
	263	.num_resources = ARRAY_SIZE(sa11x0fb_resources),
	264	.resource = sa11x0fb_resources,
	265	};
	266
e1b7a72a RK	267	void sa11x0_register_lcd(struct sa1100fb_mach_info *inf)
	268	{
	269	sa11x0_register_device(&sa11x0fb_device, inf);
	270	}
	271
1da177e4 LT	272	static struct platform_device sa11x0pcmcia_device = {
	273	.name = "sa11x0-pcmcia",
	274	.id = -1,
	275	};
	276
	277	static struct platform_device sa11x0mtd_device = {
bcc8f3e0	278	.name = "sa1100-mtd",
1da177e4 LT	279	.id = -1,
	280	};
	281
7a5b4e16 RK	282	void sa11x0_register_mtd(struct flash_platform_data *flash,
7a5b4e16 RK	283	struct resource *res, int nr)
1da177e4	284	{
14e66f76	285	flash->name = "sa1100";
1da177e4 LT	286	sa11x0mtd_device.resource = res;
1da177e4 LT	287	sa11x0mtd_device.num_resources = nr;
7a5b4e16	288	sa11x0_register_device(&sa11x0mtd_device, flash);
1da177e4 LT	289	}
	290
	291	static struct resource sa11x0ir_resources[] = {
a181099e RK	292	DEFINE_RES_MEM(__PREG(Ser2UTCR0), 0x24),
	293	DEFINE_RES_MEM(__PREG(Ser2HSCR0), 0x1c),
	294	DEFINE_RES_MEM(__PREG(Ser2HSCR2), 0x04),
	295	DEFINE_RES_IRQ(IRQ_Ser2ICP),
1da177e4 LT	296	};
	297
	298	static struct platform_device sa11x0ir_device = {
	299	.name = "sa11x0-ir",
	300	.id = -1,
	301	.num_resources = ARRAY_SIZE(sa11x0ir_resources),
	302	.resource = sa11x0ir_resources,
	303	};
	304
7a5b4e16	305	void sa11x0_register_irda(struct irda_platform_data *irda)
1da177e4	306	{
7a5b4e16	307	sa11x0_register_device(&sa11x0ir_device, irda);
1da177e4 LT	308	}
1da177e4 LT	309
3888c090	310	static struct resource sa1100_rtc_resources[] = {
9f9d27e3	311	DEFINE_RES_MEM(0x90010000, 0x40),
3888c090 HZ	312	DEFINE_RES_IRQ_NAMED(IRQ_RTC1Hz, "rtc 1Hz"),
	313	DEFINE_RES_IRQ_NAMED(IRQ_RTCAlrm, "rtc alarm"),
	314	};
	315
e842f1c8 RP	316	static struct platform_device sa11x0rtc_device = {
	317	.name = "sa1100-rtc",
	318	.id = -1,
3888c090 HZ	319	.num_resources = ARRAY_SIZE(sa1100_rtc_resources),
3888c090 HZ	320	.resource = sa1100_rtc_resources,
e842f1c8 RP	321	};
e842f1c8 RP	322
7931d92f	323	static struct resource sa11x0dma_resources[] = {
c2132010	324	DEFINE_RES_MEM(DMA_PHYS, DMA_SIZE),
7931d92f RK	325	DEFINE_RES_IRQ(IRQ_DMA0),
	326	DEFINE_RES_IRQ(IRQ_DMA1),
	327	DEFINE_RES_IRQ(IRQ_DMA2),
	328	DEFINE_RES_IRQ(IRQ_DMA3),
	329	DEFINE_RES_IRQ(IRQ_DMA4),
	330	DEFINE_RES_IRQ(IRQ_DMA5),
	331	};
	332
	333	static u64 sa11x0dma_dma_mask = DMA_BIT_MASK(32);
	334
	335	static struct platform_device sa11x0dma_device = {
	336	.name = "sa11x0-dma",
	337	.id = -1,
	338	.dev = {
	339	.dma_mask = &sa11x0dma_dma_mask,
	340	.coherent_dma_mask = 0xffffffff,
	341	},
	342	.num_resources = ARRAY_SIZE(sa11x0dma_resources),
	343	.resource = sa11x0dma_resources,
	344	};
	345
1da177e4 LT	346	static struct platform_device *sa11x0_devices[] __initdata = {
	347	&sa11x0udc_device,
	348	&sa11x0uart1_device,
	349	&sa11x0uart3_device,
1da177e4 LT	350	&sa11x0ssp_device,
1da177e4 LT	351	&sa11x0pcmcia_device,
e842f1c8	352	&sa11x0rtc_device,
7931d92f	353	&sa11x0dma_device,
1da177e4 LT	354	};
	355
	356	static int __init sa1100_init(void)
	357	{
	358	pm_power_off = sa1100_power_off;
1da177e4 LT	359	return platform_add_devices(sa11x0_devices, ARRAY_SIZE(sa11x0_devices));
	360	}
	361
	362	arch_initcall(sa1100_init);
	363
7fea1ba5 SG	364	void __init sa11x0_init_late(void)
	365	{
	366	sa11x0_pm_init();
	367	}
1da177e4 LT	368
	369	/*
	370	* Common I/O mapping:
	371	*
	372	* Typically, static virtual address mappings are as follow:
	373	*
	374	* 0xf0000000-0xf3ffffff: miscellaneous stuff (CPLDs, etc.)
	375	* 0xf4000000-0xf4ffffff: SA-1111
	376	* 0xf5000000-0xf5ffffff: reserved (used by cache flushing area)
	377	* 0xf6000000-0xfffeffff: reserved (internal SA1100 IO defined above)
	378	* 0xffff0000-0xffff0fff: SA1100 exception vectors
	379	* 0xffff2000-0xffff2fff: Minicache copy_user_page area
	380	*
	381	* Below 0xe8000000 is reserved for vm allocation.
	382	*
	383	* The machine specific code must provide the extra mapping beside the
	384	* default mapping provided here.
	385	*/
	386
	387	static struct map_desc standard_io_desc[] __initdata = {
bda03086	388	{ /* PCM */
92519d82 DS	389	.virtual = 0xf8000000,
	390	.pfn = __phys_to_pfn(0x80000000),
	391	.length = 0x00100000,
	392	.type = MT_DEVICE
	393	}, { /* SCM */
	394	.virtual = 0xfa000000,
	395	.pfn = __phys_to_pfn(0x90000000),
	396	.length = 0x00100000,
	397	.type = MT_DEVICE
	398	}, { /* MER */
	399	.virtual = 0xfc000000,
	400	.pfn = __phys_to_pfn(0xa0000000),
	401	.length = 0x00100000,
	402	.type = MT_DEVICE
	403	}, { /* LCD + DMA */
	404	.virtual = 0xfe000000,
	405	.pfn = __phys_to_pfn(0xb0000000),
	406	.length = 0x00200000,
	407	.type = MT_DEVICE
	408	},
1da177e4 LT	409	};
	410
	411	void __init sa1100_map_io(void)
	412	{
	413	iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
	414	}
	415
	416	/*
	417	* Disable the memory bus request/grant signals on the SA1110 to
	418	* ensure that we don't receive spurious memory requests. We set
	419	* the MBGNT signal false to ensure the SA1111 doesn't own the
	420	* SDRAM bus.
	421	*/
80ea2065	422	void sa1110_mb_disable(void)
1da177e4 LT	423	{
	424	unsigned long flags;
	425
	426	local_irq_save(flags);
	427
	428	PGSR &= ~GPIO_MBGNT;
	429	GPCR = GPIO_MBGNT;
	430	GPDR = (GPDR & ~GPIO_MBREQ) \| GPIO_MBGNT;
	431
	432	GAFR &= ~(GPIO_MBGNT \| GPIO_MBREQ);
	433
	434	local_irq_restore(flags);
	435	}
	436
	437	/*
	438	* If the system is going to use the SA-1111 DMA engines, set up
	439	* the memory bus request/grant pins.
	440	*/
80ea2065	441	void sa1110_mb_enable(void)
1da177e4 LT	442	{
	443	unsigned long flags;
	444
	445	local_irq_save(flags);
	446
	447	PGSR &= ~GPIO_MBGNT;
	448	GPCR = GPIO_MBGNT;
	449	GPDR = (GPDR & ~GPIO_MBREQ) \| GPIO_MBGNT;
	450
	451	GAFR \|= (GPIO_MBGNT \| GPIO_MBREQ);
	452	TUCR \|= TUCR_MR;
	453
	454	local_irq_restore(flags);
	455	}
	456