Commit | Line | Data |
---|---|---|
ea5f5070 PB |
1 | /* linux/arch/arm/mach-s5pv210/gpiolib.c |
2 | * | |
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com/ | |
5 | * | |
6 | * S5PV210 - GPIOlib support | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/irq.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/gpio.h> | |
17 | #include <plat/gpio-core.h> | |
18 | #include <plat/gpio-cfg.h> | |
19 | #include <plat/gpio-cfg-helpers.h> | |
20 | #include <mach/map.h> | |
21 | ||
22 | static struct s3c_gpio_cfg gpio_cfg = { | |
23 | .set_config = s3c_gpio_setcfg_s3c64xx_4bit, | |
24 | .set_pull = s3c_gpio_setpull_updown, | |
25 | .get_pull = s3c_gpio_getpull_updown, | |
26 | }; | |
27 | ||
28 | static struct s3c_gpio_cfg gpio_cfg_noint = { | |
29 | .set_config = s3c_gpio_setcfg_s3c64xx_4bit, | |
30 | .set_pull = s3c_gpio_setpull_updown, | |
31 | .get_pull = s3c_gpio_getpull_updown, | |
32 | }; | |
33 | ||
34 | /* GPIO bank's base address given the index of the bank in the | |
35 | * list of all gpio banks. | |
36 | */ | |
37 | #define S5PV210_BANK_BASE(bank_nr) (S5P_VA_GPIO + ((bank_nr) * 0x20)) | |
38 | ||
39 | /* | |
40 | * Following are the gpio banks in v210. | |
41 | * | |
42 | * The 'config' member when left to NULL, is initialized to the default | |
43 | * structure gpio_cfg in the init function below. | |
44 | * | |
45 | * The 'base' member is also initialized in the init function below. | |
46 | * Note: The initialization of 'base' member of s3c_gpio_chip structure | |
47 | * uses the above macro and depends on the banks being listed in order here. | |
48 | */ | |
49 | static struct s3c_gpio_chip s5pv210_gpio_4bit[] = { | |
50 | { | |
51 | .chip = { | |
52 | .base = S5PV210_GPA0(0), | |
53 | .ngpio = S5PV210_GPIO_A0_NR, | |
54 | .label = "GPA0", | |
55 | }, | |
56 | }, { | |
57 | .chip = { | |
58 | .base = S5PV210_GPA1(0), | |
59 | .ngpio = S5PV210_GPIO_A1_NR, | |
60 | .label = "GPA1", | |
61 | }, | |
62 | }, { | |
63 | .chip = { | |
64 | .base = S5PV210_GPB(0), | |
65 | .ngpio = S5PV210_GPIO_B_NR, | |
66 | .label = "GPB", | |
67 | }, | |
68 | }, { | |
69 | .chip = { | |
70 | .base = S5PV210_GPC0(0), | |
71 | .ngpio = S5PV210_GPIO_C0_NR, | |
72 | .label = "GPC0", | |
73 | }, | |
74 | }, { | |
75 | .chip = { | |
76 | .base = S5PV210_GPC1(0), | |
77 | .ngpio = S5PV210_GPIO_C1_NR, | |
78 | .label = "GPC1", | |
79 | }, | |
80 | }, { | |
81 | .chip = { | |
82 | .base = S5PV210_GPD0(0), | |
83 | .ngpio = S5PV210_GPIO_D0_NR, | |
84 | .label = "GPD0", | |
85 | }, | |
86 | }, { | |
87 | .chip = { | |
88 | .base = S5PV210_GPD1(0), | |
89 | .ngpio = S5PV210_GPIO_D1_NR, | |
90 | .label = "GPD1", | |
91 | }, | |
92 | }, { | |
93 | .chip = { | |
94 | .base = S5PV210_GPE0(0), | |
95 | .ngpio = S5PV210_GPIO_E0_NR, | |
96 | .label = "GPE0", | |
97 | }, | |
98 | }, { | |
99 | .chip = { | |
100 | .base = S5PV210_GPE1(0), | |
101 | .ngpio = S5PV210_GPIO_E1_NR, | |
102 | .label = "GPE1", | |
103 | }, | |
104 | }, { | |
105 | .chip = { | |
106 | .base = S5PV210_GPF0(0), | |
107 | .ngpio = S5PV210_GPIO_F0_NR, | |
108 | .label = "GPF0", | |
109 | }, | |
110 | }, { | |
111 | .chip = { | |
112 | .base = S5PV210_GPF1(0), | |
113 | .ngpio = S5PV210_GPIO_F1_NR, | |
114 | .label = "GPF1", | |
115 | }, | |
116 | }, { | |
117 | .chip = { | |
118 | .base = S5PV210_GPF2(0), | |
119 | .ngpio = S5PV210_GPIO_F2_NR, | |
120 | .label = "GPF2", | |
121 | }, | |
122 | }, { | |
123 | .chip = { | |
124 | .base = S5PV210_GPF3(0), | |
125 | .ngpio = S5PV210_GPIO_F3_NR, | |
126 | .label = "GPF3", | |
127 | }, | |
128 | }, { | |
129 | .chip = { | |
130 | .base = S5PV210_GPG0(0), | |
131 | .ngpio = S5PV210_GPIO_G0_NR, | |
132 | .label = "GPG0", | |
133 | }, | |
134 | }, { | |
135 | .chip = { | |
136 | .base = S5PV210_GPG1(0), | |
137 | .ngpio = S5PV210_GPIO_G1_NR, | |
138 | .label = "GPG1", | |
139 | }, | |
140 | }, { | |
141 | .chip = { | |
142 | .base = S5PV210_GPG2(0), | |
143 | .ngpio = S5PV210_GPIO_G2_NR, | |
144 | .label = "GPG2", | |
145 | }, | |
146 | }, { | |
147 | .chip = { | |
148 | .base = S5PV210_GPG3(0), | |
149 | .ngpio = S5PV210_GPIO_G3_NR, | |
150 | .label = "GPG3", | |
151 | }, | |
152 | }, { | |
153 | .chip = { | |
154 | .base = S5PV210_GPI(0), | |
155 | .ngpio = S5PV210_GPIO_I_NR, | |
156 | .label = "GPI", | |
157 | }, | |
158 | }, { | |
159 | .chip = { | |
160 | .base = S5PV210_GPJ0(0), | |
161 | .ngpio = S5PV210_GPIO_J0_NR, | |
162 | .label = "GPJ0", | |
163 | }, | |
164 | }, { | |
165 | .chip = { | |
166 | .base = S5PV210_GPJ1(0), | |
167 | .ngpio = S5PV210_GPIO_J1_NR, | |
168 | .label = "GPJ1", | |
169 | }, | |
170 | }, { | |
171 | .chip = { | |
172 | .base = S5PV210_GPJ2(0), | |
173 | .ngpio = S5PV210_GPIO_J2_NR, | |
174 | .label = "GPJ2", | |
175 | }, | |
176 | }, { | |
177 | .chip = { | |
178 | .base = S5PV210_GPJ3(0), | |
179 | .ngpio = S5PV210_GPIO_J3_NR, | |
180 | .label = "GPJ3", | |
181 | }, | |
182 | }, { | |
183 | .chip = { | |
184 | .base = S5PV210_GPJ4(0), | |
185 | .ngpio = S5PV210_GPIO_J4_NR, | |
186 | .label = "GPJ4", | |
187 | }, | |
188 | }, { | |
189 | .config = &gpio_cfg_noint, | |
190 | .chip = { | |
191 | .base = S5PV210_MP01(0), | |
192 | .ngpio = S5PV210_GPIO_MP01_NR, | |
193 | .label = "MP01", | |
194 | }, | |
195 | }, { | |
196 | .config = &gpio_cfg_noint, | |
197 | .chip = { | |
198 | .base = S5PV210_MP02(0), | |
199 | .ngpio = S5PV210_GPIO_MP02_NR, | |
200 | .label = "MP02", | |
201 | }, | |
202 | }, { | |
203 | .config = &gpio_cfg_noint, | |
204 | .chip = { | |
205 | .base = S5PV210_MP03(0), | |
206 | .ngpio = S5PV210_GPIO_MP03_NR, | |
207 | .label = "MP03", | |
208 | }, | |
84543901 MS |
209 | }, { |
210 | .config = &gpio_cfg_noint, | |
211 | .chip = { | |
212 | .base = S5PV210_MP04(0), | |
213 | .ngpio = S5PV210_GPIO_MP04_NR, | |
214 | .label = "MP04", | |
215 | }, | |
216 | }, { | |
217 | .config = &gpio_cfg_noint, | |
218 | .chip = { | |
219 | .base = S5PV210_MP05(0), | |
220 | .ngpio = S5PV210_GPIO_MP05_NR, | |
221 | .label = "MP05", | |
222 | }, | |
ea5f5070 PB |
223 | }, { |
224 | .base = (S5P_VA_GPIO + 0xC00), | |
225 | .config = &gpio_cfg_noint, | |
226 | .chip = { | |
227 | .base = S5PV210_GPH0(0), | |
228 | .ngpio = S5PV210_GPIO_H0_NR, | |
229 | .label = "GPH0", | |
230 | }, | |
231 | }, { | |
232 | .base = (S5P_VA_GPIO + 0xC20), | |
233 | .config = &gpio_cfg_noint, | |
234 | .chip = { | |
235 | .base = S5PV210_GPH1(0), | |
236 | .ngpio = S5PV210_GPIO_H1_NR, | |
237 | .label = "GPH1", | |
238 | }, | |
239 | }, { | |
240 | .base = (S5P_VA_GPIO + 0xC40), | |
241 | .config = &gpio_cfg_noint, | |
242 | .chip = { | |
243 | .base = S5PV210_GPH2(0), | |
244 | .ngpio = S5PV210_GPIO_H2_NR, | |
245 | .label = "GPH2", | |
246 | }, | |
247 | }, { | |
248 | .base = (S5P_VA_GPIO + 0xC60), | |
249 | .config = &gpio_cfg_noint, | |
250 | .chip = { | |
251 | .base = S5PV210_GPH3(0), | |
252 | .ngpio = S5PV210_GPIO_H3_NR, | |
253 | .label = "GPH3", | |
254 | }, | |
255 | }, | |
256 | }; | |
257 | ||
258 | static __init int s5pv210_gpiolib_init(void) | |
259 | { | |
260 | struct s3c_gpio_chip *chip = s5pv210_gpio_4bit; | |
261 | int nr_chips = ARRAY_SIZE(s5pv210_gpio_4bit); | |
262 | int i = 0; | |
263 | ||
264 | for (i = 0; i < nr_chips; i++, chip++) { | |
265 | if (chip->config == NULL) | |
266 | chip->config = &gpio_cfg; | |
267 | if (chip->base == NULL) | |
268 | chip->base = S5PV210_BANK_BASE(i); | |
269 | } | |
270 | ||
271 | samsung_gpiolib_add_4bit_chips(s5pv210_gpio_4bit, nr_chips); | |
272 | ||
273 | return 0; | |
274 | } | |
275 | core_initcall(s5pv210_gpiolib_init); |