Commit | Line | Data |
---|---|---|
3109e550 KK |
1 | /* linux/arch/arm/mach-s5p64x0/clock.c |
2 | * | |
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com | |
5 | * | |
6 | * S5P64X0 - Clock support | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/init.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/list.h> | |
17 | #include <linux/errno.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/clk.h> | |
edbaa603 | 20 | #include <linux/device.h> |
3109e550 KK |
21 | #include <linux/io.h> |
22 | ||
23 | #include <mach/hardware.h> | |
24 | #include <mach/map.h> | |
25 | #include <mach/regs-clock.h> | |
26 | ||
27 | #include <plat/cpu-freq.h> | |
28 | #include <plat/clock.h> | |
29 | #include <plat/cpu.h> | |
30 | #include <plat/pll.h> | |
31 | #include <plat/s5p-clock.h> | |
32 | #include <plat/clock-clksrc.h> | |
95af214b KK |
33 | |
34 | #include "common.h" | |
3109e550 KK |
35 | |
36 | struct clksrc_clk clk_mout_apll = { | |
37 | .clk = { | |
38 | .name = "mout_apll", | |
39 | .id = -1, | |
40 | }, | |
41 | .sources = &clk_src_apll, | |
42 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 0, .size = 1 }, | |
43 | }; | |
44 | ||
45 | struct clksrc_clk clk_mout_mpll = { | |
46 | .clk = { | |
47 | .name = "mout_mpll", | |
48 | .id = -1, | |
49 | }, | |
50 | .sources = &clk_src_mpll, | |
51 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 1, .size = 1 }, | |
52 | }; | |
53 | ||
54 | struct clksrc_clk clk_mout_epll = { | |
55 | .clk = { | |
56 | .name = "mout_epll", | |
57 | .id = -1, | |
58 | }, | |
59 | .sources = &clk_src_epll, | |
60 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 2, .size = 1 }, | |
61 | }; | |
62 | ||
63 | enum perf_level { | |
64 | L0 = 532*1000, | |
65 | L1 = 266*1000, | |
66 | L2 = 133*1000, | |
67 | }; | |
68 | ||
69 | static const u32 clock_table[][3] = { | |
70 | /*{ARM_CLK, DIVarm, DIVhclk}*/ | |
71 | {L0 * 1000, (0 << ARM_DIV_RATIO_SHIFT), (3 << S5P64X0_CLKDIV0_HCLK_SHIFT)}, | |
72 | {L1 * 1000, (1 << ARM_DIV_RATIO_SHIFT), (1 << S5P64X0_CLKDIV0_HCLK_SHIFT)}, | |
73 | {L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P64X0_CLKDIV0_HCLK_SHIFT)}, | |
74 | }; | |
75 | ||
15545026 | 76 | static unsigned long s5p64x0_armclk_get_rate(struct clk *clk) |
3109e550 KK |
77 | { |
78 | unsigned long rate = clk_get_rate(clk->parent); | |
79 | u32 clkdiv; | |
80 | ||
81 | /* divisor mask starts at bit0, so no need to shift */ | |
82 | clkdiv = __raw_readl(ARM_CLK_DIV) & ARM_DIV_MASK; | |
83 | ||
84 | return rate / (clkdiv + 1); | |
85 | } | |
86 | ||
15545026 KK |
87 | static unsigned long s5p64x0_armclk_round_rate(struct clk *clk, |
88 | unsigned long rate) | |
3109e550 KK |
89 | { |
90 | u32 iter; | |
91 | ||
92 | for (iter = 1 ; iter < ARRAY_SIZE(clock_table) ; iter++) { | |
93 | if (rate > clock_table[iter][0]) | |
94 | return clock_table[iter-1][0]; | |
95 | } | |
96 | ||
97 | return clock_table[ARRAY_SIZE(clock_table) - 1][0]; | |
98 | } | |
99 | ||
15545026 | 100 | static int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate) |
3109e550 KK |
101 | { |
102 | u32 round_tmp; | |
103 | u32 iter; | |
104 | u32 clk_div0_tmp; | |
105 | u32 cur_rate = clk->ops->get_rate(clk); | |
106 | unsigned long flags; | |
107 | ||
108 | round_tmp = clk->ops->round_rate(clk, rate); | |
109 | if (round_tmp == cur_rate) | |
110 | return 0; | |
111 | ||
112 | ||
113 | for (iter = 0 ; iter < ARRAY_SIZE(clock_table) ; iter++) { | |
114 | if (round_tmp == clock_table[iter][0]) | |
115 | break; | |
116 | } | |
117 | ||
118 | if (iter >= ARRAY_SIZE(clock_table)) | |
119 | iter = ARRAY_SIZE(clock_table) - 1; | |
120 | ||
121 | local_irq_save(flags); | |
122 | if (cur_rate > round_tmp) { | |
123 | /* Frequency Down */ | |
124 | clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK); | |
125 | clk_div0_tmp |= clock_table[iter][1]; | |
126 | __raw_writel(clk_div0_tmp, ARM_CLK_DIV); | |
127 | ||
128 | clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & | |
129 | ~(S5P64X0_CLKDIV0_HCLK_MASK); | |
130 | clk_div0_tmp |= clock_table[iter][2]; | |
131 | __raw_writel(clk_div0_tmp, ARM_CLK_DIV); | |
132 | ||
133 | ||
134 | } else { | |
135 | /* Frequency Up */ | |
136 | clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & | |
137 | ~(S5P64X0_CLKDIV0_HCLK_MASK); | |
138 | clk_div0_tmp |= clock_table[iter][2]; | |
139 | __raw_writel(clk_div0_tmp, ARM_CLK_DIV); | |
140 | ||
141 | clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK); | |
142 | clk_div0_tmp |= clock_table[iter][1]; | |
143 | __raw_writel(clk_div0_tmp, ARM_CLK_DIV); | |
144 | } | |
145 | local_irq_restore(flags); | |
146 | ||
147 | clk->rate = clock_table[iter][0]; | |
148 | ||
149 | return 0; | |
150 | } | |
151 | ||
15545026 | 152 | static struct clk_ops s5p64x0_clkarm_ops = { |
3109e550 KK |
153 | .get_rate = s5p64x0_armclk_get_rate, |
154 | .set_rate = s5p64x0_armclk_set_rate, | |
155 | .round_rate = s5p64x0_armclk_round_rate, | |
156 | }; | |
157 | ||
158 | struct clksrc_clk clk_armclk = { | |
159 | .clk = { | |
160 | .name = "armclk", | |
161 | .id = 1, | |
162 | .parent = &clk_mout_apll.clk, | |
163 | .ops = &s5p64x0_clkarm_ops, | |
164 | }, | |
165 | .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 0, .size = 4 }, | |
166 | }; | |
167 | ||
168 | struct clksrc_clk clk_dout_mpll = { | |
169 | .clk = { | |
170 | .name = "dout_mpll", | |
171 | .id = -1, | |
172 | .parent = &clk_mout_mpll.clk, | |
173 | }, | |
174 | .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 4, .size = 1 }, | |
175 | }; | |
176 | ||
15545026 | 177 | static struct clk *clkset_hclk_low_list[] = { |
3109e550 KK |
178 | &clk_mout_apll.clk, |
179 | &clk_mout_mpll.clk, | |
180 | }; | |
181 | ||
182 | struct clksrc_sources clkset_hclk_low = { | |
183 | .sources = clkset_hclk_low_list, | |
184 | .nr_sources = ARRAY_SIZE(clkset_hclk_low_list), | |
185 | }; | |
186 | ||
187 | int s5p64x0_pclk_ctrl(struct clk *clk, int enable) | |
188 | { | |
189 | return s5p_gatectrl(S5P64X0_CLK_GATE_PCLK, clk, enable); | |
190 | } | |
191 | ||
192 | int s5p64x0_hclk0_ctrl(struct clk *clk, int enable) | |
193 | { | |
194 | return s5p_gatectrl(S5P64X0_CLK_GATE_HCLK0, clk, enable); | |
195 | } | |
196 | ||
197 | int s5p64x0_hclk1_ctrl(struct clk *clk, int enable) | |
198 | { | |
199 | return s5p_gatectrl(S5P64X0_CLK_GATE_HCLK1, clk, enable); | |
200 | } | |
201 | ||
202 | int s5p64x0_sclk_ctrl(struct clk *clk, int enable) | |
203 | { | |
204 | return s5p_gatectrl(S5P64X0_CLK_GATE_SCLK0, clk, enable); | |
205 | } | |
206 | ||
207 | int s5p64x0_sclk1_ctrl(struct clk *clk, int enable) | |
208 | { | |
209 | return s5p_gatectrl(S5P64X0_CLK_GATE_SCLK1, clk, enable); | |
210 | } | |
211 | ||
212 | int s5p64x0_mem_ctrl(struct clk *clk, int enable) | |
213 | { | |
214 | return s5p_gatectrl(S5P64X0_CLK_GATE_MEM0, clk, enable); | |
215 | } | |
216 | ||
217 | int s5p64x0_clk48m_ctrl(struct clk *clk, int enable) | |
218 | { | |
219 | unsigned long flags; | |
220 | u32 val; | |
221 | ||
222 | /* can't rely on clock lock, this register has other usages */ | |
223 | local_irq_save(flags); | |
224 | ||
225 | val = __raw_readl(S5P64X0_OTHERS); | |
226 | if (enable) | |
227 | val |= S5P64X0_OTHERS_USB_SIG_MASK; | |
228 | else | |
229 | val &= ~S5P64X0_OTHERS_USB_SIG_MASK; | |
230 | ||
231 | __raw_writel(val, S5P64X0_OTHERS); | |
232 | ||
233 | local_irq_restore(flags); | |
234 | ||
235 | return 0; | |
236 | } |