[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-s3c6410 / mach-smdk6410.c

/* linux/arch/arm/mach-s3c6410/mach-smdk6410.c
 *
 * Copyright 2008 Openmoko, Inc.
 * Copyright 2008 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *	http://armlinux.simtec.co.uk/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
*/

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/i2c.h>
#include <linux/fb.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/smsc911x.h>
#include <linux/regulator/fixed.h>

#ifdef CONFIG_SMDK6410_WM1190_EV1
#include <linux/mfd/wm8350/core.h>
#include <linux/mfd/wm8350/pmic.h>
#endif

#include <video/platform_lcd.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include <mach/hardware.h>
#include <mach/regs-fb.h>
#include <mach/map.h>

#include <asm/irq.h>
#include <asm/mach-types.h>

#include <plat/regs-serial.h>
#include <plat/regs-modem.h>
#include <plat/regs-gpio.h>
#include <plat/regs-sys.h>
#include <plat/regs-srom.h>
#include <plat/iic.h>
#include <plat/fb.h>
#include <plat/gpio-cfg.h>

#include <plat/s3c6410.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>

#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE

static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = {
	[0] = {
		.hwport	     = 0,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
	},
	[1] = {
		.hwport	     = 1,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
	},
	[2] = {
		.hwport	     = 2,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
	},
	[3] = {
		.hwport	     = 3,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
	},
};

/* framebuffer and LCD setup. */

/* GPF15 = LCD backlight control
 * GPF13 => Panel power
 * GPN5 = LCD nRESET signal
 * PWM_TOUT1 => backlight brightness
 */

static void smdk6410_lcd_power_set(struct plat_lcd_data *pd,
				   unsigned int power)
{
	if (power) {
		gpio_direction_output(S3C64XX_GPF(13), 1);
		gpio_direction_output(S3C64XX_GPF(15), 1);

		/* fire nRESET on power up */
		gpio_direction_output(S3C64XX_GPN(5), 0);
		msleep(10);
		gpio_direction_output(S3C64XX_GPN(5), 1);
		msleep(1);
	} else {
		gpio_direction_output(S3C64XX_GPF(15), 0);
		gpio_direction_output(S3C64XX_GPF(13), 0);
	}
}

static struct plat_lcd_data smdk6410_lcd_power_data = {
	.set_power	= smdk6410_lcd_power_set,
};

static struct platform_device smdk6410_lcd_powerdev = {
	.name			= "platform-lcd",
	.dev.parent		= &s3c_device_fb.dev,
	.dev.platform_data	= &smdk6410_lcd_power_data,
};

static struct s3c_fb_pd_win smdk6410_fb_win0 = {
	/* this is to ensure we use win0 */
	.win_mode	= {
		.pixclock	= 41094,
		.left_margin	= 8,
		.right_margin	= 13,
		.upper_margin	= 7,
		.lower_margin	= 5,
		.hsync_len	= 3,
		.vsync_len	= 1,
		.xres		= 800,
		.yres		= 480,
	},
	.max_bpp	= 32,
	.default_bpp	= 16,
};

/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
	.win[0]		= &smdk6410_fb_win0,
	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
};

/*
 * Configuring Ethernet on SMDK6410
 *
 * Both CS8900A and LAN9115 chips share one chip select mediated by CFG6.
 * The constant address below corresponds to nCS1
 *
 *  1) Set CFGB2 p3 ON others off, no other CFGB selects "ethernet"
 *  2) CFG6 needs to be switched to "LAN9115" side
 */

static struct resource smdk6410_smsc911x_resources[] = {
	[0] = {
		.start = S3C64XX_PA_XM0CSN1,
		.end   = S3C64XX_PA_XM0CSN1 + SZ_64K - 1,
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.start = S3C_EINT(10),
		.end   = S3C_EINT(10),
		.flags = IORESOURCE_IRQ | IRQ_TYPE_LEVEL_LOW,
	},
};

static struct smsc911x_platform_config smdk6410_smsc911x_pdata = {
	.irq_polarity  = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
	.irq_type      = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
	.flags         = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
	.phy_interface = PHY_INTERFACE_MODE_MII,
};


static struct platform_device smdk6410_smsc911x = {
	.name          = "smsc911x",
	.id            = -1,
	.num_resources = ARRAY_SIZE(smdk6410_smsc911x_resources),
	.resource      = &smdk6410_smsc911x_resources[0],
	.dev = {
		.platform_data = &smdk6410_smsc911x_pdata,
	},
};

#ifdef CONFIG_REGULATOR
static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] = {
	{
		/* WM8580 */
		.supply = "PVDD",
		.dev_name = "0-001b",
	},
	{
		/* WM8580 */
		.supply = "AVDD",
		.dev_name = "0-001b",
	},
};

static struct regulator_init_data smdk6410_b_pwr_5v_data = {
	.constraints = {
		.always_on = 1,
	},
	.num_consumer_supplies = ARRAY_SIZE(smdk6410_b_pwr_5v_consumers),
	.consumer_supplies = smdk6410_b_pwr_5v_consumers,
};

static struct fixed_voltage_config smdk6410_b_pwr_5v_pdata = {
	.supply_name = "B_PWR_5V",
	.microvolts = 5000000,
	.init_data = &smdk6410_b_pwr_5v_data,
	.gpio = -EINVAL,
};

static struct platform_device smdk6410_b_pwr_5v = {
	.name          = "reg-fixed-voltage",
	.id            = -1,
	.dev = {
		.platform_data = &smdk6410_b_pwr_5v_pdata,
	},
};
#endif

static struct map_desc smdk6410_iodesc[] = {};

static struct platform_device *smdk6410_devices[] __initdata = {
#ifdef CONFIG_SMDK6410_SD_CH0
	&s3c_device_hsmmc0,
#endif
#ifdef CONFIG_SMDK6410_SD_CH1
	&s3c_device_hsmmc1,
#endif
	&s3c_device_i2c0,
	&s3c_device_i2c1,
	&s3c_device_fb,
	&s3c_device_ohci,
	&s3c_device_usb_hsotg,

#ifdef CONFIG_REGULATOR
	&smdk6410_b_pwr_5v,
#endif
	&smdk6410_lcd_powerdev,

	&smdk6410_smsc911x,
};

#ifdef CONFIG_SMDK6410_WM1190_EV1
/* S3C64xx internal logic & PLL */
static struct regulator_init_data wm8350_dcdc1_data = {
	.constraints = {
		.name = "PVDD_INT/PVDD_PLL",
		.min_uV = 1200000,
		.max_uV = 1200000,
		.always_on = 1,
		.apply_uV = 1,
	},
};

/* Memory */
static struct regulator_init_data wm8350_dcdc3_data = {
	.constraints = {
		.name = "PVDD_MEM",
		.min_uV = 1800000,
		.max_uV = 1800000,
		.always_on = 1,
		.state_mem = {
			 .uV = 1800000,
			 .mode = REGULATOR_MODE_NORMAL,
			 .enabled = 1,
		 },
		.initial_state = PM_SUSPEND_MEM,
	},
};

/* USB, EXT, PCM, ADC/DAC, USB, MMC */
static struct regulator_consumer_supply wm8350_dcdc4_consumers[] = {
	{
		/* WM8580 */
		.supply = "DVDD",
		.dev_name = "0-001b",
	},
};

static struct regulator_init_data wm8350_dcdc4_data = {
	.constraints = {
		.name = "PVDD_HI/PVDD_EXT/PVDD_SYS/PVCCM2MTV",
		.min_uV = 3000000,
		.max_uV = 3000000,
		.always_on = 1,
	},
	.num_consumer_supplies = ARRAY_SIZE(wm8350_dcdc4_consumers),
	.consumer_supplies = wm8350_dcdc4_consumers,
};

/* ARM core */
static struct regulator_consumer_supply dcdc6_consumers[] = {
	{
		.supply = "vddarm",
	}
};

static struct regulator_init_data wm8350_dcdc6_data = {
	.constraints = {
		.name = "PVDD_ARM",
		.min_uV = 1000000,
		.max_uV = 1300000,
		.always_on = 1,
		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
	},
	.num_consumer_supplies = ARRAY_SIZE(dcdc6_consumers),
	.consumer_supplies = dcdc6_consumers,
};

/* Alive */
static struct regulator_init_data wm8350_ldo1_data = {
	.constraints = {
		.name = "PVDD_ALIVE",
		.min_uV = 1200000,
		.max_uV = 1200000,
		.always_on = 1,
		.apply_uV = 1,
	},
};

/* OTG */
static struct regulator_init_data wm8350_ldo2_data = {
	.constraints = {
		.name = "PVDD_OTG",
		.min_uV = 3300000,
		.max_uV = 3300000,
		.always_on = 1,
	},
};

/* LCD */
static struct regulator_init_data wm8350_ldo3_data = {
	.constraints = {
		.name = "PVDD_LCD",
		.min_uV = 3000000,
		.max_uV = 3000000,
		.always_on = 1,
	},
};

/* OTGi/1190-EV1 HPVDD & AVDD */
static struct regulator_init_data wm8350_ldo4_data = {
	.constraints = {
		.name = "PVDD_OTGI/HPVDD/AVDD",
		.min_uV = 1200000,
		.max_uV = 1200000,
		.apply_uV = 1,
		.always_on = 1,
	},
};

static struct {
	int regulator;
	struct regulator_init_data *initdata;
} wm1190_regulators[] = {
	{ WM8350_DCDC_1, &wm8350_dcdc1_data },
	{ WM8350_DCDC_3, &wm8350_dcdc3_data },
	{ WM8350_DCDC_4, &wm8350_dcdc4_data },
	{ WM8350_DCDC_6, &wm8350_dcdc6_data },
	{ WM8350_LDO_1, &wm8350_ldo1_data },
	{ WM8350_LDO_2, &wm8350_ldo2_data },
	{ WM8350_LDO_3, &wm8350_ldo3_data },
	{ WM8350_LDO_4, &wm8350_ldo4_data },
};

static int __init smdk6410_wm8350_init(struct wm8350 *wm8350)
{
	int i;

	/* Configure the IRQ line */
	s3c_gpio_setpull(S3C64XX_GPN(12), S3C_GPIO_PULL_UP);

	/* Instantiate the regulators */
	for (i = 0; i < ARRAY_SIZE(wm1190_regulators); i++)
		wm8350_register_regulator(wm8350,
					  wm1190_regulators[i].regulator,
					  wm1190_regulators[i].initdata);

	return 0;
}

static struct wm8350_platform_data __initdata smdk6410_wm8350_pdata = {
	.init = smdk6410_wm8350_init,
	.irq_high = 1,
	.irq_base = IRQ_BOARD_START,
};
#endif

static struct i2c_board_info i2c_devs0[] __initdata = {
	{ I2C_BOARD_INFO("24c08", 0x50), },
	{ I2C_BOARD_INFO("wm8580", 0x1b), },

#ifdef CONFIG_SMDK6410_WM1190_EV1
	{ I2C_BOARD_INFO("wm8350", 0x1a),
	  .platform_data = &smdk6410_wm8350_pdata,
	  .irq = S3C_EINT(12),
	},
#endif
};

static struct i2c_board_info i2c_devs1[] __initdata = {
	{ I2C_BOARD_INFO("24c128", 0x57), },	/* Samsung S524AD0XD1 */
};

static void __init smdk6410_map_io(void)
{
	u32 tmp;

	s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
	s3c24xx_init_clocks(12000000);
	s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));

	/* set the LCD type */

	tmp = __raw_readl(S3C64XX_SPCON);
	tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
	tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
	__raw_writel(tmp, S3C64XX_SPCON);

	/* remove the lcd bypass */
	tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
	tmp &= ~MIFPCON_LCD_BYPASS;
	__raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
}

static void __init smdk6410_machine_init(void)
{
	u32 cs1;

	s3c_i2c0_set_platdata(NULL);
	s3c_i2c1_set_platdata(NULL);
	s3c_fb_set_platdata(&smdk6410_lcd_pdata);

	/* configure nCS1 width to 16 bits */

	cs1 = __raw_readl(S3C64XX_SROM_BW) &
		    ~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
	cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) |
		(1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) |
		(1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
						   S3C64XX_SROM_BW__NCS1__SHIFT;
	__raw_writel(cs1, S3C64XX_SROM_BW);

	/* set timing for nCS1 suitable for ethernet chip */

	__raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
		     (6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
		     (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
		     (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
		     (0xe << S3C64XX_SROM_BCX__TACC__SHIFT) |
		     (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
		     (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);

	gpio_request(S3C64XX_GPN(5), "LCD power");
	gpio_request(S3C64XX_GPF(13), "LCD power");
	gpio_request(S3C64XX_GPF(15), "LCD power");

	i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));

	platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices));
}

MACHINE_START(SMDK6410, "SMDK6410")
	/* Maintainer: Ben Dooks <ben@fluff.org> */
	.phys_io	= S3C_PA_UART & 0xfff00000,
	.io_pg_offst	= (((u32)S3C_VA_UART) >> 18) & 0xfffc,
	.boot_params	= S3C64XX_PA_SDRAM + 0x100,

	.init_irq	= s3c6410_init_irq,
	.map_io		= smdk6410_map_io,
	.init_machine	= smdk6410_machine_init,
	.timer		= &s3c24xx_timer,
MACHINE_END
Commit	Line	Data
5718df9d BD	1	/* linux/arch/arm/mach-s3c6410/mach-smdk6410.c
	2	*
	3	* Copyright 2008 Openmoko, Inc.
	4	* Copyright 2008 Simtec Electronics
	5	* Ben Dooks <ben@simtec.co.uk>
	6	* http://armlinux.simtec.co.uk/
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/types.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/list.h>
	18	#include <linux/timer.h>
	19	#include <linux/init.h>
	20	#include <linux/serial_core.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/io.h>
096941ed	23	#include <linux/i2c.h>
438a5d42 BD	24	#include <linux/fb.h>
	25	#include <linux/gpio.h>
	26	#include <linux/delay.h>
3056ea0a	27	#include <linux/smsc911x.h>
42015c13	28	#include <linux/regulator/fixed.h>
438a5d42	29
ecc558ac MB	30	#ifdef CONFIG_SMDK6410_WM1190_EV1
	31	#include <linux/mfd/wm8350/core.h>
	32	#include <linux/mfd/wm8350/pmic.h>
	33	#endif
438a5d42 BD	34
438a5d42 BD	35	#include <video/platform_lcd.h>
5718df9d BD	36
	37	#include <asm/mach/arch.h>
	38	#include <asm/mach/map.h>
	39	#include <asm/mach/irq.h>
	40
	41	#include <mach/hardware.h>
438a5d42	42	#include <mach/regs-fb.h>
5718df9d BD	43	#include <mach/map.h>
	44
	45	#include <asm/irq.h>
	46	#include <asm/mach-types.h>
	47
	48	#include <plat/regs-serial.h>
d6662c35 BD	49	#include <plat/regs-modem.h>
	50	#include <plat/regs-gpio.h>
	51	#include <plat/regs-sys.h>
f01fdac0	52	#include <plat/regs-srom.h>
d85fa24c	53	#include <plat/iic.h>
438a5d42	54	#include <plat/fb.h>
3056ea0a	55	#include <plat/gpio-cfg.h>
5718df9d BD	56
	57	#include <plat/s3c6410.h>
	58	#include <plat/clock.h>
	59	#include <plat/devs.h>
	60	#include <plat/cpu.h>
	61
	62	#define UCON S3C2410_UCON_DEFAULT \| S3C2410_UCON_UCLK
	63	#define ULCON S3C2410_LCON_CS8 \| S3C2410_LCON_PNONE \| S3C2410_LCON_STOPB
	64	#define UFCON S3C2410_UFCON_RXTRIG8 \| S3C2410_UFCON_FIFOMODE
	65
	66	static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = {
	67	[0] = {
	68	.hwport = 0,
	69	.flags = 0,
bd258e52 MH	70	.ucon = UCON,
	71	.ulcon = ULCON,
	72	.ufcon = UFCON,
5718df9d BD	73	},
	74	[1] = {
	75	.hwport = 1,
	76	.flags = 0,
bd258e52 MH	77	.ucon = UCON,
	78	.ulcon = ULCON,
	79	.ufcon = UFCON,
	80	},
	81	[2] = {
	82	.hwport = 2,
	83	.flags = 0,
	84	.ucon = UCON,
	85	.ulcon = ULCON,
	86	.ufcon = UFCON,
	87	},
	88	[3] = {
	89	.hwport = 3,
	90	.flags = 0,
	91	.ucon = UCON,
	92	.ulcon = ULCON,
	93	.ufcon = UFCON,
5718df9d BD	94	},
	95	};
	96
438a5d42 BD	97	/* framebuffer and LCD setup. */
	98
	99	/* GPF15 = LCD backlight control
	100	* GPF13 => Panel power
	101	* GPN5 = LCD nRESET signal
	102	* PWM_TOUT1 => backlight brightness
	103	*/
	104
	105	static void smdk6410_lcd_power_set(struct plat_lcd_data *pd,
	106	unsigned int power)
	107	{
	108	if (power) {
	109	gpio_direction_output(S3C64XX_GPF(13), 1);
	110	gpio_direction_output(S3C64XX_GPF(15), 1);
	111
	112	/* fire nRESET on power up */
	113	gpio_direction_output(S3C64XX_GPN(5), 0);
	114	msleep(10);
	115	gpio_direction_output(S3C64XX_GPN(5), 1);
	116	msleep(1);
	117	} else {
	118	gpio_direction_output(S3C64XX_GPF(15), 0);
	119	gpio_direction_output(S3C64XX_GPF(13), 0);
	120	}
	121	}
	122
	123	static struct plat_lcd_data smdk6410_lcd_power_data = {
	124	.set_power = smdk6410_lcd_power_set,
	125	};
	126
	127	static struct platform_device smdk6410_lcd_powerdev = {
	128	.name = "platform-lcd",
	129	.dev.parent = &s3c_device_fb.dev,
	130	.dev.platform_data = &smdk6410_lcd_power_data,
	131	};
	132
	133	static struct s3c_fb_pd_win smdk6410_fb_win0 = {
	134	/* this is to ensure we use win0 */
	135	.win_mode = {
	136	.pixclock = 41094,
	137	.left_margin = 8,
	138	.right_margin = 13,
	139	.upper_margin = 7,
	140	.lower_margin = 5,
	141	.hsync_len = 3,
	142	.vsync_len = 1,
	143	.xres = 800,
	144	.yres = 480,
	145	},
	146	.max_bpp = 32,
	147	.default_bpp = 16,
	148	};
	149
	150	/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
	151	static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
	152	.setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
	153	.win[0] = &smdk6410_fb_win0,
	154	.vidcon0 = VIDCON0_VIDOUT_RGB \| VIDCON0_PNRMODE_RGB,
	155	.vidcon1 = VIDCON1_INV_HSYNC \| VIDCON1_INV_VSYNC,
	156	};
	157
a4e94694 AG	158	/*
	159	* Configuring Ethernet on SMDK6410
	160	*
	161	* Both CS8900A and LAN9115 chips share one chip select mediated by CFG6.
	162	* The constant address below corresponds to nCS1
	163	*
	164	* 1) Set CFGB2 p3 ON others off, no other CFGB selects "ethernet"
	165	* 2) CFG6 needs to be switched to "LAN9115" side
	166	*/
	167
3056ea0a MB	168	static struct resource smdk6410_smsc911x_resources[] = {
3056ea0a MB	169	[0] = {
f01fdac0 AG	170	.start = S3C64XX_PA_XM0CSN1,
f01fdac0 AG	171	.end = S3C64XX_PA_XM0CSN1 + SZ_64K - 1,
3056ea0a MB	172	.flags = IORESOURCE_MEM,
	173	},
	174	[1] = {
	175	.start = S3C_EINT(10),
	176	.end = S3C_EINT(10),
	177	.flags = IORESOURCE_IRQ \| IRQ_TYPE_LEVEL_LOW,
	178	},
	179	};
	180
	181	static struct smsc911x_platform_config smdk6410_smsc911x_pdata = {
	182	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
	183	.irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
	184	.flags = SMSC911X_USE_32BIT \| SMSC911X_FORCE_INTERNAL_PHY,
	185	.phy_interface = PHY_INTERFACE_MODE_MII,
	186	};
	187
	188
	189	static struct platform_device smdk6410_smsc911x = {
	190	.name = "smsc911x",
	191	.id = -1,
	192	.num_resources = ARRAY_SIZE(smdk6410_smsc911x_resources),
	193	.resource = &smdk6410_smsc911x_resources[0],
	194	.dev = {
	195	.platform_data = &smdk6410_smsc911x_pdata,
	196	},
	197	};
	198
42015c13 MB	199	#ifdef CONFIG_REGULATOR
	200	static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] = {
	201	{
	202	/* WM8580 */
	203	.supply = "PVDD",
	204	.dev_name = "0-001b",
	205	},
	206	{
	207	/* WM8580 */
	208	.supply = "AVDD",
	209	.dev_name = "0-001b",
	210	},
	211	};
	212
	213	static struct regulator_init_data smdk6410_b_pwr_5v_data = {
	214	.constraints = {
	215	.always_on = 1,
	216	},
	217	.num_consumer_supplies = ARRAY_SIZE(smdk6410_b_pwr_5v_consumers),
	218	.consumer_supplies = smdk6410_b_pwr_5v_consumers,
	219	};
	220
	221	static struct fixed_voltage_config smdk6410_b_pwr_5v_pdata = {
	222	.supply_name = "B_PWR_5V",
	223	.microvolts = 5000000,
	224	.init_data = &smdk6410_b_pwr_5v_data,
d3cf4489	225	.gpio = -EINVAL,
42015c13 MB	226	};
	227
	228	static struct platform_device smdk6410_b_pwr_5v = {
	229	.name = "reg-fixed-voltage",
	230	.id = -1,
	231	.dev = {
	232	.platform_data = &smdk6410_b_pwr_5v_pdata,
	233	},
	234	};
	235	#endif
	236
027191a8	237	static struct map_desc smdk6410_iodesc[] = {};
5718df9d BD	238
5718df9d BD	239	static struct platform_device *smdk6410_devices[] __initdata = {
b24636cf	240	#ifdef CONFIG_SMDK6410_SD_CH0
39057f23	241	&s3c_device_hsmmc0,
b24636cf BD	242	#endif
	243	#ifdef CONFIG_SMDK6410_SD_CH1
	244	&s3c_device_hsmmc1,
	245	#endif
d85fa24c	246	&s3c_device_i2c0,
d7ea3743	247	&s3c_device_i2c1,
438a5d42	248	&s3c_device_fb,
b813248c	249	&s3c_device_ohci,
06fa1d37	250	&s3c_device_usb_hsotg,
42015c13 MB	251
	252	#ifdef CONFIG_REGULATOR
	253	&smdk6410_b_pwr_5v,
	254	#endif
438a5d42	255	&smdk6410_lcd_powerdev,
3056ea0a MB	256
3056ea0a MB	257	&smdk6410_smsc911x,
5718df9d BD	258	};
5718df9d BD	259
ecc558ac MB	260	#ifdef CONFIG_SMDK6410_WM1190_EV1
	261	/* S3C64xx internal logic & PLL */
	262	static struct regulator_init_data wm8350_dcdc1_data = {
	263	.constraints = {
	264	.name = "PVDD_INT/PVDD_PLL",
	265	.min_uV = 1200000,
	266	.max_uV = 1200000,
	267	.always_on = 1,
	268	.apply_uV = 1,
	269	},
	270	};
	271
	272	/* Memory */
	273	static struct regulator_init_data wm8350_dcdc3_data = {
	274	.constraints = {
	275	.name = "PVDD_MEM",
	276	.min_uV = 1800000,
	277	.max_uV = 1800000,
	278	.always_on = 1,
	279	.state_mem = {
	280	.uV = 1800000,
	281	.mode = REGULATOR_MODE_NORMAL,
	282	.enabled = 1,
	283	},
	284	.initial_state = PM_SUSPEND_MEM,
	285	},
	286	};
	287
	288	/* USB, EXT, PCM, ADC/DAC, USB, MMC */
42015c13 MB	289	static struct regulator_consumer_supply wm8350_dcdc4_consumers[] = {
	290	{
	291	/* WM8580 */
	292	.supply = "DVDD",
	293	.dev_name = "0-001b",
	294	},
	295	};
	296
ecc558ac MB	297	static struct regulator_init_data wm8350_dcdc4_data = {
	298	.constraints = {
	299	.name = "PVDD_HI/PVDD_EXT/PVDD_SYS/PVCCM2MTV",
	300	.min_uV = 3000000,
	301	.max_uV = 3000000,
	302	.always_on = 1,
	303	},
42015c13 MB	304	.num_consumer_supplies = ARRAY_SIZE(wm8350_dcdc4_consumers),
42015c13 MB	305	.consumer_supplies = wm8350_dcdc4_consumers,
ecc558ac MB	306	};
	307
	308	/* ARM core */
e3980b6a MB	309	static struct regulator_consumer_supply dcdc6_consumers[] = {
	310	{
	311	.supply = "vddarm",
	312	}
	313	};
	314
ecc558ac MB	315	static struct regulator_init_data wm8350_dcdc6_data = {
	316	.constraints = {
	317	.name = "PVDD_ARM",
	318	.min_uV = 1000000,
	319	.max_uV = 1300000,
	320	.always_on = 1,
e3980b6a	321	.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
ecc558ac	322	},
e3980b6a MB	323	.num_consumer_supplies = ARRAY_SIZE(dcdc6_consumers),
e3980b6a MB	324	.consumer_supplies = dcdc6_consumers,
5718df9d BD	325	};
5718df9d BD	326
ecc558ac MB	327	/* Alive */
	328	static struct regulator_init_data wm8350_ldo1_data = {
	329	.constraints = {
	330	.name = "PVDD_ALIVE",
	331	.min_uV = 1200000,
	332	.max_uV = 1200000,
	333	.always_on = 1,
	334	.apply_uV = 1,
	335	},
	336	};
	337
	338	/* OTG */
	339	static struct regulator_init_data wm8350_ldo2_data = {
	340	.constraints = {
	341	.name = "PVDD_OTG",
	342	.min_uV = 3300000,
	343	.max_uV = 3300000,
f53aee29	344	.always_on = 1,
ecc558ac MB	345	},
	346	};
	347
	348	/* LCD */
	349	static struct regulator_init_data wm8350_ldo3_data = {
	350	.constraints = {
	351	.name = "PVDD_LCD",
	352	.min_uV = 3000000,
	353	.max_uV = 3000000,
f53aee29	354	.always_on = 1,
ecc558ac MB	355	},
	356	};
	357
	358	/* OTGi/1190-EV1 HPVDD & AVDD */
	359	static struct regulator_init_data wm8350_ldo4_data = {
	360	.constraints = {
	361	.name = "PVDD_OTGI/HPVDD/AVDD",
	362	.min_uV = 1200000,
	363	.max_uV = 1200000,
	364	.apply_uV = 1,
f53aee29	365	.always_on = 1,
ecc558ac MB	366	},
	367	};
	368
	369	static struct {
	370	int regulator;
	371	struct regulator_init_data *initdata;
	372	} wm1190_regulators[] = {
	373	{ WM8350_DCDC_1, &wm8350_dcdc1_data },
	374	{ WM8350_DCDC_3, &wm8350_dcdc3_data },
	375	{ WM8350_DCDC_4, &wm8350_dcdc4_data },
	376	{ WM8350_DCDC_6, &wm8350_dcdc6_data },
	377	{ WM8350_LDO_1, &wm8350_ldo1_data },
	378	{ WM8350_LDO_2, &wm8350_ldo2_data },
	379	{ WM8350_LDO_3, &wm8350_ldo3_data },
	380	{ WM8350_LDO_4, &wm8350_ldo4_data },
	381	};
	382
	383	static int __init smdk6410_wm8350_init(struct wm8350 *wm8350)
	384	{
	385	int i;
	386
a3323b72 MB	387	/* Configure the IRQ line */
	388	s3c_gpio_setpull(S3C64XX_GPN(12), S3C_GPIO_PULL_UP);
	389
ecc558ac MB	390	/* Instantiate the regulators */
	391	for (i = 0; i < ARRAY_SIZE(wm1190_regulators); i++)
	392	wm8350_register_regulator(wm8350,
	393	wm1190_regulators[i].regulator,
	394	wm1190_regulators[i].initdata);
	395
	396	return 0;
	397	}
	398
	399	static struct wm8350_platform_data __initdata smdk6410_wm8350_pdata = {
	400	.init = smdk6410_wm8350_init,
db9256f3	401	.irq_high = 1,
9fca8786	402	.irq_base = IRQ_BOARD_START,
ecc558ac MB	403	};
	404	#endif
	405
096941ed BD	406	static struct i2c_board_info i2c_devs0[] __initdata = {
096941ed BD	407	{ I2C_BOARD_INFO("24c08", 0x50), },
77897479	408	{ I2C_BOARD_INFO("wm8580", 0x1b), },
ecc558ac MB	409
	410	#ifdef CONFIG_SMDK6410_WM1190_EV1
	411	{ I2C_BOARD_INFO("wm8350", 0x1a),
	412	.platform_data = &smdk6410_wm8350_pdata,
	413	.irq = S3C_EINT(12),
	414	},
	415	#endif
096941ed BD	416	};
	417
	418	static struct i2c_board_info i2c_devs1[] __initdata = {
	419	{ I2C_BOARD_INFO("24c128", 0x57), }, /* Samsung S524AD0XD1 */
5718df9d BD	420	};
5718df9d BD	421
5718df9d BD	422	static void __init smdk6410_map_io(void)
5718df9d BD	423	{
d6662c35 BD	424	u32 tmp;
d6662c35 BD	425
5718df9d BD	426	s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
	427	s3c24xx_init_clocks(12000000);
	428	s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
d6662c35 BD	429
	430	/* set the LCD type */
	431
	432	tmp = __raw_readl(S3C64XX_SPCON);
	433	tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
	434	tmp \|= S3C64XX_SPCON_LCD_SEL_RGB;
	435	__raw_writel(tmp, S3C64XX_SPCON);
	436
	437	/* remove the lcd bypass */
	438	tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
	439	tmp &= ~MIFPCON_LCD_BYPASS;
	440	__raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
5718df9d BD	441	}
	442
	443	static void __init smdk6410_machine_init(void)
	444	{
f01fdac0 AG	445	u32 cs1;
f01fdac0 AG	446
d85fa24c	447	s3c_i2c0_set_platdata(NULL);
d7ea3743	448	s3c_i2c1_set_platdata(NULL);
438a5d42	449	s3c_fb_set_platdata(&smdk6410_lcd_pdata);
096941ed	450
f01fdac0 AG	451	/* configure nCS1 width to 16 bits */
	452
	453	cs1 = __raw_readl(S3C64XX_SROM_BW) &
	454	~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
	455	cs1 \|= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) \|
	456	(1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) \|
	457	(1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
	458	S3C64XX_SROM_BW__NCS1__SHIFT;
	459	__raw_writel(cs1, S3C64XX_SROM_BW);
	460
	461	/* set timing for nCS1 suitable for ethernet chip */
	462
	463	__raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) \|
	464	(6 << S3C64XX_SROM_BCX__TACP__SHIFT) \|
	465	(4 << S3C64XX_SROM_BCX__TCAH__SHIFT) \|
	466	(1 << S3C64XX_SROM_BCX__TCOH__SHIFT) \|
	467	(0xe << S3C64XX_SROM_BCX__TACC__SHIFT) \|
	468	(4 << S3C64XX_SROM_BCX__TCOS__SHIFT) \|
	469	(0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
	470
b7f9a94b MB	471	gpio_request(S3C64XX_GPN(5), "LCD power");
	472	gpio_request(S3C64XX_GPF(13), "LCD power");
	473	gpio_request(S3C64XX_GPF(15), "LCD power");
	474
096941ed BD	475	i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
	476	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
	477
5718df9d BD	478	platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices));
	479	}
	480
	481	MACHINE_START(SMDK6410, "SMDK6410")
	482	/* Maintainer: Ben Dooks <ben@fluff.org> */
	483	.phys_io = S3C_PA_UART & 0xfff00000,
	484	.io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
	485	.boot_params = S3C64XX_PA_SDRAM + 0x100,
	486
	487	.init_irq = s3c6410_init_irq,
	488	.map_io = smdk6410_map_io,
	489	.init_machine = smdk6410_machine_init,
	490	.timer = &s3c24xx_timer,
	491	MACHINE_END